Advanced Materials Research Center and University Research Alex Oscilowski Vice President-Strategy SEMATECH
SEMATECH and University Research Key Partnership Models to Facilitate University Research: Advanced Materials Research Center (AMRC) Semiconductor Research Corporation (SRC) Engineering Research Center (ERC) for Benign Semiconductor Manufacturing
Advanced Materials Research Center (AMRC) University R&D partnership - accelerating commercialization of university research Government Texas Universities Selected Semiconductors Programs Select programs in: Semiconductors, Nanotechnology Provides technology pipeline from universities through SEMATECH to industry Focus on future transistors, interconnects, patterning, metrology; emerging nanotechnology applications
AMRC Partnership with Texas SEMATECH / ATDF Microelectronics Research Center University of Texas at Austin Participating facilities include: SEMATECH/ATDF Microelectronics Research Center Texas Materials Institute Center for Nano & Molecular Science and Technology Provides technology pipeline to SEMATECH members Fundamental understanding High-quality students, technical skills SEMATECH members get IP rights
2004-05 AMRC University Programs Topic Details UT Lead Title Materials and Structures for Future Transistors Materials and Structures for Future Connectivity Patterning of Materials and Structures Metrology and Characterization of Materials and Structures Advanced CMOS Materials & Processes Beyond CMOS Novel Transistors Advanced Cu/Low-K Future Connectivity Gate Stack Materials Lee Kwong PVD High -K Dielectrics: Reliability Issues Understanding and Characterization of Key Issues Related to High-K Gate Dielectrics and Metal Gate Electrodes Register Modeling of Gate Stack Materials Channel Materials Banerjee Channel materials Ultra-Shallow Junctions Hwang Ultra Shallow Junctions Novel Transistors: Multi-gate SOI MOSFETS, FinFETs, New Transistors on Singh / Banerjee and Vertical MOSFETS Strained Silicon + SOI Register Transport Models for Strained Si and FinFETs NanoTechnology Dodabalapur Advanced Organic/Silicon Devices for Chemical and Biosensing Ekerdt Quantum Dot Floating Gate Flash Memories Barrier Materials/ Ultra Thin Diffusion Barrier and Pore Sealing Techniques Low-k Ekerdt / White for 45 nm and Beyond Nano-Conductors / Low-k Ho Nanoconductors for Future Interconnects 3-D Technology Neikirk Optical Interconnect Optical Detectors for Interconnect Common Resist for for 193 nm, e-beam, & Imprint Template R. Chen Deppe Campbell Holmes Measurement, Electrical Characterization, and Design Of Advanced Interconnects Optical On-Chip and Chip-to-Chip Interconnects Optical Interconnect Elements Optical Extension Immersion Lithography Willson / Bonnecaze / Shi Immersion Lithography - Fluids and Resists Functional Resist Willson / Ekerdt / Shi Functional Resists Nanotechnology Patterning Willson / Ekerdt / Shi Common Electron Beam Resists Field Assisted Lithography Willson / Sreenivasan Field Assisted Lithography Spectroscopic Methods for Profiling High-K Dielectric Films Downer and Nanometer-Scale SOI Structures Future Advanced CMOS Shih Dopant Profiling with STM Transistors Yacaman Transition Electron Microscopy Studies Beyond CMOS Campion Strain Measurement by Raman Spectroscopy Patterning Patterning & Standards Korgel Nanowires and Nanodots for Metrology Standards Defects De Lozzane STM Studies for Metrology
Higher-k Gate Dielectric (Prof. Dim-Lee Kwong) Results for HfTaTiO Studying potential for extension of Hf-based dielectrics 1st SEMATECH-AMRC higher-k material achieving sub-1.0nm results with good device properties K values > 40 obtained (HfO 2 ~ 20) Peak mobility similar to best FEP HfO 2 Ultra-thin equivalent oxide thickness ( 9Å) achieved through process optimization HfTaTiO nmosfet characteristics also studied Laminated HfTaTiO dielectric increases the crystallization temperature up to 900 o C
Functional Materials for Cost Reduction Direct formation of dual Damascene dielectric using imprint patterning (Prof. G. Willson) Imprinting multi-tier templates Integrating SFIL wafers into ATDF copper flow Developing new imprintable dielectric materials 1 st try 2 nd try Template improvements Multi-tier imprint in resist Copper/CMP dual Damascene test structure made in ATDF Cubic Silsesquioxane structures
Sensors Low Cost Organic Transistors (Prof. A. Dodabalapur) Change of transistor drain current 4 terminal transistor/sensor High sensitivity/selectivity Can be reset with low hysteresis (>70 cycles) AMRC IP disclosure/patent Δ on sweep # ddhα6t / 1-hexanol, on response 60 40 20 0 0.00-0.04 0.02 0.00-0.02-0.04-0.06-0.08 Analyte delivery -0.08 0 5 10 time (sec) 15 20 Ohmic Contacts (Al) Organic Source/Drain Contacts (Ag) Si0 2 Organic Si Source/Drain Semiconductor Si Source/Drain Contact (Ag) Si0 2 Gate Oxide Contact (Ag) + n Source/Drain (Si) n - channel doping Source/Drain (Si) n + p - Substrate (Si)
Nanowires Aberration Corrected HR-TEM Results (Prof. Korgel) 400,000 x 200 kev Simulated TEM images when [110] grown nanowire with {111} defect is viewed from various perspectives 10 nm Improved imaging: Au dot structure Epitaxy of Si nanowire on gold dot Nanowire Twinning New calibration mechanism for HR-TEM, and sub-35nm dimensional imaging
AMRC Status Year 1 (2004/05) Projects Impact 26 ongoing projects About 200 graduate students, post-docs, faculty, and staff being supported fully or in part by AMRC Assignees dedicated to AMRC projects Publications >100 Joint authorship by multiple AMRC faculty, industry partners and/or SEMATECH (>20) Invited papers IP University or joint invention disclosures Patent applications Member-proprietary reports and briefings
FEP Transition Center Semiconductor Research Corporation (SRC) $ Technology NCSU, Rutgers, Stanford, U. Albany, UT Austin, UT Dallas, UT Arlington, Texas A&M Univ., UCSB, OSU, Yale, Penn State Univ., DeMontfort Univ. U. of Washington. U. Minnesota, UCLA Purdue, UIUC, U. of Houston, Cornell, UC Berkeley, U. of Utah, U. of North Texas Funding Universities
FORCe II Factory Operations Research Center IC Makers Technology Suppliers Funding Academia Participating Universities Govt.
FORCe II Mission and Objectives Provide new concepts and capabilities for modeling and decision support to address the challenges of next-generation factories, including management of supply chain, fab operations, process control and yield Evaluate software/tools from research via member company pilot projects Understand more complex, integration-oriented areas to provide new concepts/methods to business owners Drive suppliers to provide capability via business owner department (direct customer) pull Plan commercialization projects in parallel with research as appropriate
FORCe II Projects Qin, Hasenbein University of Texas Austin Fab-wide Control and Disruption Management in High Volume Semiconductor Manufacturing Mastrangelo, Montgomery University of Washington / Arizona State Hierarchical Modeling of Yield and Defectivity to Improve Factory Operations Uzsoy Purdue University Incorporating Nonlinear Phenomena in Semiconductor Supply Chain Planning Models Ni University of Michigan Development of Predictive Modeling and Intelligent Decision Support Tools for the High Yield Next Generation Semiconductor Factories
FORCe II Projects Wu, Berger Lehigh University Demand Planning and Supply Chain Coordination in the Contract Mfgm. Environments Nelson, Fowler Northwestern Univ. / Arizona State Univ. Multi-product Cycle Time and Throughput Evaluation via Simulation on Demand Chou, Chen, Chang National Taiwan University Configuration, monitoring and control of semiconductor supply chain Raghavan Indian Institute of Science Models and Algorithms for Demand Planning and order allocation across high mix factories
Engineering Research Center for Environmentally Benign Semiconductor Manufacturing Mission Research to develop science and technology leading to simultaneous process performance/cost/esh gain Incorporating ESH principles in engineering and science education Promoting Design for Environment and sustainability as a technology driver and not a burden Chairman: Farhang Shadman, Univ. of Arizona
Participating Research Institutions University of Arizona MIT Stanford University UC Berkeley Cornell University Lincoln Laboratory University of Maryland Purdue University Founders 1996 Joined in 1998 New Partners
ERC Membership Core Members AMD* Chartered Semiconductor Freescale Semiconductor* IBM* Intel* LSI Logic* National Semiconductor* Texas Instruments* Adjunct Members HP Strategic Partners SEMATECH SEMI SRC * Companies that have traditionally participated in the ERC project selection process Science Area Members Axcelis Technologies Cadence Design Mentor Graphics Novellus Systems Rohm and Haas Associate Members The MITRE Corporation Affiliate Members PDF Solutions Government Participants DARPA, NSF, NIST, NY State, U.S. Dept. of Defense
ERC Program Organization Thrust A BEOL Processes Environmentally Benign Etching of BEOL Dielectrics Solventless Low-k Dielectric Novel Barrier Film Deposition Methods CMP Waste Minimization Environmentally Benign Planarization Thrust B FEOL Processes Thrust C Factory Integration Thrust D Patterning Education New Thrusts Novel Surface Cleaning and Passivation Selective Deposition for Gate Stack Manufacturing Etching of New High-k and Electrode Materials Low-Energy Water Purification and Wastewater Treatment Efficient Wafer Rinsing and Cleaning Water Recycle and Reuse Integrated ESH Impact Assessment Solventless Lithography Additive Processing ESH Concepts in Science/Engineering Curricula Continuing Education and Short Courses Outreach Long-Term Plan in Packaging Area
2005/2006 ERC Deliverables 1. Evaluation of biological and physico-chemical methods for PFOS removal from semiconductor effluents 2. Survey of CMP waste treatment technologies 3. Optimization of CMP process parameters, pad groove configurations and slurries for reduced delamination processes 4. Study of the effects of alternate brush design and brush porosity on post-cmp cleaning efficiency
2005/2006 ERC Deliverables 5. Evaluation of SCCO 2 as a viable technology in porous low-k film cleans - pore capping at the surface of patterned porous MSQ films 6. Wet cleans systems for 45 nm node and beyond 7. Pore sealing and repair of low k films 8. Non-damaging Plasma Etch
Success depends on executing the right collaborative model with the right partners. Collaboration is the key