19-2152; Rev 2; 11/02 ifferential LPECL/LECL/HSTL Receiver/rivers General escription The are low-skew differential receiver/drivers designed for clock and data distribution. The differential input can be adapted to accept a single-ended input by connecting the on-chip BB supply to an input as a reference voltage. The feature ultra-low propagation delay (172ps) and part-to-part skew (20ps) with 24mA maximum supply current, making these devices ideal for clock buffering or repeating. For interfacing to differential HSTL and LPECL signals, these devices operate over a +2.25 to +3.8 supply range, allowing high-performance clock and data distribution in systems with a nominal +2.5 or +3.3 supply. For differential LECL operation, these devices operate from a -2.25 to -3.8 supply. Multiple pinouts are provided to simplify routing across a backplane to either side of a double-sided board. Both devices are offered in space-saving 8-pin SOT23, SO, and µmax packages. Precision Clock Buffers Low-Jitter ata Repeaters Applications Features Improved Second Source of the MC10LEP16 (MAX9321) +2.25 to +3.8 ifferential HSTL/LPECL Operation -2.25 to -3.8 ifferential LECL Operation Low 17mA Supply Current 20ps Part-to-Part Skew 172ps Propagation elay Minimum 300m Output at 3GHz Output Low for Open Input ES Protection >2k (Human Body Model) On-Chip Reference for Single-Ended Input Available in Thermally Enhanced Exposed-Pad SO Package PART Ordering Information TEMP RANGE PIN- PACKAGE *Future product contact factory for availability. **EP = Exposed pad. TOP MARK MAX9321EKA-T -40 C to +85 C 8 SOT23-8 AALK MAX9321EUA* -40 C to +85 C 8 µmax MAX9321ESA -40 C to +85 C 8 SO M A X9 3 2 1 A E KA- T -40 C to +85 C 8 SOT23-8 AAIX MAX9321AEUA* -40 C to +85 C 8 µmax MAX9321AESA -40 C to +85 C 8 SO-EP** Pin Configurations 1 2 3 4 MAX9321 60kΩ 8 7 6 N.C. 5 BB N.C. 1 2 3 BB 4 MAX9321 60kΩ 8 7 6 5 SOT23 µmax/so Pin Configurations continued at end of data sheet. Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/allas irect! at 1-888-629-4642, or visit Maxim s website at www.maxim-ic.com.
ifferential LPECL/LECL/HSTL Receiver/rivers ABSOLUTE MAXIMUM RATINGS to...+4.1 or... - 0.3 to + 0.3 to...±3.0 Continuous Output Current...50mA Surge Output Current...100mA BB Sink/Source Current...±0.6mA Junction-to-Ambient Thermal Resistance in Still Air 8-Pin SOT23...+112 C/W 8-Pin µmax...+221 C/W 8-Pin SO-EP...+53 C/W Junction-to-Ambient Thermal Resistance with 500 LFPM Airflow 8-Pin SOT23...+78 C/W 8-Pin µmax...+155 C/W 8-Pin SO...+99 C/W Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. C ELECTRICAL CHARACTERISTICS Junction-to-Case Thermal Resistance 8-Pin SOT23...+80 C/W 8-Pin µmax...+39 C/W 8-Pin SO...+40 C/W Operating Temperature Range...-40 C to +85 C Junction Temperature...+150 C Storage Temperature Range...-65 C to +150 C ES Protection Human Body Model (,,,, BB )...>2k Soldering Temperature (10s)...+300 C ( = +2.25 to +3.8, outputs loaded with 50Ω ±1% to 2.0. Typical values are at = +3.3, IH = 1, IL = 1.5, unless otherwise noted.) (Notes 1 5) PARAMETER SYMBOL CONITIONS IFFERENTIAL INPUT (, ) -40 C +25 C +85 C MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS Single-Ended Input High oltage IH BB connected to ( IL for BB connected to ), Figure 1 1.210 1.145 1.085 Single-Ended Input Low oltage IL BB connected to ( IH for BB connected to ), Figure 1 1.65 1.545 1.485 High oltage of ifferential Input Low oltage of ifferential Input ifferential Input oltage IH + 1.2 IL + 1.2 + 1.2 For < 3.0 IH - IL For 3.0 3.0 3.0 3.0 Input High Current Input Low Current Input Low Current I IH 150 150 150 µa I IL -10 100-10 100-10 100 µa I IL -150 +150-150 +150-150 +150 µa 2
ifferential LPECL/LECL/HSTL Receiver/rivers C ELECTRICAL CHARACTERISTICS (continued) ( = +2.25 to +3.8, outputs loaded with 50Ω ±1% to 2.0. Typical values are at = +3.3, IH = 1, IL = 1.5, unless otherwise noted.) (Notes 1 5) PARAMETER SYMBOL CONITIONS IFFERENTIAL OUTPUT (, ) Single-Ended Output High oltage Single-Ended Output Low oltage ifferential Output oltage REFERENCE ( BB ) Reference oltage Output (Note 6) OH Figure 1 1.135 OL Figure 1 1.935-40 C +25 C +85 C MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS 0.885 1.685 1.07 1.87 0.82 1.62 1.01 1.81 0.76 1.56 OH - OL Figure 1 550 550 550 m BB I BB = ±0.5mA 1.55 1.31 1.445 1.245 1.385 1.185 POWER SUPPLY Supply Current (Note 7) I EE 16 24 17 24 18 24 ma AC ELECTRICAL CHARACTERISTICS ( = +2.25 to +3.8, outputs loaded with 50Ω ±1% to 2, input frequency = 1.5GHz, input transition time = 125ps (20% to 80%), IH = + 1.2 to, IL = to 5, IH - IL = 5 to the smaller of 3 or. Typical values are at = 3.3, IH = 1, IL = 1.5, unless otherwise noted.) (Notes 8, 11) PARAMETER SYMBOL CONITIONS -40 C +25 C +85 C UNITS MIN TYP MAX MIN TYP MAX MIN TYP MAX ifferential Input-to- Output elay Part-to-Part Skew (Note 9) t PLH, t PHL Figure 2 145 184 235 145 172 245 130 167 230 ps t SKPP 25 90 20 100 20 100 ps Added Random Jitter (Note 10) t RJ f IN = 1.5GHz, Clock pattern f IN = 3.0GHz, Clock pattern 1.7 2.8 1.7 2.8 1.7 2.8 0.6 1.5 0.6 1.5 0.6 1.5 ps (RMS) 3
ifferential LPECL/LECL/HSTL Receiver/rivers AC ELECTRICAL CHARACTERISTICS (continued) ( = +2.25 to +3.8, outputs loaded with 50Ω ±1% to 2, input frequency = 1.5GHz, input transition time = 125ps (20% to 80%), IH = + 1.2 to, IL = to 5, IH - IL = 5 to the smaller of 3 or. Typical values are at = 3.3, IH = 1, IL = 1.5, unless otherwise noted.) (Notes 8, 11) PARAMETER SYMBOL CONITIONS Added eterministic Jitter (Note 10) Switching Frequency Output Rise/ Fall Time (20% to 80%) t J f MAX 3.0Gbps 2 23-1 PRBS pattern OH - OL 300m, Clock pattern, Figure 2 OH - OL 550m, Clock pattern, Figure 2-40 C +25 C +85 C MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS 57 80 57 80 57 80 3.0 3.0 3.0 2.0 2.0 2.0 t R, t F Figure 2 50 88 120 50 89 120 50 90 120 ps ps (p-p) GHz Note 1: Guaranteed by design and characterization. Note 2: Measurements are made with the device in thermal equilibrium. Note 3: Current into a pin is defined as positive. Current out of a pin is defined as negative. Note 4: C parameters production tested at T A = +25 C. Guaranteed by design and characterization over the full operating temperature range. Note 5: Single-ended input operation is limited to 3.0. Note 6: Use BB as a reference for inputs on the same device only. Note 7: All pins open except and. Note 8: Guaranteed by design and characterization. Limits are set at ±6 sigma. Note 9: Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge transition. Note 10: evice jitter added to the input signal. 4
ifferential LPECL/LECL/HSTL Receiver/rivers Typical Operating Characteristics (SO packages) ( = +3.3, = 0, input transition time = 125ps (20% to 80%), IH = 1, IL = 1.5, f IN = 1.5GHz, outputs loaded with 50Ω to 2, T A = +25 C, unless otherwise noted.) SUPPLY CURRENT (ma) SUPPLY CURRENT, I EE vs. TEMPERATURE 20 19 18 17 16 15 14-40 -15 10 35 60 85 TEMPERATURE ( C) MAX9321 toc01 OUTPUT AMPLITUE () 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 OUTPUT AMPLITUE, OH - OL vs. FREUENCY 0 0 500 1000 1500 2000 2500 3000 3500 FREUENCY (MHz) MAX9321 toc02 TRANSITION TIME (ps) 90 89 88 87 TRANSITION TIME vs. TEMPERATURE t F t R -40-15 10 35 60 85 TEMPERATURE ( C) MAX9321 toc03 PROPAGATION ELAY (ps) 200 195 190 185 180 175 170 165 160 155 PROPAGATION ELAY vs. HIGH OLTAGE OF IFFERENTIAL INPUT, IH t PLH IH - IL = 0.5 t PHL 150 1.0 1.4 1.8 2.2 2.6 3.0 3.4 3.8 IH () MAX9321 toc04 PROPAGATION ELAY (ps) PROPAGATION ELAY vs. TEMPERATURE 200 190 180 t PLH 170 160 t PHL 150 140 130 120-40 -15 10 35 60 85 TEMPERATURE ( C) MAX9321 toc05 5
ifferential LPECL/LECL/HSTL Receiver/rivers µmax/so PIN SOT23 NAME 1 6 N.C. No Connection Pin escription (MAX9321) FUNCTION 2 3 Noninverting ifferential Input. pulldown to. 3 4 Inverting ifferential Input. 60kΩ pullup to and pulldown to. 4 5 BB reference for single-ended operation. When used, bypass with a 0.01µF ceramic Reference Output oltage. Connect to the inverting or noninverting input to provide a capacitor to ; otherwise leave open. 5 2 Negative Supply oltage 6 7 Inverting Output. Typically terminate with 50Ω resistor to 2. 7 8 Noninverting Output. Typically terminate with 50Ω resistor to 2. 8 1 capacitors. Place the capacitors as close to the device as possible with the smaller Positive Supply oltage. Bypass from to with µf and 0.01µF ceramic value capacitor closest to the device. PIN µmax/so SOT23 NAME 1 6 N.C. No Connection Pin escription (MAX9321A) FUNCTION 2 3 Inverting ifferential Input. 60kΩ pullup to and pulldown to. 3 4 Noninverting ifferential Input. pulldown to. 4 5 BB reference for single-ended operation. When used, bypass with a 0.01µF ceramic Reference Output oltage. Connect to the inverting or noninverting input to provide a capacitor to ; otherwise leave open. 5 2 Negative Supply oltage 6 8 Noninverting Output. Typically terminate with 50Ω resistor to 2. 7 7 Inverting Output. Typically terminate with 50Ω resistor to 2. 8 1 capacitors. Place the capacitors as close to the device as possible with the smaller Positive Supply oltage. Bypass from to with µf and 0.01µF ceramic value capacitor closest to the device. 6
ifferential LPECL/LECL/HSTL Receiver/rivers Figure 1. Switching with Single-Ended Input t PLH IL OH - OL IH - IL t PHL IH BB (CONNECTE TO ) OH OL IH IL OH OH - OL OL 80% 80% 0 (IFFERENTIAL) 0 (IFFERENTIAL) () - () 20% 20% t R t F Figure 2. ifferential Transition Time and Propagation elay Timing iagram etailed escription The are low-skew differential receiver/drivers designed for clock and data distribution. For interfacing to differential HSTL and LPECL signals, these devices operate over a +2.25 to +3.8 supply range, allowing high-performance clock and data distribution in systems with a nominal +2.5 or +3.3 supply. For differential LECL operation, these devices operate from a -2.25 to -3.8 supply. Inputs The differential input can be configured to accept a single-ended input when operating at approximately = 3.0 to 3.8. This is accomplished by connecting the on-chip reference voltage, BB, to an input as a reference. For example, the differential, input is converted to a noninverting, single-ended input by connecting BB to and connecting the single-ended input to. An inverting input is obtained by connecting BB to and connecting the single-ended input to. With the differential input configured as single ended (using BB), the single-ended input can be driven to CC and EE or with a single-ended LPECL/LECL signal. When the differential input is configured as a singleended input (using BB), the approximate supply range is CC - EE = 3.0 to 3.8. This is because one of the inputs must be EE + 1.2 or higher for proper operation of the input stage. BB must be at least EE + 1.2 because it becomes the high-level input when the other (single-ended) input swings below it. Therefore, minimum BB = EE + 1.2. The minimum BB output is CC - 1.510. Substituting the minimum BB into BB = EE + 1.2 results in a minimum supply of 2.71. Rounding up to a standard supply gives the single-ended operating supply range of CC - EE = 3.0 to 3.8. 7
ifferential LPECL/LECL/HSTL Receiver/rivers When using the BB reference output, bypass it with a 0.01µF ceramic capacitor to. If the BB reference is not used, it can be left open. The BB reference can source or sink 0.5mA. Use BB only for an input on the same device as the BB reference. The maximum magnitude of the differential input from to is 3.0 or, whichever is less. This limit also applies to the difference between any reference voltage input and a single-ended input. The differential input has bias resistors that drive the output to a differential low when the inputs are open. The inverting input is biased with a 60kΩ pullup to and a pulldown to EE. The noninverting input is biased with a pulldown to. Specifications for the high and low voltage of the differential input ( IH and IL ) and the differential input voltage ( IH - IL ) apply simultaneously ( IL cannot be higher than IH ). Outputs Output levels are referenced to and are considered LPECL or LECL, depending on the level of the supply. With connected to a positive supply and connected to GN, the output is LPECL. The output is LECL when is connected to GN and is connected to a negative supply. A single-ended input of at least BB ±100m or a differential input of at least ±100m switches the outputs to the OH and OL levels specified in the C Electrical Characteristics table. Applications Information Supply Bypassing Bypass CC to EE with high-frequency surface-mount ceramic µf and 0.01µF capacitors in parallel as close to the device as possible, with the 0.01µF value capacitor closest to the device. Use multiple parallel vias for low inductance. When using the BB reference output, bypass it with a 0.01µF ceramic capacitor to (if the BB reference is not used, it can be left open). Traces Input and output trace characteristics affect the performance of the. Connect each signal of a differential input or output to a 50Ω characteristic impedance trace. Minimize the number of vias to prevent impedance discontinuities. Reduce reflections by maintaining the 50Ω characteristic impedance through connectors and across cables. Reduce skew within a differential pair by matching the electrical length of the traces. The exposed-pad (EP) SO package can be soldered to the PC board for enhanced thermal performance. If the EP is not soldered to the PC board, the thermal resistance is the same as the regular SO package. The EP is connected to the chip supply. Be sure that the pad does not touch signal lines or other supplies. Contact Maxim's Packaging department for guidelines on the use of EP packages. Output Termination Terminate outputs through 50Ω to 2 or use an equivalent Thevenin termination. When a single-ended signal is taken from the differential output, terminate both outputs. For example, when is used as a singleended output, terminate both and. TRANSISTOR COUNT: 162 Chip Information Pin Configurations (continued) 1 MAX9321A 8 N.C. 1 MAX9321A 60kΩ 8 2 3 4 60kΩ 7 6 5 N.C. BB BB 2 3 4 7 6 5 SOT23 µmax/so 8
ifferential LPECL/LECL/HSTL Receiver/rivers Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 8L, SOIC EXP. PA.EPS SOT23, 8L.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel rive, Sunnyvale, CA 94086 408-737-7600 9 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.