System Clock for Embedded AMD TM based Systems Recommended Application: AMD M69T/78E systems Output Features: 2 - Greyhound compatible K8 CPU pair 4 - low-power differential SRC pairs 2 - low-power differential SouthBridge SRC pairs 3 - low-power differential ATIG pairs - Selectable MHz low-power differential/ 66 MHz single-ended HTT clock 2-48MHz USB clock 3-4.38MHz Reference clock Key Specifications: CPU outputs cycle-to-cycle jitter < 5ps SRC outputs cycle-to-cycle jitter < 25ps ATIG outputs cycle-to-cycle jitter < 25ps +/- 3ppm frequency accuracy on CPU, SRC & ATIG clocks Features/Benefits: Spread Spectrum for EMI reduction Outputs may be disabled via SMBus External crystal load capacitors for maximum frequency accuracy PCI Express Generation 2. compliant Pin Configuration 48MHz_ 48MHz_ 2 GND48 3 SMBCLK 4 SMBDAT 5 SRC3C_LPRS 6 SRC3T_LPRS 7 SRC2C_LPRS 8 SRC2T_LPRS 9 GNDSRC VDDSRC SRCC_LPRS 2 SRCT_LPRS 3 VDDSRC 4 GNDSRC 5 SRCC_LPRS 6 SRCT_LPRS 7 SB_SRCC_LPRS 8 SB_SRCT_LPRS 9 GNDSB_SRC 2 VDDSB_SRC 2 SB_SRCC_LPRS 22 SB_SRCT_LPRS 23 GNDATIG 24 ATIG2C_LPRS 25 ATIG2T_LPRS 26 GNDATIG 27 VDDATIG 28 56-Pin TSSOP 56 VDD48 55 2 54 53 GNDREF 52 VDDREF 5 REF/SEL_HTT66 5 REF 49 REF2 48 VDDHTT 47 HTTT_LPRS/66M 46 HTTC_LPRS/66M 45 GNDHTT 44 RESTORE# 43 PD# 42 CPUKGT_LPRS 4 CPUKGC_LPRS 4 VDDCPU 39 GNDCPU 38 CPUKGT_LPRS 37 CPUKGC_LPRS 36 VDDA 35 GNDA 34 GND 33 VDD 32 ATIGT_LPRS 3 ATIGC_LPRS 3 ATIGT_LPRS 29 ATIGC_LPRS 65 8/9/9 *Other names and brands may be claimed as the property of others. Document contains information on products in the formative or design phase development. Characteristic data and other specifications are design goals. IDTreserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
Pin Description PIN # PIN NAME TYPE DESCRIPTION 48MHz_ OUT 48MHz clock output. 2 48MHz_ OUT 48MHz clock output. 3 GND48 GND Ground pin for the 48MHz outputs 4 SMBCLK IN Clock pin of SMBus circuitry, 5V tolerant. 5 SMBDAT I/O Data pin for SMBus circuitry, 5V tolerant. 6 SRC3C_LPRS OUT Complement clock of low power differential SRC clock pair. (no 5ohm shunt resistor to GND and no 33 ohm series resistor needed 7 SRC3T_LPRS OUT True clock of low power differential SRC clock pair. (no 5ohm shunt resistor to GND and no 33 ohm series resistor needed 8 SRC2C_LPRS OUT Complement clock of low power differential SRC clock pair. (no 5ohm shunt resistor to GND and no 33 ohm series resistor needed 9 SRC2T_LPRS OUT True clock of low power differential SRC clock pair. (no 5ohm shunt resistor to GND and no 33 ohm series resistor needed GNDSRC GND Ground pin for the SRC outputs VDDSRC PWR Supply for SRC core, 3.3V nominal 2 SRCC_LPRS OUT Complement clock of low power differential SRC clock pair. (no 5ohm shunt resistor to GND and no 33 ohm series resistor needed 3 SRCT_LPRS OUT True clock of low power differential SRC clock pair. (no 5ohm shunt resistor to GND and no 33 ohm series resistor needed 4 VDDSRC PWR Supply for SRC core, 3.3V nominal 5 GNDSRC GND Ground pin for the SRC outputs 6 SRCC_LPRS OUT Complement clock of low power differential SRC clock pair. (no 5ohm shunt resistor to GND and no 33 ohm series resistor needed 7 SRCT_LPRS OUT True clock of low power differential SRC clock pair. (no 5ohm shunt resistor to GND and no 33 ohm series resistor needed 8 SB_SRCC_LPRS OUT Complement clock of low power differential SouthBridge SRC clock pair. (no 5ohm shunt resistor to GND and no 33 ohm series resistor needed 9 SB_SRCT_LPRS OUT True clock of low power differential SouthBridge SRC clock pair. (no 5ohm shunt resistor to GND and no 33 ohm series resistor needed 2 GNDSB_SRC GND Ground pin for the SB_SRC outputs 2 VDDSB_SRC PWR Supply for SRC core, 3.3V nominal 22 SB_SRCC_LPRS OUT Complement clock of low power differential SouthBridge SRC clock pair. (no 5ohm shunt resistor to GND and no 33 ohm series resistor needed 23 SB_SRCT_LPRS OUT True clock of low power differential SouthBridge SRC clock pair. (no 5ohm shunt resistor to GND and no 33 ohm series resistor needed 24 GNDATIG GND Ground pin for the ATIG outputs 25 ATIG2C_LPRS OUT Complementary clock of low-power differential push-pull ATIG pair with integrated series resistor. (no 5ohm shunt resistor to GND and no 33 ohm series resistor needed) 26 ATIG2T_LPRS OUT True clock of low-power differential push-pull ATIG pair with integrated series resistor. (no 5ohm shunt resistor to GND and no 33 ohm series resistor needed) 27 GNDATIG GND Ground pin for the ATIG outputs 28 VDDATIG PWR Power supply for ATIG core, nominal 3.3V 29 ATIGC_LPRS OUT Complementary clock of low-power differential push-pull ATIG pair with integrated series resistor. (no 5ohm shunt resistor to GND and no 33 ohm series resistor needed) 3 ATIGT_LPRS OUT True clock of low-power differential push-pull ATIG pair with integrated series resistor. (no 5ohm shunt resistor to GND and no 33 ohm series resistor needed) 65 8/9/9 2
Pin Description (Continued) PIN # PIN NAME TYPE DESCRIPTION Complementary clock of low-power differential push-pull ATIG pair with integrated series resistor. (no ATIGC_LPRS OUT 3 5ohm shunt resistor to GND and no 33 ohm series resistor needed) 32 ATIGT_LPRS OUT True clock of low-power differential push-pull ATIG pair with integrated series resistor. (no 5ohm shunt resistor to GND and no 33 ohm series resistor needed) 33 VDD PWR Power supply, nominal 3.3V 34 GND GND Ground pin 35 GNDA GND Ground for the Analog Core 36 VDDA PWR 3.3V Power for the Analog Core Complementary signal of low-power differential push-pull AMD K8 "Greyhound" clock with integrated CPUKGC_LPRS OUT 37 series resistor.(no 33 ohm series resistor needed) 38 CPUKGT_LPRS OUT True signal of low-power differential push-pull AMD K8 "Greyhound" clock with integrated series resistor. (no 33 ohm series resistor needed) 39 GNDCPU GND Ground pin for the CPU outputs 4 VDDCPU PWR Supply for CPU core, 3.3V nominal Complementary signal of low-power differential push-pull AMD K8 "Greyhound" clock with integrated CPUKGC_LPRS OUT 4 series resistor. (no 33 ohm series resistor needed) 42 CPUKGT_LPRS OUT True signal of low-power differential push-pull AMD K8 "Greyhound" clock with integrated series resistor.(no 33 ohm series resistor needed) Enter /Exit Power Down. PD# IN 43 = Power Down, = normal operation. Open Drain I/O. As an input it restores the PLL's to power up default state. As an output, this signal 44 RESTORE# I/O is driven low when the internal watchdog hardware timer expires. It is cleared when the internal watchdog hardware timer is reset or disabled. The input is falling edge triggered. = Restore Settings, = normal operation. 45 GNDHTT PWR Ground pin for the HTT outputs 46 HTTC_LPRS/66M OUT Complementary signal of low-power differential push-pull hypertransport clock with integrated series resistor. (no 5ohm shunt resistor to GND and no 33 ohm series resistor needed) / 3.3V single ended 66MHz hyper transport clock 47 HTTT_LPRS/66M OUT True signal of low-power differential push-pull hypertransport clock with integrated series resistor. (no 5ohm shunt resistor to GND and no 33 ohm series resistor needed) / 3.3V single ended 66MHz hyper transport clock 48 VDDHTT PWR Supply for HTT clocks, nominal 3.3V. 49 REF2 OUT 4.38 MHz reference clock, 3.3V 5 REF OUT 4.38 MHz 3.3V reference clock 5 REF/SEL_HTT66 I/O 4.38 MHz 3.3V reference clock./ 3.3V tolerant latched input to select Hyper Transport Clock Frequency. = MHz differential HTT clock, = 66MHz 3.3V single ended HTT clock 52 VDDREF PWR Ref, TAL power supply, nominal 3.3V 53 GNDREF GND Ground pin for the REF outputs. 54 IN Crystal input, nominally 4.38MHz 55 2 OUT Crystal output, nominally 4.38MHz 56 VDD48 PWR Power pin for the 48MHz outputs and core. 3.3V 65 8/9/9 3
General Description The is a main clock synthesizer chip that provides all clocks required for AMD embedded systems. An SMBus interface allows full control of the device. Block Diagram 2 OSC 4.38MHz REF 48MHz Fixed PLL EACT 48MHz SS PLL SB_SRC (-.5% DWN SP) 8MHz MHz SB_SRC SS PLL SRC/SB_SRC/ATIG MHz SRC SRC ZDB PLL 4 to 9 MHz PWD @ 6MHz/6 MHz ATIG SEL_HTT66 SS PLL HTT MHz HTT 66MHz 2MHz HTT_T/66 HTT_C/66 CPUKG PD# SEL_HTT66 SMBCLK SMBDAT RESTORE# MODE Control Logic 65 8/9/9 4
Table: CPU and HTT Frequency Selection Table Byte 3 HTT Singleended HTT or SB_SRC Differential CPU VCO Bit5 Bit4 Bit3 Bit Bit CPU SB_SRC Spread CPU Output (MHz) (MHz) % OverClock % CPU CPU CPU CPU CPU SEL_HTT66 = SEL_HTT66 = Divider (MHz) FS4 FS3 FS2 FS FS 33.33 44.44 66.67 66.67-33% 3 4. 37.78 45.93 68.89 68.89-3% 3 43.33 42.22 47.4 7. 7. -29% 3 426.67 46.67 48.89 73.33 73.33-27% 3 44. 5. 5.37 75.56 75.56-24% 3 453.33 55.56 5.85 77.78 77.78-22% 3 466.67 6. 53.33 8. 8. -2% 3 48. 64.44 54.8 82.22 82.22-8% 3 493.33 68.89 56.3 84.44 84.44-6% 3 56.67 73.33 57.78 86.67 86.67-3% 3 52. 77.78 59.26 88.89 88.89 -% 3 533.33 82.22 6.74 9. 9. -9% 3 546.67 86.67 62.22 93.33 93.33-7% 3 56. 9. 63.7 95.56 95.56-4% 3 573.33 95.56 65.9 97.78 97.78-2% 3 586.67 2. 66.67.. Off % 3 6. 2. 66.67.. -.5% % 3 6. 26.25 68.75 3.3 3.3 3% 3 68.75 22.5 7.83 6.25 6.25 6% 3 637.5 28.75 72.92 9.38 9.38 9% 3 656.25 225. 75. 2.5 2.5 3% 3 675. 23.25 77.8 5.63 5.63 6% 3 693.75 237.5 79.7 8.75 8.75 9% 3 72.5 243.75 8.25 2.88 2.88 22% 3 73.25 25. 83.33 25. 25. 25% 3 75. 256.25 85.42 28.3 28.3 28% 3 768.75 262.5 87.5 3.25 3.25 3% 3 787.5 268.75 89.58 34.38 34.38 34% 3 86.25 275. 9.67 37.5 37.5 38% 3 825. 28.25 93.75 4.63 4.63 4% 3 843.75 287.5 95.83 43.75 43.75 44% 3 862.5 293.75 97.92 46.88 46.88 47% 3 88.25 -.5% -.5% 65 8/9/9 5
Table 2: SRC Frequency Selection Table Byte 4 SB_SRC SRC Bit4 Bit3 Bit2 Bit Bit SRC ATIG(3:) Spread VCO (:) OverClo Output SB SB SB SB SB (MHz) (MHz) % (MHz) (MHz) ck % Divider FS4 FS3 FS2 FS FS 87. 87. 87. -3% 87. 87.87 87.87 87.87-2% 878.7 88.73 88.73 88.73 -% 887.3 89.6 89.6 89.6 -% 896. 9.47 9.47 9.47 -% 94.7 9.33 9.33 9.33-9% 93.3 92.2 92.2 92.2-8% 922. 93.7 93.7 93.7-7% 93.7 93.93 93.93 93.93-6% 939.3 94.8 94.8 94.8-5% 948. 95.67 95.67 95.67-4% 956.7 95.67 95.67 95.67-4% 956.7 97.4 97.4 97.4-3% 974. 98.27 98.27 98.27-2% 982.7 99.3 99.3 99.3 -% 99.3... Off %.... %..87.87.87 % 8.7.73.73.73 2% 7.3 2.6 2.6 2.6 3% 26. 3.47 3.47 3.47 3% 34.7 4.33 4.33 4.33 4% 43.3 5.2 5.2 5.2 5% 52. 6.7 6.7 6.7 6% 6.7 6.93 6.93 6.93 7% 69.3 7.8 7.8 7.8 8% 78. 8.67 8.67 8.67 9% 86.7 9.53 9.53 9.53 % 95.3.4.4.4 % 4..27.27.27 % 2.7 2.3 2.3 2.3 2% 2.3 3. 3. 3. 3% 3. NOTE: All frequencies assume that the SRC / SB_SRC / ATIG are at % Overclocking. -.48 max -.48 max 65 8/9/9 6
General SMBus serial interface information for the How to Write: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + - (see Note 2) ICS clock will acknowledge each byte one at a time Controller (host) sends a Stop bit How to Read: Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = ICS clock sends Byte N + - ICS clock sends Byte through byte (if (H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit T Index Block Write Operation Controller (Host) ICS (Slave/Receiver) start bit Index Block Read Operation Controller (Host) ICS (Slave/Receiver) T start bit Slave Address D2 (H) WR WRite Beginning Byte = N Data Byte Count = Beginning Byte N ACK ACK ACK ACK Slave Address D2 (H) WR WRite Beginning Byte = N RT Repeat start Slave Address D3 (H) RD ReaD ACK ACK ACK P Byte N + - stop bit Byte ACK ACK ACK Byte Data Byte Count = Beginning Byte N N P Not acknowledge stop bit Byte N + - 65 8/9/9 7
SMBus Table: Latched Input Readback Output Enable Control Register Byte Name Description.3 Default Bit 7 SEL_HTT66 readback Hypertransport Select R MHz Differential HTT 66 MHz 3.3V Singleended HTT clock clock Latch Bit 5 REF_OE Output Enable RW Low Enabled Bit 4 REF_OE Output Enable RW Low Enabled Bit 3 REF2_OE Output Enable RW Low Enabled Bit 2 48MHz OE Output Enable RW Low Enabled Bit 48MHz OE Output Enable RW Low Enabled Bit SS_Enable Spread Spectrum Enable (CPU, HTT) RW Spread Off Spread On SMBus Table:Output Enable Control Register Byte Name Control Function Type Default Bit 7 CPU_OE Output enable RW Low/Low Enable Bit 6 CPU_OE Output enable RW Low/Low Enable Bit 5 SRC3_OE Output Enable RW Low/Low Enabled Bit 4 SRC2_OE Output Enable RW Low/Low Enabled Bit 3 HTT_OE Output Enable RW Low/Low Enabled Bit 2 SRC_OE Output Enable RW Low/Low Enabled Bit Bit SRC_OE Output Enable RW Low/Low Enabled SMBus Table: Output Enable and 48MHz Strength Control Register Byte 2 Name Control Function Type Default Bit 7 SB_SRC_OE Output Enable RW Low/Low Enabled Bit 6 SB_SRC_OE Output Enable RW Low/Low Enabled Bit 5 SRC_PLL_SS_Enable Spread Spectrum Enable (SRC, SB_SRC, ATIG) RW Spread Off Spread On Bit 4 ATIG2_OE Output Enable RW Low/Low Enabled Bit 3 ATIG_OE Output Enable RW Low/Low Enabled Bit 2 ATIG_OE Output Enable RW Low/Low Enabled Bit 48MHz Strength 48MHz_ Drive Strength Sel. RW Load 2 Load Bit 48MHz Strength 48MHz_ Drive Strength Sel. RW Load 2 Load SMBus Table: CPU/HTT Frequency Control Register Byte 3 Name Control Function Type Default Bit 7 Bit 5 Bit 4 CPU_FS4 CPU Frequency Select MSB RW See CPU Frequency Select Table Bit 3 CPU_FS3 CPU Frequency Select RW Default value corresponds to 2MHz. Bit 2 CPU_FS2 CPU Frequency Select RW Note that Selected HTT frequency tracks the Bit CPU_FS CPU Frequency Select RW CPU frequency. Bit CPU_FS CPU Frequency Select LSB RW SMBus Table: SRC Frequency Control Register Byte 4 Name Control Function Type Default Bit 7 REF_Strength REF_Drive Strength Sel RW Load 2 Load Bit 6 REF_Strength REF_Drive Strength Sel RW Load 2 Load Bit 5 REF2_Strength REF2_Drive Strength Sel RW Load 2 Load Bit 4 SRC_FS4 SRC Frequency Select MSB RW See SRC Frequency Select Table Bit 3 SRC_FS3 SRC Frequency Select RW Note: SB_SRC and ATIG Clocks are Bit 2 SRC_FS2 SRC Frequency Select RW synchronous to these outputs. Changing this Bit SRC_FS SRC Frequency Select RW frequency will alter the SB_SRC and ATIG Bit SRC_FS SRC Frequency Select LSB RW frequency by the same percentage. 65 8/9/9 8
SMBus Table: Byte 5 Name Control Function Type Default Bit 7 Bit 5 Bit 3 Bit 2 Bit Bit SMBus Table: Byte 6 Name Control Function Type Default Bit 7 Bit 5 Bit 3 Bit 2 Bit HTT66M_OE_ Output Enable RW Low/Low Enable Bit HTT66M_OE_ Output Enable RW Low/Low Enable SMBus Table: Device ID register Byte 7 Name Control Function Type Default Bit 7 Device ID7 R Bit 6 Device ID6 R Bit 5 Device ID5 R Bit 4 Device ID4 R Device ID 7 hex Bit 3 Device ID3 R Bit 2 Device ID2 R Bit Device ID R Bit Device ID R SMBus Table: Vendor & Revision ID Register Byte 8 Name Control Function Type Default Bit 7 RID3 R - - Bit 6 RID2 R - - REVISION ID Bit 5 RID R - - Bit 4 RID R - - Bit 3 VID3 R - - Bit 2 VID2 R - - VENDOR ID Bit VID R - - Bit VID R - - SMBus Table: WatchDog Timer Control Register Byte 9 Name Control Function Type Default Disable and Reload Bit 7 HWD_EN Watchdog Hard Alarm Enable RW Enable Timer Hartd Alarm Timer Clear Bit 5 WD Hard Status WD Hard Alarm Status R Normal Alarm Bit 4 WDTCtrl Watch Dog Alarm Time base Control RW 29ms Base 6ms Base Bit 3 HWD3 WD Hard Alarm Timer Bit 3 RW Bit 2 HWD2 WD Hard Alarm Timer Bit 2 RW These bits represent the number of Watch Dog Time Base Units that pass before the Watch Bit HWD WD Hard Alarm Timer Bit RW Alarm expires. Default is 7 x 29 ms = 2s Bit HWD WD Hard Alarm Timer Bit RW 65 8/9/9 9
SMBus Table: Byte Name Control Function Type Default Bit 7 Bit 5 Bit 3 Bit 2 Bit Bit SMBus Table: Byte Count Register Byte Name Control Function Type Default Bit 7 Bit 5 BC5 Byte Count bit 5 (MSB) RW Bit 4 BC4 Byte Count bit 4 RW Bit 3 BC3 Byte Count bit 3 RW Determines the number of bytes that are read Bit 2 BC2 Byte Count bit 2 RW back from the device. Default is F hex. Bit BC Byte Count bit RW Bit BC Byte Count bit (LSB) RW SMBus Table: M/N Programming Enable and I/O Vout Control Register Byte 2 Name Control Function Type Default Bit 7 CPU M/N En CPU PLL M/N Prog. Enable RW M/N Prog. Disabled M/N Prog. Enabled Bit 6 SRC M/N En SRC M/N Prog.Enable RW M/N Prog. Disabled M/N Prog. Enabled Bit 5 SKIP_N_INC Skip N Incrementing during CPU PLL M/N Programming RW N-Increment Bypass N-Increment Bit 3 IO Output Voltage Select (Most Bit 2 IO_VOUT2 RW Significant Bit) See Table 5: V_IO Selection Bit IO_VOUT IO Output Voltage Select RW (Default is.8v) IO Output Voltage Select (Least Bit IO_VOUT RW Significant Bit) SMBus Table: Register Byte 3 Name Control Function Type Default Bit 7 Bit 5 Bit 3 Bit 2 Bit Bit SMBus Table: Register Byte 4 Name Control Function Type Default Bit 7 CPU NDiv LSB N Divider Programming RW Byte 27 has the N Divider LSB (bit ) for CPU Bit 5 Bit 3 SB_SRCDiv3 RW :/2 ; :/4 :/8 ; :/6 Bit 2 SB_SRCDiv2 SB_SRC Divider Ratio Programming RW :/3 ; :/6 :/2 ; :/24 Bit SB_SRCDiv Bits from CPU PLL RW :/5 ; :/ :/2 ; :/4 Bit SB_SRCDiv RW :/9 ; :/8 :/36 ; :/72 65 8/9/9
SMBus Table:Test Mode Register Byte 5 Name Control Function Type Default Bit 7 Test_Md_Sel Selects Test Mode RW Normal mode All ouputs are REF/N Bit 5 Bit 3 Bit 2 Bit Bit SMBus Table: CPU PLL Frequency Control Register Byte 6 Name Control Function Type Default Bit 7 N Div2 N Divider Prog bit 2 RW Bit 6 N Div N Divider Prog bit RW Bit 5 M Div5 RW The decimal representation of M and N Divider in Bit 4 M Div4 RW Byte 6 and 7 will configure the VCO frequency. Bit 3 M Div3 RW Default at power up = Byte Rom table. See M/N M Divider Programming bits Bit 2 M Div2 RW Caculation Tables for VCO frequency formulas. Bit M Div RW Bit M Div RW SMBus Table: CPU PLL Frequency Control Register Byte 7 Name Control Function Type Default Bit 7 N Div RW Bit 6 N Div9 RW Bit 5 N Div8 RW The decimal representation of M and N Divider in Bit 4 N Div7 RW Byte 6 and 7 will configure the VCO frequency. N Divider Programming b(:3) Bit 3 N Div6 RW Default at power up = Byte Rom table. See M/N Bit 2 N Div5 RW Caculation Tables for VCO frequency formulas. Bit N Div4 RW Bit N Div3 RW SMBus Table: CPU PLL Spread Spectrum Control Register Byte 8 Name Control Function Type Default Bit 7 Bit 5 Bit 3 SB_SRC_Ssel SB_SRC PLL Source Selection (MSB) RW - N/A - CPU PLL Bit 2 ATIG_Ssel ATIGCLK PLL Source Selection RW SRC PLL FI PLL Bit SRC_Ssel SRC PLL Source Selection RW SRC PLL FI PLL Bit SB_SRC_Ssel SB_SRC PLL Source Selection (LSB) RW - SRC PLL - FI PLL SMBus Table: Byte 9 Name Control Function Type Default Bit 7 Bit 5 Bit 3 Bit 2 Bit Bit 65 8/9/9
SMBUS Table: SRC spread enable Byte 2 Name Control Function Type Default Bit 7 SRC_PLL_SS_Enable Spread Spectrum Enable (SRC, SB_SRC, ATIG) RW Spread Off Spread On Bit 5 Bit 3 Bit 2 Bit Bit SMBUS Table: Byte 2 Name Control Function Type Default Bit 7 Bit 5 Bit 3 Bit 2 Bit Bit SMBUS Table: Byte 22 Name Control Function Type Default Bit 7 ATIGDiv3 RW :/2 ; :/4 :/8 ; :/6 Bit 6 ATIGDiv2 RW N/A ; :/6 :/2 ; :/24 ATIG Divider Ratio Programming Bits Bit 5 ATIGDiv RW N/A ; :/ :/2 ; :/4 Bit 4 ATIGDiv RW N/A ; :/4 :/28 ; :/56 Bit 3 SB_SRCDiv3 RW :/2 ; :/4 :/8 ; :/6 Bit 2 SB_SRCDiv2 SB_SRC Divider Ratio Programming RW :/3 ; :/6 :/2 ; :/24 Bit SB_SRCDiv Bits from SRC Fixed / PLL RW :/5 ; :/ :/2 ; :/4 Bit SB_SRCDiv RW :/7 ; :/4 :/28 ; :/56 SMBUS Table: SRC Spread Spectrum Control Register Byte 23 Name Control Function Type Default Bit 7 SSP7 RW Bit 6 SSP6 RW Bit 5 SSP5 RW These bits set the SRC, the ATIG and SB_SRC Bit 4 SSP4 Spread Spectrum Programming RW spread pecentages.please contact ICS for the Bit 3 SSP3 bit(7:) RW appropriate values. Bit 2 SSP2 RW Bit SSP RW Bit SSP RW SMBUS Table: SRC Spread Spectrum Control Register Byte 24 Name Control Function Type Default Bit 7 SSP5 RW Bit 6 SSP4 RW Bit 5 SSP3 RW These bits set the SRC, the ATIG and SB_SRC Bit 4 SSP2 Spread Spectrum Programming RW spread pecentages.please contact ICS for the Bit 3 SSP bit(5:8) RW appropriate values. Bit 2 SSP RW Bit SSP9 RW Bit SSP8 RW 65 8/9/9 2
SMBUS Table: SRC Frequency Control Register Byte 25 Name Control Function Type Default Bit 7 N Div2 N Divider Prog bit 2 RW The decimal representation of M and N Divider in Bit 6 N Div N Divider Prog bit RW Byte 2 and 2 configure the SRC VCO Bit 5 M Div5 RW frequency. See M/N Caculation Tables for VCO Bit 4 M Div4 RW frequency formulas. Bit 3 M Div3 M Divider Programming RW Bit 2 M Div2 bit (5:) RW NOTE: Changing this frequency will also alter the Bit M Div RW ATIG and SB_SRC frequencies by a similar Bit M Div RW amount. SMBUS Table: SRC Frequency Control Register Byte 26 Name Control Function Type Default Bit 7 N Div RW The decimal representation of M and N Divider in Bit 6 N Div9 RW Byte 2 and 2 configure the SRC VCO Bit 5 N Div8 RW frequency. See M/N Caculation Tables for VCO Bit 4 N Div7 N Divider Programming Byte6 RW frequency formulas. Bit 3 N Div6 bit(7:) and Byte5 bit(7:6) RW Bit 2 N Div5 RW NOTE: Changing this frequency will also alter the Bit N Div4 RW ATIG and SB_SRC frequencies by a similar Bit N Div3 RW amount. SMBUS Table: CPU Output Divider Control Register Byte 27 Name Control Function Type Default Bit 7 HTTDiv3 RW :/2 ; :/4 :/8 ; :/6 Bit 6 HTTDiv2 RW N/A ; :/6 :/2 ; :/24 HTT Divider Ratio Programming Bits Bit 5 HTTDiv RW N/A ; :/ :/2 ; :/4 Bit 4 HTTDiv RW N/A ; :/8 :/36 ; :/72 Bit 3 CPUDiv3 RW :/2 ; :/4 :/8 ; :/6 Bit 2 CPUDiv2 RW :/3 ; :/6 :/2 ; :/24 CPU Divider Ratio Programming Bits Bit CPUDiv RW :/5 ; :/ :/2 ; :/4 Bit CPUDiv RW :/9 ; :/8 :/36 ; :/72 SMBUS Table: CPU PLL Spread Spectrum Control Register Byte 28 Name Control Function Type Default Bit 7 SSP7 RW Bit 6 SSP6 RW Bit 5 SSP5 RW These bits set the CPU/HTT spread Bit 4 SSP4 RW Spread Spectrum Programming b(7:) pecentage.please contact ICS for the appropriate Bit 3 SSP3 RW values. Bit 2 SSP2 RW Bit SSP RW Bit SSP RW SMBUS Table: CPU PLL Spread Spectrum Control Register Byte 29 Name Control Function Type Default Bit 7 SSP5 RW Bit 6 SSP4 RW Bit 5 SSP3 RW Bit 4 SSP2 RW These bits set the CPU/HTT spread Spread Spectrum Programming pecentage.please contact ICS for the appropriate Bit 3 SSP b(5:8) RW values. Bit 2 SSP RW Bit SSP9 RW Bit SSP8 RW 65 8/9/9 3
SMBUS Table: SRC Output Divider Control Register Byte 3 Name Control Function Type Default Bit 7 SRC NDiv LSB N Divider Programming RW Byte 3 has the N Divider LSB (bit ) for SRC Bit 6 Bit 5 Bit 4 Bit 3 SRCDiv3 RW :/2 ; :/4 :/8 ; :/6 Bit 2 SRCDiv2 RW N/A ; :/6 :/2 ; :/24 SRC Divider Ratio Programming Bits Bit SRCDiv RW N/A; :/ :/2 ; :/4 Bit SRCDiv RW N/A; :/4 :/28 ; :/56 SMBUS Table: Register Byte 3 Name Control Function Type Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit Bit 65 8/9/9 4
Absolute Maximum Rating PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Notes 3.3V Core Supply Voltage VDDxxx - 3.3 GND + 3.9V V Storage Temperature Ts - -65 5 C Ambient Operating Temp Tambient - 7 C Case Temperature Tcase - 5 C Input ESD protection HBM ESD prot - 2 V Guaranteed by design and characterization, not % tested in production. Electrical Characteristics - Input/Supply/Common Output Parameters PARAMETER SYMBOL CONDITIONS* MIN TYP MA UNITS Notes 3.3V Core Supply Voltage VDDxxx - 3.35 3.3 3.465 V Input High Voltage V IH VDD = 3.3 V +/-5% 2 V DD +.3 V Input Low Voltage V IL VDD = 3.3 V +/-5% V SS -.3.8 V Input High Current I IH V IN = V DD -5 5 ua Input Low Current V I IN = V; Inputs with no pull-up IL resistors -5 ua V I IN = V; Inputs with pull-up IL2 resistors -2 ua Low Threshold Input- High Voltage V IH_FS VDD = 3.3 V +/-5%.7 V DD +.3 V Low Threshold Input- V Low Voltage IL_FS VDD = 3.3 V +/-5% 3.3V VDD current, all outputs Operating Current I DD3.3OP driven 65 8/9/9 V SS -.3.35 V 5 ma Powerdown Current I DD3.3PD all diff pairs low/low 2 ma Input Frequency F i VDD = 3.3 V +/-5% 4.388 MHz 2 Pin Inductance L pin 7 nh C IN Logic Inputs 5 pf Input Capacitance C OUT Output pin capacitance 6 pf C IN & 2 pins 5 pf From VDD Power-Up or deassertion of PD to st clock Clk Stabilization T STAB.8 ms Modulation Frequency Triangular Modulation 3 33 khz Tdrive_PD CPU output enable after PD de-assertion 3 us Tfall_PD PD fall time of 5 ns Trise_PD PD rise time of 5 ns SMBus Voltage V DDSMB 2.7 5.5 V Low-level Output Voltage V OLSMB @ I PULLUP.4 V Current sinking at V OL =.4 V I PULLUPSMB 4 6 ma SMBCLK/SMBDAT (Max VIL -.5) to T Clock/Data Rise Time RSMB (Min VIH +.5) ns SMBCLK/SMBDAT (Min VIH +.5) to T Clock/Data Fall Time FSMB (Max VIL -.5) 3 ns *TA = - 7 C; Supply Voltage VDD = 3.3 V +/-5% Guaranteed by design and characterization, not % tested in production. 2 Input frequency should be measured at the REF pin and tuned to ideal 4.388MHz to meet ppm frequency accuracy on PLL outputs. 5
AC Electrical Characteristics - Low-Power DIF Outputs: CPUKG and HTT PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS NOTES Crossing Point Variation V CROSS Single-ended Measurement 4 mv,2,5 Frequency f Spread Specturm On 98.8 2 MHz,3 Long Term Accuracy ppm Spread Specturm Off -3 +3 ppm, Rising Edge Slew Rate S RISE Differential Measurement.5 V/ns,4 Falling Edge Slew Rate S FALL Differential Measurement.5 V/ns,4 Slew Rate Variation t SLVAR Single-ended Measurement 2 % CPU, DIF HTT Jitter - Cycle to Cycle CPUJ C2C Differential Measurement 5 ps,6 Accumulated Jitter t JACC See Notes ns,7 Peak to Peak Differential Voltage V D(PK-PK) Differential Measurement 4 24 mv,8 Differential Voltage V D Differential Measurement 2 2 mv,9 Duty Cycle D CYC Differential Measurement 45 55 % Amplitude Variation V D Change in V D DC cycle to cycle -75 75 mv, CPU[:] Skew CPU SKEW Differential Measurement ps Notes on Electrical Characteristics: Guaranteed by design and characterization, not % tested in production. Single-ended measurement at crossing point. Value is maximum minimum over all time. DC value of common mode is not important due to the blocking cap. Minimum Frequency is a result of.5% down spread spectrum Differential measurement through the range of ± mv, differential signal must remain monotonic and within slew rate spec when crossing through this region. 5 Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK and falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets CLK#. 6 Max difference of t CYCLE between any two adjacent cycles. 7 Accumulated tjc.over a µs time period, measured with JIT2 TIE at 5ps interval. 8 VD(PK-PK) is the overall magnitude of the differential signal. 9 VD(min) is the amplitude of the ring-back differential measurement, guaranteed by design, that ring-back will not cross V VD. VD(max) is the largest amplitude allowed. The difference in magnitude of two adjacent VD_DC measurements. VD_DC is the stable post overshoot and ring-back part of the signal. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 4.388MHz 65 8/9/9 6
AC Electrical Characteristics - Low-Power DIF Outputs: SRC, SB_SRC, ATIG PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS NOTES Rising Edge Slew Rate t SLR Differential Measurement.6 4 V/ns,2 Falling Edge Slew Rate t FLR Differential Measurement.6 4 V/ns,2 Slew Rate Variation t SLVAR Single-ended Measurement 2 % Maximum Output Voltage V HIGH Includes overshoot 5 mv Minimum Output Voltage V LOW Includes undershoot -3 mv Differential Voltage Swing V SWING Differential Measurement 3 mv Crossing Point Voltage V ABS Single-ended Measurement 3 55 mv,3,4 Crossing Point Variation V ABSVAR Single-ended Measurement 4 mv,3,5 Duty Cycle D CYC Differential Measurement 45 55 % SRC Jitter - Cycle to Cycle SRCJ C2C Differential Measurement 25 ps SRC[3:] Skew SRC SKEW Differential Measurement ps SB_SRC[:] Skew SRC SKEW Differential Measurement ps Notes on Electrical Characteristics: Guaranteed by design and characterization, not % tested in production. 2 Slew rate measured through Vswing centered around differential zero 3 Vxabs is defined as the voltage where CLK = CLK# 4 Only applies to the differential rising edge (CLK rising and CLK# falling) 5 Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of 6 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 4.388MHz Electrical Characteristics - Single-ended HTT 66MHz Clock PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Notes Long Accuracy ppm see Tperiod min-max values -3 3 ppm,2 PCI33 Clock period HTT66 Clock period T period T period 33.33MHz output nominal 29.99 3.9 ns 2 33.33MHz output spread 29.99 3.598 ns 2 66.67MHz output nominal 4.9955 5.45 ns 2 66.67MHz output spread 4.9955 5.799 ns 2 Output High Voltage V OH I OH = - ma 2.4 V Output Low Voltage V OL I OL = ma.55 V Output High Current Output Low Current I OH I OL V OH @MIN =. V -33 ma V OH @ MA = 3.35 V -33 ma V OL @ MIN =.95 V 3 ma V OL @ MA =.4 V 38 ma Edge Rate δv/δt Rising edge rate (VOL =.4 V, VOH = 2.4 V) 4 V/ns Edge Rate δv/δt Falling edge rate (VOL =.4 V, VOH = 2.4 V) 4 V/ns Duty Cycle d t V T =.5 V 45 55 % Jitter, Cycle to cycle t jcyc-cyc V T =.5 V 8 ps *TA = - 7 C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pf with Rs = 22Ω (unless otherwise specified) Guaranteed by design and characterization, not % tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that REF is at 4.388MHz 65 8/9/9 7
Electrical Characteristics - USB - 48MHz PARAMETER SYMBOL CONDITIONS* MIN TYP MA UNITS NOTES Long Accuracy ppm see Tperiod min-max values - ppm,2 Clock period T period 48.MHz output nominal 2.8229 2.8344 ns 2 Clock Low Time T low Measure from <.6V 9.375.458 ns 2 Clock High Time T high Measure from > 2.V 9.375.458 ns 2 Output High Voltage V OH I OH = - ma 2.4 V Output Low Voltage V OL I OL = ma.55 V Output High Current Output Low Current I OH I OL V OH @MIN =. V -33 ma V OH @MA = 3.35 V -33 ma V OL @ MIN =.95 V 3 ma V OL @ MA =.4 V 38 ma Edge Rate δv/δt Rising edge rate (VOL =.4 V, VOH = 2.4 V).3 4 V/ns Edge Rate δv/δt Falling edge rate (VOL =.4 V, VOH = 2.4 V).3 4 V/ns Duty Cycle d t V T =.5 V 45 55 % Group Skew t skew V T =.5 V 25 ps Jitter, Cycle to cycle t jcyc-cyc V T =.5 V 3 ps,2 *TA = - 7 C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pf with Rs = 22Ω (unless otherwise specified) Guaranteed by design and characterization, not % tested in production. 2 ICS recommended and/or chipset vendor layout guidelines must be followed to meet this specification Electrical Characteristics - REF-4.38MHz PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Notes Long Accuracy ppm see Tperiod min-max values -3 3 ppm,2 Clock period T period 4.38MHz output nominal 69.827 69.855 ns 2 Clock Low Time T low Measure from <.6V 3.929 37.93 ns 2 Clock High Time T high Measure from > 2.V 3.929 37.93 ns 2 Output High Voltage V OH I OH = - ma 2.4 V Output Low Voltage V OL I OL = ma.4 V V OH @MIN =. V, Output High Current I OH V OH @MA = 3.35 V -29-23 ma V OL @MIN =.95 V, Output Low Current I OL V OL @MA =.4 V 29 27 ma Edge Rate δv/δt Rising edge rate (VOL =.4 V, VOH = 2.4 V).3 2 V/ns Edge Rate δv/δt Falling edge rate (VOL =.4 V, VOH = 2.4 V).3 2 V/ns Skew t sk V T =.5 V 25 ps Duty Cycle d t V T =.5 V 45 55 % Jitter t jcyc-cyc V T =.5 V 3 ps *TA = - 7 C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pf with Rs = 22Ω (unless otherwise specified) Guaranteed by design and characterization, not % tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 4.388MHz 65 8/9/9 8
INDE AREA A2 e N 2 D -Cb E A A E c SEATING PLANE aaa C α L 56-Lead 6. mm. Body,.5 mm. Pitch TSSOP (24 mil) (2 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MA MIN MA A --.2 --.47 A.5.5.2.6 A2.8.5.32.4 b.7.27.7. c.9.2.35.8 D E SEE VARIATIONS 8. BASIC SEE VARIATIONS.39 BASIC E 6. 6.2.236.244 e.5 BASIC.2 BASIC L.45.75.8.3 N SEE VARIATIONS SEE VARIATIONS α 8 8 aaa --. --.4 VARIATIONS D mm. D (inch) N MIN MA MIN MA 56 3.9 4..547.555 Reference Doc.: JEDEC Publication 95, M O-53-39 Ordering Information Part/Order Number Shipping Packaging Package Temperature 9EPRS475BGLF Tubes 56-pin TSSOP to 7 C 9EPRS475BGLFT Tape and Reel 56-pin TSSOP to 7 C Parts that are ordered with a LF suffix to the part number are the Pb-Free configuration and are RoHS compliant. Due to package size constraints, actual top-side marking may differ from the full orderable part number. 65 8/9/9 9
Revision History Rev. Issue Date Description Page #. 7/3/29 Initial Release - A 8/9/29 Released to final. 65 8/9/9 This product is protected by United States Patent NO. 7,342,42 and other patents. 2