DATASHEET General Description The 9VRS488B is a.5v Core main clock synthesizer chip for AMD Fusion platform. An SMBus interface allows full control of the device. Recommended Application Very Low Power Clock Generator for AMD Fusion II Platforms Input/utput Features Low power differential outputs with integrated series resistors for Zo=5ohm systems 2 - Differential PCIe Gen2 SRC pairs w/dedicated CLKREQ# pins 3 - Differential PCIe Gen2 SATA_DISPLAY pairs w/microspread capability 2-48MHz USB clocks (8 degrees out of phase for EMI reduction) 2-4.38MHz REF clock outputs - 25MHz LAN clock output that can run from VDD suspend rail - CkPwrGd/WL_STP# - VDD_SUSPEND pin - RESET_IN# pin 9VRS488B Features/Benefits.5V Core for minimal Power consumption Spread Spectrum for EMI reduction utputs may be disabled via SMBus External crystal load capacitors for maximum frequency accuracy Key Specifications SRC/SATA_DISP output cycle-to-cycle jitter < 25ps 4.38MHz output cycle-to-cycle jitter < 2ps 48MHz output cycle-to-cycle jitter < 3ps SRC/SATA_DISP output phase jitter < 3.ps rms (PCIe Gen2) +/- ppm frequency accuracy on all clocks, (assuming REF is trimmed to ppm) 3.5KHz spread modulation frequency; passes USB3. compliance test Pin Configuration 48MHz_ VDD48_3.3 ^RESET_IN# ^CLKREQ4# ^CLKREQ5# ^CLKREQ6# VDDREF_3.3 REF REF GNDREF ^CLKREQ7# ^CLKREQ8# ^CLKREQ9# SMBCLK SMBDAT 25MHz GND25M VDD25_SUSP3.3 72 7 7 69 68 67 66 65 64 63 62 6 6 59 58 57 56 55 48MHz_ GND48 2 ^CLKREQ3# 3 ^CLKREQ2# 4 ^CLKREQ# 5 ^CLKREQ# 6 SRCT_LPRS 7 SRCC_LPRS 8 SRCT_LPRS 9 SRCC_LPRS 9VRS488 GNDSRC VDDSRC_LI 2 SRC2T_LPRS 3 SRC2C_LPRS 4 SRC3T_LPRS 5 SRC3C_LPRS 6 VDDSRC_.5 7 GNDSRC 8 9 2 2 22 23 24 25 26 27 28 29 3 3 32 33 34 35 36 SRC4T_LPRS SRC4C_LPRS SRC5T_LPRS SRC5C_LPRS SRC6T_LPRS SRC6C_LPRS SRC7T_LPRS SRC7C_LPRS GNDSRC VDDSRC_LI SRC8T_LPRS SRC8C_LPRS SRC9T_LPRS SRC9C_LPRS VDDSRC_.5 GNDSRC SRCT_LPRS SRCC_LPRS 54 X_25 53 X2_25 52 ^CKPwrGd/WL_STP# 5 ^CLKREQ# 5 ^CLKREQ# 49 VDDSATADISP_.5 48 GNDSATADISP 47 SATA_DISPC_LPRS 46 SATA_DISPT_LPRS 45 SATA_DISPC_LPRS 44 SATA_DISPT_LPRS 43 GNDSATADISP 42 VDDSATADISP_LI 4 SATA_DISP2C_LPRS 4 SATA_DISP2T_LPRS 39 GNDSRC 38 SRCC_LPRS 37 SRCT_LPRS ^ Indicates that pin has Kohm internal pullup resistor. IDT 9VRS488B REV A 6252
9VRS488B Pin Descriptions PIN # PIN NAME PIN TYPE DESCRIPTIN 48MHz_ UT 48MHz clock output. (8 degrees out of phase with 48MHz_) 2 GND48 GND Ground pin for the 48MHz outputs 3 ^CLKREQ3# IN utput enable for SRC/PCI Express output pair '3' = enabled, = Low/Low. This pin has a 2K internal pull up resistor. 4 ^CLKREQ2# IN utput enable for SRC/PCI Express output pair '2' = enabled, = Low/Low. This pin has a 2K internal pull up resistor. 5 ^CLKREQ# IN utput enable for SRC/PCI Express output pair '' = enabled, = Low/Low. This pin has a 2K internal pull up resistor. 6 ^CLKREQ# IN utput enable for SRC/PCI Express output pair '' = enabled, = Low/Low. This pin has a 2K internal pull up resistor. 7 SRCT_LPRS UT True clock of low power differential SRC clock pair. (no 5 ohm shunt resistor to GND and no 33 ohm series resistor 8 SRCC_LPRS UT Complement clock of low power differential SRC clock pair. (no 5 ohm shunt resistor to GND and no 33 ohm series resistor 9 SRCT_LPRS UT True clock of low power differential SRC clock pair. (no 5 ohm shunt resistor to GND and no 33 ohm series resistor SRCC_LPRS UT Complement clock of low power differential SRC clock pair. (no 5 ohm shunt resistor to GND and no 33 ohm series resistor GNDSRC GND Ground pin for the SRC outputs 2 VDDSRC_LI PWR Supply for SRC outputs,.5v to.5v nominal 3 SRC2T_LPRS UT True clock of low power differential SRC clock pair. (no 5 ohm shunt resistor to GND and no 33 ohm series resistor 4 SRC2C_LPRS UT Complement clock of low power differential SRC clock pair. (no 5 ohm shunt resistor to GND and no 33 ohm series resistor 5 SRC3T_LPRS UT True clock of low power differential SRC clock pair. (no 5 ohm shunt resistor to GND and no 33 ohm series resistor 6 SRC3C_LPRS UT Complement clock of low power differential SRC clock pair. (no 5 ohm shunt resistor to GND and no 33 ohm series resistor 7 VDDSRC_.5 PWR Supply for SRC core and outputs,.5v nominal 8 GNDSRC GND Ground pin for the SRC outputs 9 SRC4T_LPRS UT True clock of low power differential SRC clock pair. (no 5 ohm shunt resistor to GND and no 33 ohm series resistor 2 SRC4C_LPRS UT Complement clock of low power differential SRC clock pair. (no 5 ohm shunt resistor to GND and no 33 ohm series resistor 2 SRC5T_LPRS UT True clock of low power differential SRC clock pair. (no 5 ohm shunt resistor to GND and no 33 ohm series resistor 22 SRC5C_LPRS UT Complement clock of low power differential SRC clock pair. (no 5 ohm shunt resistor to GND and no 33 ohm series resistor 23 SRC6T_LPRS UT True clock of low power differential SRC clock pair. (no 5 ohm shunt resistor to GND and no 33 ohm series resistor 24 SRC6C_LPRS UT Complement clock of low power differential SRC clock pair. (no 5 ohm shunt resistor to GND and no 33 ohm series resistor 25 SRC7T_LPRS UT True clock of low power differential SRC clock pair. (no 5 ohm shunt resistor to GND and no 33 ohm series resistor 26 SRC7C_LPRS UT Complement clock of low power differential SRC clock pair. (no 5 ohm shunt resistor to GND and no 33 ohm series resistor 27 GNDSRC GND Ground pin for the SRC outputs 28 VDDSRC_LI PWR Supply for SRC outputs,.5v to.5v nominal 29 SRC8T_LPRS UT True clock of low power differential SRC clock pair. (no 5 ohm shunt resistor to GND and no 33 ohm series resistor 3 SRC8C_LPRS UT Complement clock of low power differential SRC clock pair. (no 5 ohm shunt resistor to GND and no 33 ohm series resistor 3 SRC9T_LPRS UT True clock of low power differential SRC clock pair. (no 5 ohm shunt resistor to GND and no 33 ohm series resistor 32 SRC9C_LPRS UT Complement clock of low power differential SRC clock pair. (no 5 ohm shunt resistor to GND and no 33 ohm series resistor 33 VDDSRC_.5 PWR Supply for SRC core and outputs,.5v nominal 34 GNDSRC GND Ground pin for the SRC outputs 35 SRCT_LPRS UT True clock of low power differential SRC clock pair. (no 5 ohm shunt resistor to GND and no 33 ohm series resistor 36 SRCC_LPRS UT Complement clock of low power differential SRC clock pair. (no 5 ohm shunt resistor to GND and no 33 ohm series resistor IDT 2 9VRS488B REV A 6252
9VRS488B Pin Descriptions (cont.) PIN # PIN TYPE DESCRIPTIN 37 SRCT_LPRS UT True clock of low power differential SRC clock pair. (no 5 ohm shunt resistor to GND and no 33 ohm series resistor 38 SRCC_LPRS UT Complement clock of low power differential SRC clock pair. (no 5 ohm shunt resistor to GND and no 33 ohm series resistor 39 GNDSRC GND Ground pin for the SRC outputs 4 SATA_DISP2T_LPRS UT True clock of low power differential SATA_DISPlay clock pair. (no 5 ohm shunt resistor to GND and no 33 ohm series resistor 4 SATA_DISP2C_LPRS UT Complement clock of low power differential SATA_DISPlay clock pair. (no 5 ohm shunt resistor to GND and no 33 ohm series resistor 42 VDDSATADISP_LI PWR Supply for SATA_DISPlay outputs,.5v to.5v nominal 43 GNDSATADISP GND Ground pin for the SATA_DISPlay outputs 44 SATA_DISPT_LPRS UT True clock of low power differential SATA_DISPlay clock pair. (no 5 ohm shunt resistor to GND and no 33 ohm series resistor 45 SATA_DISPC_LPRS UT Complement clock of low power differential SATA_DISPlay clock pair. (no 5 ohm shunt resistor to GND and no 33 ohm series resistor 46 SATA_DISPT_LPRS UT True clock of low power differential SATA_DISPlay clock pair. (no 5 ohm shunt resistor to GND and no 33 ohm series resistor 47 SATA_DISPC_LPRS UT Complement clock of low power differential SATA_DISPlay clock pair. (no 5 ohm shunt resistor to GND and no 33 ohm series resistor 48 GNDSATADISP GND Ground pin for the SATA_DISPlay outputs 49 VDDSATADISP_.5 PWR Supply for SATA_DISPlay core and outputs,.5v nominal 5 ^CLKREQ# IN utput enable for SRC/PCI Express output pair '' = enabled, = Low/Low. This pin has a 2K internal pull up resistor. 5 ^CLKREQ# IN utput enable for SRC/PCI Express output pair '' = enabled, = Low/Low. This pin has a 2K internal pull up resistor. 52 ^CKPwrGd/WL_STP# IN This devices powers up the clock chip and latched strap pins when asserted high. When asserted low, the clock is powered down except for the 25M output, if VDD25_SUSP3.3 is maintained. = Power Down, = normal operation. 53 X2_25 UT Crystal output, nominally 25MHz 54 X_25 IN Crystal input, nominally 25MHz 55 VDD25_SUSP3.3 PWR Power pin for the 25M output and XTAL oscillator. This pin allows the 25MHz output when the rest of the power is collapsed and VttPwrGd/WL_STP# is low. 56 GND25M GND Ground pin for the 25MHz output and XTAL oscillator circuit 57 25MHz UT 25MHz clock output. 58 SMBDAT I/ Data pin for SMBus circuitry, 5V tolerant. 59 SMBCLK IN Clock pin of SMBus circuitry, 5V tolerant. 6 ^CLKREQ9# IN utput enable for SRC/PCI Express output pair '9' = enabled, = Low/Low. This pin has a 2K internal pull up resistor. 6 ^CLKREQ8# IN utput enable for SRC/PCI Express output pair '8' 62 ^CLKREQ7# IN = enabled, = Low/Low. This pin has a 2K internal pull up resistor. utput enable for SRC/PCI Express output pair '7' = enabled, = Low/Low. This pin has a 2K internal pull up resistor. 63 GNDREF GND Ground pin for the REF outputs. 64 REF UT 4.38 MHz reference clock, 3.3V 65 REF UT 4.38 MHz reference clock, 3.3V 66 VDDREF_3.3 PWR Ref, XTAL power supply, nominal 3.3V 67 ^CLKREQ6# IN 68 ^CLKREQ5# IN 69 ^CLKREQ4# IN 7 ^RESET_IN# D I/ utput enable for SRC/PCI Express output pair '6' = enabled, = Low/Low. This pin has a 2K internal pull up resistor. utput enable for SRC/PCI Express output pair '5' = enabled, = Low/Low. This pin has a 2K internal pull up resistor. utput enable for SRC/PCI Express output pair '4' = enabled, = Low/Low. This pin has a 2K internal pull up resistor. As an input it resets the device to the power up default state. As an output, it is driven low when the internal watchdog hardware timer expires. It is cleared when the internal watchdog hardware timer is reset or disabled. The input is falling edge triggered. = Restore Settings, = normal operation. 7 VDD48_3.3 PWR Power pin for the 48MHz and SI outputs and core. 3.3V 72 48MHz_ UT 48MHz clock output. IDT 3 9VRS488B REV A 6252
9VRS488B Block Diagram 25MHz 4.38MHz PLL REF(:) SATA_DISP PLL SATA_DISP(2:) Gen2 SRC PLL SS capable SRC(:) X X2 25M XTAL SC USB48 PLL 48M(:) CKPwrGD/WL_STP# CLKREQ(:)# SMBCLK SMBDAT LGIC DIFFERENTIAL SINGLE-ENDED Power Groups Pin Number VDD3.3 VDD.5 VDD_LI GND 7, 33 2, 28,, 8, 27, 34, 39 49 42 43, 48 Description Power for SRC PLL and utputs Power for SATA_DISP PLL and utputs 47 5 Power for HTT output 66 63 Power for REF PLL and utputs 55 56 Power for XTAL osc.and 25M outputs 7 2 Power for 48MHz PLL and outputs. IDT 4 9VRS488B REV A 6252
9VRS488B SATA_DISP Frequency Selection Table Line SATA_DISP FS4 Byte 3, Bit 4 SATA_DISP FS3 Byte 3, Bit 3 SATA_DISP FS2 Byte 3, Bit2 SATA_DISP FS Byte 3, Bit SATA_DISP FS Byte 3, Bit SATA_DISP Speed (MHz) 9.25 9.25 2 92.5 3 92.5 4 93.75 5 93.75 6 95. 7 95. 8 96.25 9 96.25 97.5 97.5 2 98.75 3 98.75 4. 5. 6. 7. 8.25 9.25 2 2.5 2 2.5 22 3.75 23 3.75 24 5. 25 5. 26 6.25 27 6.25 28 7.5 29 7.5 3 8.75 3 8.75 Spread % N/A IDT 5 9VRS488B REV A 6252
9VRS488B Line SS Type Byte 4, Bit 4 SRC Spread Selection Table SRC SRC FS SS_EN Byte 4, Byte 4, Bit Bit2 SS Range Byte 4, Bit 3 SRC FS Byte 4, Bit SRC Speed (MHz).. 2. 3. Spread % 4. -.49 5. -.45 6. -.4 7. -.35 8. 9... 2. -.3 3. -.25 4. -.25 5. -.25 6. 7. 8. 9. 2. +/-.25 2. +/-.225 22. +/-.2 23. +/-.75 24. 25. 26. 27. SS FF % SS FF % SS FF % SS FF % 28. +/-.5 29. +/-.25 3. +/-.25 3. +/-.25 IDT 6 9VRS488B REV A 6252
9VRS488B Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the 9VRS488B. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. PARAMETER SYMBL CNDITINS MIN TYP MAX UNITS Notes I/ Supply Voltage VDDxxx_LI -.5 GND+.9V V.5V Core Supply Voltage VDDxxx_.5 -.5 GND+.9V V 3.3V Core Supply Voltage VDDxxx_3.3-3.3 GND+3.8V V Storage Temperature Ts - -65 5 C Ambient perating Temp Tambient - 7 C Case Temperature Tcase - 5 C Input ESD protection ESD prot Human Body Model 2 V Guaranteed by design and characterization, not % tested in production. Electrical Characteristics USB - 48MHz PARAMETER SYMBL CNDITINS* MIN TYP MAX UNITS NTES Long Accuracy ppm see Tperiod min-max values - ppm Clock period T PERID USB output nominal 2.83 2.833 2.836 ns,3 Clock Low Time T LW Measure from <.6V 9.375.4.458 ns Clock High Time T HIGH Measure from > 2.V 9.375.75.458 ns utput High Voltage V H I H = - ma 2.4 2.8 3.3 V utput Low Voltage V L I L = ma.4 V V L = 2% of Voh, Rise Time t r_usb V H = 8%of Voh.5.9 3 ns V L = 2% of Voh, Fall Time t f_usb V H = 8%of Voh.5 2 3 ns utput High Voltage V HUSB I H = - ma 2.4 V utput Low Voltage V LUSB I L = ma.4 V utput High Voltage V HUSB2 I H = -.2 ma.8 2 2.2 V utput Low Voltage V LUSB2 I L =.2 ma.4 V Skew(out of phase) t SKEW V T =.5 V 24 25 ps,4 Jitter, Cycle to cycle t jcyc-cyc V T =.5 V 5 3 ps,2 V Jitter, Short Term t T =.5 V, integrated from jshrt-term MHz to 25Mhz - ps,2 V Jitter, Long Term t T =.5 V, integrated from jlng-term.mhz to Mhz -3 3 ps,2,3 Duty Cycle d CYCUSB V T =.5 V 45 5 55 % *TA = - 7 C; Supply Voltage VDD = 3.3 V +/-5% Guaranteed by design and characterization, not % tested in production. 2 IDT recommended and/or chipset vendor layout guidelines must be followed to meet this specification 3 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that 25MHz output is at 25MHz 4 USB outputs are 8 degrees out of phase. 5 The Ncycle jitter (N periods after trigger) must not exceed +/- 3 ps for any N-cuycle inside a winder starting at trigger and finsihing ns after trigger. (N=..4) IDT 7 9VRS488B REV A 6252
9VRS488B Electrical Characteristics Input/Supply/Common utput Parameters PARAMETER SYMBL CNDITINS* MIN TYP MAX UNITS Notes I/ Supply Voltage VDDxxx_LI -.9975.5.25 V.5V Core Supply Voltage VDDxxx_.5 -.425.5.575 V 3.3V Core Supply Voltage VDDxxx_3.3-3.35 3.3 3.465 V Input High Voltage V IH 3.3V Inputs 2 V DD +.3 V, 3 Input Low Voltage V IL 3.3V inputs V SS -.3.8 V, 3 Input High Current I IH V IN = V DD -5 5 ua Input Low Current Suspend Current I DD_3.3SUSP ma WL_STP (25M) I DD_.5SUSP ma Enabled in Power Down I IL V IN = V; Inputs with no pull-up resistors -5 ua I IL2 V IN = V; Inputs with pullup resistors -2 ua I DD_I/SUSP ma Power Down Current I DD_3.3PD 2 ma WL_STP (25M) I DD_.5PD ma Disabled in Power down I DD_I/PD. ma I DD_3.3 3 ma perating Current I DD_.5 all outputs driven 3 ma I DD_I/ 7 ma Input Frequency F i VDD = 3.3 V +/-5% 25. MHz 2 Pin Inductance L pin 7 nh C IN Logic Inputs 5 pf Input Capacitance C UT utput pin capacitance 6 pf C INX X & X2 pins 5 pf From VDD Power-Up to st Clk Stabilization T STAB clock.8 ms Modulation Frequency Triangular Modulation 3 3.5 32 khz Tdrive_PD SATA_DISP output enable after 3 us PD de-assertion Tfall_PD PD fall time of 5 ns Trise_PD PD rise time of 5 ns SMBus Voltage V DDSMB 2.7 5.5 V Low-level utput Voltage V LSMB @ I PULLUP.4 V Current sinking at V L =.4 V I PULLUPSMB 4 6 ma SMBCLK/SMBDAT (Max VIL -.5) to T RSMB Clock/Data Rise Time (Min VIH +.5) ns SMBCLK/SMBDAT (Min VIH +.5) to T FSMB Clock/Data Fall Time (Max VIL -.5) 3 ns *TA = - 7 C; All Supply Voltages at nominal+/-5% Guaranteed by design and characterization, not % tested in production. 2 Input frequency should be measured at the 25M output pin and tuned to ideal 25MHz to meet ppm frequency accuracy on PLL outputs. 3 CLKREQ# Inputs are 3.3V tolerant IDT 8 9VRS488B REV A 6252
9VRS488B AC Electrical Characteristics Low-Power DIF utputs: SATA_DISP and SRC PARAMETER SYMBL CNDITINS MIN TYP MAX UNITS NTES SRC/SATA Frequency f SRC_SATA Spread Specturm ff MHz,6 Long Term Accuracy ppm Spread Specturm ff - + ppm,6 Rising Edge Slew Rate t SLR Differential Measurement.6 3.5 4 V/ns,2 Falling Edge Slew Rate t FLR Differential Measurement.6 3.5 4 V/ns,2 Slew Rate Variation t SLVAR Single-ended Measurement 2 % Maximum utput Voltage V HIGH Includes overshoot 925 5 mv Minimum utput Voltage V LW Includes undershoot -3-5 mv Differential Voltage Swing V SWING Differential Measurement 3 95 mv Crossing Point Voltage V XABS Single-ended Measurement 3 445 55 mv,3,4 Crossing Point Variation V XABSVAR Single-ended Measurement 28 4 mv,3,5 Duty Cycle t dcyc Differential Measurement 47 5 53 % Jitter - Cycle to Cycle t jcyc-cyc Differential Measurement 55 25 ps SRC[:] Skew Even utputs t SRCSKEW_E Differential Measurement 46 2 ps,8 SRC[:] Skew dd utputs t SRCSKEW_ Differential Measurement 6 2 ps,8 SRC[:] Even to dd Skew t SRCSKEW Differential Measurement.925 ns,8 Jitter - SSC Residual t SSC_RES Differential Measurement 75 ps PCIe Gen specs (.5-22 MHz) 38 86 ps, 7 PCIe Gen 2 (8-6 MHz, 5-6 MHz).5 3 ps rms, 7 Lo-band content Jitter, Phase t jphase (khz to.5mhz) PCIe Gen 2 (8-6 MHz, 5-6 MHz) Hi-band content 2.4 3. ps rms, 7 (.5MHz to Nyquist) Default Spread when enabled -.49 %, 9 SSC t jphasesrc Spread ption -.48 %, 9 Spread ption 2 -.47 %, 9 Spread ption 3 -.46 %, 9 *TA = - 7 C; All Supply Voltages at nominal+/-5% Guaranteed by design and characterization, not % tested in production. 2 Slew rate measured through Vswing centered around differential zero 3 Vxabs is defined as the voltage where CLK = CLK# 4 nly applies to the differential rising edge (CLK rising and CLK# falling) 5 Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK and falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets CLK#. 6 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that 25MHz output is at 25MHz 7 Applicable to all SRC outputs. See http://www.pcisig.com for complete specs. Guaranteed by design/characterization, not tested in production. 8 SRC outputs are divided into two banks, odd and even. The odd bank skew window is 2 ps. The even bank skew window is 2ps. The skew between the even and odd banks is intentionally set at.925 ns. 9 nly applies to SRC outputs. SATA_DISP outputs do not spread. IDT 9 9VRS488B REV A 6252
9VRS488B Electrical Characteristics REF-4.38MHz PARAMETER SYMBL CNDITINS MIN TYP MAX UNITS Notes Long Accuracy ppm see Tperiod min-max values -5 5 ppm,2 Long Term Jitter t jlt @ us 2 5 ps,2,3 Clock period T PERID 4.38MHz output nominal 69.843 ns 2 Clock Low Time T LW Measure from V T = 5% 2 33 ns 2 Clock High Time T HIGH Measure from V T = 5% 2 34 ns 2 utput High Voltage V H I H = - ma 2.4 2.8 3.3 V utput Low Voltage V L I L = ma.4 V V L = 2% of V H, Rise Time t R V H = 8%of V H.2.5 ns V L = 2% of V H, Fall Time t F V H = 8%of V H.2.5 ns Skew t SKEW Measure from V T = 5% 7 25 ps Duty Cycle d t V T = V H /2 45 5 55 % Jitter, Cycle to Cycle t jcyc-cyc Measure from V T = 5% 25 2 ps,3 Jitter, Peak to Peak t jpk-pk Measure from V T = 5% (.9V) t jpk-pk =[ t jcyc-cyc max + t jcyccycmin ]/2 *TA = - 7 C; Supply Voltage VDD = 3.3 V +/-5% Guaranteed by design and characterization, not % tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that 25MHz output is at 25MHz 3 IDT recommended and/or chipset vendor layout guidelines must be followed to meet this specification Electrical Characteristics 25MHz 2 ps,3 PARAMETER SYMBL CNDITINS MIN TYP MAX UNITS Notes Long Accuracy ppm see Tperiod min-max values -5 5 ppm,2 Long Term Jitter t jlt @ us 2 25 ps,2,3 25MHz XTAL output Clock period T PERID nominal 4. ns 2 Clock Low Time T LW Measure from V T = 5% 2 6.6 ns 2 Clock High Time T HIGH Measure from V T = 5% 2 7.2 ns 2 utput High Voltage V H I H = - ma 2.4 2.8 3.3 V utput Low Voltage V L I L = ma.4 V V L = % of V H, Rise Time t R V H = 9%of V H 2.4 3 ns V L = % of V H, Fall Time t F V H = 9%of V H 2.4 3 ns Duty Cycle d t V T = 5% 45 48 55 % Jitter, Cycle to Cycle t jcyc-cyc Measure from V T = 5% 8 2 ps,3 Jitter, Peak to Peak t jpk-pk t jpk-pk =[ t jcyc-cyc max + t jcyccycmin ]/2 6 2 ps,3 Measure from V T = 5% *TA = - 7 C; Supply Voltage VDD = 3.3 V +/-5% Guaranteed by design and characterization, not % tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that 25MHz output is at 25MHz 3 IDT recommended and/or chipset vendor layout guidelines must be followed to meet this specification IDT 9VRS488B REV A 6252
9VRS488B General SMBus Serial Interface Information for 9VRS488B How to Write Controller (host) sends a start bit Controller (host) sends the write address IDT clock will acknowledge Controller (host) sends the beginning byte location = N IDT clock will acknowledge Controller (host) sends the byte count = X IDT clock will acknowledge Controller (host) starts sending Byte N through Byte N+X- IDT clock will acknowledge each byte one at a time Controller (host) sends a Stop bit Index Block Write peration Controller (Host) IDT (Slave/Receiver) T start bit Slave Address WR WRite ACK Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK Byte N + X - ACK P stop bit Read Address D3 (H) X Byte Write Address D2 (H) How to Read Controller (host) will send a start bit Controller (host) sends the write address IDT clock will acknowledge Controller (host) sends the beginning byte location = N IDT clock will acknowledge Controller (host) will send a separate start bit Controller (host) sends the read address IDT clock will acknowledge IDT clock will send the data byte count = X IDT clock sends Byte N+X- IDT clock sends Byte through Byte X (if X (H) was written to Byte 8) Controller (host) will need to acknowledge each byte Controller (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Read peration Controller (Host) IDT (Slave/Receiver) T start bit Slave Address WR WRite ACK Beginning Byte = N ACK RT Repeat start Slave Address RD ReaD ACK N P ACK ACK Not acknowledge stop bit X Byte Data Byte Count=X Beginning Byte N Byte N + X - IDT 9VRS488B REV A 6252
9VRS488B Byte SMBus Table: utput Enable Control Register Name Description Type Default Bit 7 25M_E utput Enable RW Low Enabled Bit 6 REF_E utput Enable RW Low Enabled Bit 5 REF_E utput Enable RW Low Enabled Bit 4 SATA_DISP2_E utput Enable RW Low/Low Enabled Bit 3 SATA_DISP_E utput Enable RW Low/Low Enabled Bit 2 SATA_DISP_E utput Enable RW Low/Low Enabled Bit 48MHz E utput Enable RW Low Enabled Bit 48MHz E utput Enable RW Low Enabled Byte SMBus Table:CKLREQ and utput Control Register Name Control Function Type Default Bit 7 CLKREQ7 CLKREQ 7controls SRC7 RW Does not control Controls Bit 6 CLKREQ6 CLKREQ6 controls SRC6 RW Does not control Controls Bit 5 CLKREQ5 CLKREQ5 controls SRC5 RW Does not control Controls Bit 4 CLKREQ4 CLKREQ4 controls SRC4 RW Does not control Controls Bit 3 SRC_E utput Enable RW Low/Low Enabled Bit 2 SRC_E utput Enable RW Low/Low Enabled Bit SRC9_E utput Enable RW Low/Low Enabled Bit SRC8_E utput Enable RW Low/Low Enabled Byte SMBus Table: utput Enable Control Register 2 Name Control Function Type Default Bit 7 SRC7_E utput Enable RW Low/Low Enabled Bit 6 SRC6_E utput Enable RW Low/Low Enabled Bit 5 SRC5_E utput Enable RW Low/Low Enabled Bit 4 SRC4_E utput Enable RW Low/Low Enabled Bit 3 SRC3_E utput Enable RW Low/Low Enabled Bit 2 SRC2_E utput Enable RW Low/Low Enabled Bit SRC_E utput Enable RW Low/Low Enabled Bit SRC_E utput Enable RW Low/Low Enabled Byte SMBus Table: SATA_DISP/HTT Frequency and utput Enable Control Register 3 Name Control Function Type Default Bit 7 CLKREQ3 CLKREQ3 controls SRC3 RW Does not control Controls Bit 6 CLKREQ2 CLKREQ2 controls SRC2 RW Does not control Controls Bit 5 WL_EN 25M does not run when 25M does RUNS when Enables 25M output in Suspend RW VDD_SUSP is present and VDD_SUSP is present and State WL_STP# = WL_STP# = Bit 4 SATA_DISP_FS4 SATA_DISP Freq. Select MSB RW Bit 3 SATA_DISP_FS3 SATA_DISP Freq. Select RW Bit 2 SATA_DISP_FS2 SATA_DISP Freq. Select RW See SATA_DISP Frequency Select Table Bit SATA_DISP_FS SATA_DISP Freq. Select RW Bit SATA_DISP_FS SATA_DISP Freq. Select LSB RW Byte SMBus Table: SRC Frequency Control Register 4 Name Control Function Type Default Bit 7 CLKREQ CLKREQ controls SRC RW Does not control Controls Bit 6 CLKREQ CLKREQ controls SRC RW Does not control Controls Bit 5 Reserved Bit 4 SRC SS TYPE Down or Center Spread RW Down Center Bit 3 SRC_SS_RNG Normal or Low Range RW Normal Low Range (<.25%) Bit 2 SRC_SS_EN SRC Spread Enable RW ff n Bit SRC_SS_SEL SRC Spread Amount RW See SRC Spread Select Table Bit SRC_SS_SEL SRC Spread Amount RW Default Corresponds to MHz. IDT 2 9VRS488B REV A 6252
9VRS488B Byte SMBus Table: I/ Vout and M/N Enable Register 5 Name Control Function Type Default Bit 7 Reserved Bit 6 SATA_DISP M/N En SATA_DISP PLL M/N Prog. Enable RW M/N Prog. Disabled M/N Prog. Enabled Bit 5 SRC M/N En SRC M/N Prog.Enable RW M/N Prog. Disabled M/N Prog. Enabled Bit 4 Test_Sel Selects Test Type RW utputs are Tri-state utputs are REF/4 Bit 3 Test_Mode Enable Test Mode RW Normal mode Enable Test Mode I utput Voltage Select (Most Bit 2 I_VUT2 RW Significant Bit) =.7V =.8V Bit I_VUT I utput Voltage Select RW =.9V =.V I utput Voltage Select (Least Bit I_VUT RW Significant Bit) Byte SMBus Table: Byte Count Register 6 Name Control Function Type Default Bit 7 Reserved Bit 6 Reserved Bit 5 Reserved Bit 4 BC4 Byte Count bit 4 RW Bit 3 BC3 Byte Count bit 3 RW Determines the number of bytes that are read back from the device. Bit 2 BC2 Byte Count bit 2 RW Default is 8 hex. Bit BC Byte Count bit RW Bit BC Byte Count bit (LSB) RW Byte SMBus Table: Device ID register 7 Name Control Function Type Default Bit 7 Device ID7 R Bit 6 Device ID6 R Bit 5 Device ID5 R Bit 4 Device ID4 R Device ID 8 hex for 9VRS488 Bit 3 Device ID3 R Bit 2 Device ID2 R Bit Device ID R Bit Device ID R Byte SMBus Table: Vendor & Revision ID Register 8 Name Control Function Type Default Bit 7 RID3 R x Bit 6 RID2 R x REVISIN ID Rev B = Bit 5 RID R x Bit 4 RID R x Bit 3 VID3 R Bit 2 VID2 R VENDR ID IDT/ICS = Bit VID R Bit VID R Byte SMBus Table: WatchDog Timer Control Register 9 Name Control Function Type Default Bit 7 HWD_EN Watchdog Hard Alarm Enable RW Disable and Reload Hartd Alarm Timer, Clear WD Hard status bit. Enable Timer Bit 6 SWD_EN Watchdog Soft Alarm Enable RW Disable Enable Bit 5 WD Hard Status WD Hard Alarm Status R Normal Alarm X Bit 4 WD Soft Status WD Soft Alarm Status R Normal Alarm X Bit 3 WDTCtrl Watch Dog Alarm Time base Control RW 29ms Base 6ms Base Bit 2 HWD2 WD Hard Alarm Timer Bit 2 RW These bits represent the number of Watch Dog Time Base Units that Bit HWD WD Hard Alarm Timer Bit RW pass before the Watch Alarm expires. Default is 7 X 29ms = 2s. Bit HWD WD Hard Alarm Timer Bit RW IDT 3 9VRS488B REV A 6252
9VRS488B Byte SMBus Table: WD Timer Safe Frequency Control Register Name Control Function Type Default Bit 7 SWD2 WD Soft Alarm Timer Bit 2 RW These bits represent the number of Watch Dog Time Base Units that Bit 6 SWD WD Soft Alarm Timer Bit RW pass before the Watch Alarm expires. Default is 7 X 29ms = 2s. Bit 5 SWD WD Soft Alarm Timer Bit RW Bit 4 Reserved Bit 3 Reserved Bit 2 Reserved Bit Reserved Bit Reserved Byte SMBus Table: CLKREQ8 and 9 Control Register Name Control Function Type Default Bit 7 Reserved Bit 6 Reserved Bit 5 Reserved Bit 4 Reserved Bit 3 CLKREQ CLKREQ controls SRC RW Does not control Controls Bit 2 CLKREQ CLKREQ controls SRC RW Does not control Controls Bit CLKREQ9 CLKREQ9 controls SRC9 RW Does not control Controls Bit CLKREQ8 CLKREQ8 controls SRC8 RW Does not control Controls Byte SMBus Table: SATA_DISP PLL Frequency Control Register 2 Name Control Function Type Default Bit 7 N Div2 N Divider Prog bit 2 RW X Bit 6 N Div N Divider Prog bit RW X Bit 5 M Div5 RW The decimal representation of M and N Divider in Byte 2 and 3 will X Bit 4 M Div4 RW X configure the VC frequency. Contact IDT for the M/N Calculation Bit 3 M Div3 RW X M Divider Programming bits Tables for VC frequency formulas. Bit 2 M Div2 RW X Bit M Div RW X Bit M Div RW X Byte SMBus Table: SATA_DISP PLL Frequency Control Register 3 Name Control Function Type Default Bit 7 N Div RW X Bit 6 N Div9 RW X Bit 5 N Div8 RW The decimal representation of M and N Divider in Byte 2 and 3 will X Bit 4 N Div7 RW X N Divider Programming b(:3) configure the VC frequency. Contact IDT for the M/N Calculation Bit 3 N Div6 RW X Tables for VC frequency formulas. Bit 2 N Div5 RW X Bit N Div4 RW X Bit N Div3 RW X Byte SMBus Table: Slew Rate Control Register 4 Name Control Function Type Default Bit 7 Reserved Bit 6 Reserved Bit 5 Reserved Bit 4 Reserved Bit 3 Reserved Bit 2 Reserved Bit 25M SLEW 25M Slew Rate Control MSB RW =.3V/ns, =.9V/ns Bit 25M SLEW 25M Slew Rate Control LSB RW = 2.5V/ns, = 2.9V/ns IDT 4 9VRS488B REV A 6252
9VRS488B Byte SMBus Table:Slew Rate Control Register 5 Name Control Function Type Default Bit 7 48M_ SLEW 48M_ Slew Rate Control RW =.3V/ns, =.9V/ns Bit 6 48M_ SLEW 48M_ Slew Rate Control RW = 2.5V/ns, = 2.9V/ns Bit 5 48M_ SLEW 48M_ Slew Rate Control RW =.3V/ns, =.9V/ns Bit 4 48M_ SLEW 48M_ Slew Rate Control RW = 2.5V/ns, = 2.9V/ns Bit 3 REF SLEW REF Slew Rate Control MSB RW =.3V/ns, =.9V/ns Bit 2 REF SLEW REF Slew Rate Control LSB RW = 2.5V/ns, = 2.9V/ns Bit REF SLEW REF Slew Rate Control MSB RW =.3V/ns, =.9V/ns Bit REF SLEW REF Slew Rate Control LSB RW = 2.5V/ns, = 2.9V/ns Byte SMBUS Table: SRC Frequency Control Register 6 Name Control Function Type Default Bit 7 N Div2 N Divider Prog bit 2 RW X Bit 6 N Div N Divider Prog bit RW X Bit 5 M Div5 RW X The decimal representation of M and N Divider in Byte 6 and 7 Bit 4 M Div4 RW X configure the SRC VC frequency. Contact IDT for M/N Calculation Bit 3 M Div3 M Divider Programming RW X Tables for VC frequency formulas. Bit 2 M Div2 bit (5:) RW X Bit M Div RW X Bit M Div RW X Byte SMBUS Table: SRC Frequency Control Register 7 Name Control Function Type Default Bit 7 N Div RW X Bit 6 N Div9 RW X Bit 5 N Div8 RW X The decimal representation of M and N Divider in Byte 6 and 7 Bit 4 N Div7 N Divider Programming Byte6 RW X configure the SRC VC frequency. Contact IDT for M/N Calculation Bit 3 N Div6 bit(7:) and Byte5 bit(7:6) RW X Tables for VC frequency formulas. Bit 2 N Div5 RW X Bit N Div4 RW X Bit N Div3 RW X Byte SMBUS Table: SRC Spread Spectrum Control Register 8 Name Control Function Type Default Bit 7 SSP7 RW X Bit 6 SSP6 RW X Bit 5 SSP5 RW X Bit 4 SSP4 Spread Spectrum Programming RW These bits set the SRC spread pecentages.please contact IDT for the X Bit 3 SSP3 bit(7:) RW appropriate values. X Bit 2 SSP2 RW X Bit SSP RW X Bit SSP RW X Byte SMBUS Table: SRC Spread Spectrum Control Register 9 Name Control Function Type Default Bit 7 SSP5 RW X Bit 6 SSP4 RW X Bit 5 SSP3 RW X Bit 4 SSP2 Spread Spectrum Programming RW These bits set the SRC spread pecentages.please contact IDT for the X Bit 3 SSP bit(5:8) RW appropriate values. X Bit 2 SSP RW X Bit SSP9 RW X Bit SSP8 RW X IDT 5 9VRS488B REV A 6252
9VRS488B Byte SMBUS Table: SRC PLL NDiv utput Divider and Single Ended utput Slew Rate Control Register 2 Name Control Function Type Default Bit 7 SRC NDiv LSB N Divider Programming RW N Divider LSB (bit ) for SRC M/N programming. X Bit 6 Reserved Bit 5 Reserved Bit 4 Reserved Bit 3 Reserved Bit 2 Reserved Bit Reserved Bit Reserved Byte SMBUS Table: SATA_DISP PLL NDiv and SATA_DISP utput Divider Register 2 Name Control Function Type Default Bit 7 SATA_DISP NDiv LSB N Divider Programming RW N Divider LSB (bit ) for SATA_DISP M/N programming. X Bit 6 Reserved Bit 5 Reserved Bit 4 Reserved Bit 3 Reserved Bit 2 SATA_DISPDiv2 SATA_DISP Divider Ratio RW = /2 = /3 Bit SATA_DISPDiv RW = /4 = /5 Programming Bits Bit SATA_DISPDiv RW = /7 - = / Bytes 22 to 63 Are Reserved Clock Periods Differential utputs with Spread Spectrum Enabled Measurement Window Symbol Clock us.s.s.s us Clock Lg- -SSC -ppm error ppm + ppm error +SSC Lg+ Definition Absolute Period Minimum Absolute Period Short-term Average Minimum Absolute Period Long-Term Average Minimum Absolute Period Period Long-Term Average Short-term Average Nominal Maximum Maximum Maximum Units Notes Signal Name SRC 9.874 9.999 9.999...53.763 ns,2 Period Clock Periods Differential utputs with Spread Spectrum Disabled Measurement Window Clock us.s.s.s us Clock Symbol Lg- -SSC -ppm error ppm + ppm error +SSC Lg+ Absolute Short-term Long-Term Long-Term Short-term Period Period Average Average Average Average Period Definition Minimum Absolute Minimum Absolute Minimum Absolute Nominal Maximum Maximum Maximum Period Period Period Units Notes Signal Name SRC/SATA_DISP 9.874 9.999...763 ns,2 Guaranteed by design and characterization, not % tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that 25MHz output is at 25MHz IDT 6 9VRS488B REV A 6252
9VRS488B Power-up Sequence Requirement Marking Diagram ICS 9VRS488BKLF LT C YYWWP Notes:. LT is the lot code. 2. C denotes country of origin. 3. YYWW is the last two digits of the year and week that the part was assembled. 4. LF designates RoHS compliant package. IDT 7 9VRS488B REV A 6252
9VRS488B Package utline and Package Dimensions (72-pin MLF) Index Area N 2 E Seating Plane Anvil Singulation -- or -- A A3 E2 (N D -)x (Ref) E2 2 L e N (Ref) N D & N E Even (Typ) e If N D & N 2 E are Even 2 (N E -)x (Ref) e Top View D Sawn Singulation.8 A C (Ref) N D & N E dd C e D2 2 D2 b Thermal Base Millimeters Symbol Min Max A.8. A.5 A3.25 Reference b.8.3 e.5 BASIC D x E BASIC. x. D2 MIN./MAX. 5.75 6.5 E2 MIN./MAX. 5.75 6.5 L MIN./MAX..3.5 N D 8 N E 8 rdering Information Part / rder Number Shipping Packaging Package Temperature 9VRS488BKLF Trays 72-pin MLF to +7 C 9VRS488BKLF8 Tape and Reel 72-pin MLF to +7 C "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. B is the device revision designator (will not correlate with the datasheet revision). While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT 8 9VRS488B REV A 6252
9VRS488B Revision History Rev. Issue Date Who Description Page # A 6/25/22 RDW. Corrected Differential Vswing value. 2. Updates to all electrical tables. 3. Move to final IDT 9 9VRS488B REV A 6252
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