A Faster Carry save Adder in Radix-8 Booth Encoded Multiplier

A Faster Carry save Adder in Radix-8 Booth Encoded Multiplier 1 K.Chandana Reddy, 2 P.Benister Joseph Pravin 1 M.Tech-VLSI Design, Department of ECE, Sathyabama University, Chennai-119, India. 2 Assistant Professor, Department of ECE, Sathyabama University, Chennai-119, India. Abstract: Carry save Adder is core of multipliers. The delay of conventional Carry save Adders constitutes high carry propagation delay and this delay reduces the overall performance of the radix-8 booth encoded multiplier. This paper proposes a simple and efficient approach to reduce the maximum delay of carry propagation in final stage of multiplier. The speed of multiplier increases and the delay can also be decreased. In this paper, the aim is to build up a Booth Encoding Radix-8 Multiplier with low delay carry save adder for efficient approach to reduce the maximum delay of carry propagation in the final stage of the multiplier. Booth encoding is an effective method which greatly increases the speed of our algebra. In this paper we are using the Faster Carry Save Adder (FCSA) replacing the Carry Save Adder. Index Terms: Carry save Adder, Radix-8 I. Introduction Multiplication is a fundamental operation in most signal processing algorithms. Multipliers have large area, long latency and consume considerable power. Therefore low-power multiplier design has been an important part in low- power VLSI system design [1]. A system s performance is generally determined by the performance of the multiplier because the multiplier is generally the slowest element in the system. Furthermore, it is generally the most area consuming. Hence, optimizing the speed and area of the multiplier is a major design issue. However, area and speed are usually conflicting constraints so that improving speed results mostly in larger areas. As a result, a whole spectrum of multipliers with different area- speed constraints has been designed with fully parallel. The main objective is to build up a Booth Encoding Radix-8 Multiplier with low delay carry save adder for efficient approach to reduce the maximum delay of carry propagation and to increase the speed in the final stage of the multiplier. In multipliers, the performance is based on adders because of adding the partial products. So we need to use high speed adders like Fast Carry Save adders. The delay of conventional Carry Save Adders constitutes high carry propagation delay and this delay reduces the overall performance of the radix-8 booth encoded multiplier. Faster Carry Save adders using Carry Select Adders have been helpful in reducing the delay of the multiplier. II. Booth s Algorithm This algorithm was invented by Andrew Donald Booth in 1950 while doing study on crystallography at Birkbeck College in Bloomsbury, London. Booth used reception desk calculators that shifts faster than adding and formed the algorithm to increasing the speed. Booth's algorithm is important in the study of computer architecture. Andrew Donald Booth was the person in charge of a team of computer pioneers at Birkbeck College in the University of London. Andrew Donald Booth was born on Feb 11th 1918 and died on Nov 29th 2009. Booth worked with inadequate resources, both human being and financial and emphasized on building smaller machines. Andrew Donald Booth was a British electrical engineer, computer scientist and physist who led the innovation of the magnetic drum memory for computers and invented Booth's multiplication algorithms. Booth was raised in Weybridge, Surrey, and learned at the Haberdashers' Aske's Boys School [2]. Booth s Algorithm is a smart move for multiplying signed numbers. It initiate with the ability to both add and subtract there are multiple ways to compute a product. Booth s algorithm is a multiplication algorithm that utilizes two s complement notation of signed binary numbers for multiplication. Earlier multiplication was in general implemented via sequence of addition then subtraction, and then shifts operations [3]. Multiplication can be well thought-out as a series of repeated additions. The number which is to be added is known as the multiplicand, and the number of times it is added is known as the multiplier, and the result we get is the multiplication result. After each step of addition a partial product is generated. When the operands are integers, the product in general is twice the length of operands in order to protect ISSN: 2320 8007 1501

the information content. This repetitive addition method that is recommended by the arithmetic definition is slow as it is always replaced by an algorithm that makes use of positional depiction. We can decompose multipliers into two parts. The first part is committed to the generation of partial products, and the second part collects and then adds them. Figure1: Radix-8 Booth encoded multiplication using Carry Save Adder The above figure represents the output waveform of Radix-8 Booth encoded multiplier using fast carry save adder. The basic operation of it is, multiplier and multiplicand are the input signals and the product is the output signal. Product of the multiplier and multiplicand is mainly based on the formulae X.Y 2 n -1 which is faster compared to the Radix-8 Booth encoded multiplier using carry save adder. Where, X=100 Y=21555 100.21555 2 8-1 Product=58380. The basic principle used for multiplication is to evaluate partial products and accumulation of shifted partial products. In order to perform this operation, the number of successive addition operation is required. Therefore one of the major components required to design a multiplier is Adder. Adders can be Ripple Carry, Carry Look Ahead, Carry Select, Carry Skip and Carry Save [6]. A lot of research work has been done to analyze performance of different fast adders.radix-8 Booth Encoded Multiplier with low delay carry save adder is used for efficient approach to reduce the maximum delay of carry propagation in the final stage of the multiplier. Booth Encoding is an effective method which greatly increases the speed of our algebra.radix8 Booth encoded multiplier which uses carry save adder to generate the sum and carry of partial products. Carry save adder mainly consists of full adders and ripple carry adder. Ripple carry adder constitutes a dominant component of the delay in the parallel multiplier. Signals from the multiplier partial products summation tree do not arrive at the final RCA at the same time. This is due to the fact that the number of partial-product bits is larger in the middle of the multiplier tree. Due to un-even arrival time of the input signals to the final RCA, the selection of the final adder is an important work in parallel multipliers [8]. Therefore decrease in carry propagation delay will result in major enhancement of the speed of the adder and multiplier. The Ripple carry adder which is shown in the below fig constitutes high propagation delay which leads to reduction in the calculation speed of the multiplier. III. Radix-8 Multiplications with Faster Carry save Adder Multipliers are most commonly used in various electronic applications such as Digital signal processing in which multipliers are used to perform various algorithms like FIR, IIR etc. Earlier, the major challenge for VLSI designer was to reduce area of chip by using efficient optimization techniques to satisfy MOORE S law. Then the next phase is to increase the speed of operation to achieve fast calculations like, in today s microprocessors millions of instructions are performed per second. Speed of operation is one of the major constraints in designing DSP processors and today s general-purpose processors. However area and speed are two conflicting constraints. So improving speed results always in larger areas. Now, as most of today s commercial electronic products are portable like Mobile, Laptops etc. that require more battery backup. Therefore, lot of research is going on to reduce power consumption. Modulo 2 n -1 Radix 8 Booth s multiplier has been designed using Faster Carry Save Adder for accumulation of partial products obtained in the process of multiplication [5]. In radix-8 recoding we take quartets of bits. Each quartet is codified as a signed-digit using the table 1: ISSN: 2320 8007 1502

Table 1: Radix-8 Encoding Signed digit Quartet value value 0000 0 0001 +1 0010 +1 0011 +2 0100 +2 0101 +3 0110 +3 0111 +4 1000-4 1001-3 1010-3 1011-2 1100-2 1101-1 1110-1 1111 0 Here we have an odd multiple of the multiplicand, 3Y, which is not immediately available. To generate it we need to perform this previous add: 2Y+Y=3Y. But we are designing a multiplier for specific purpose and thereby the multiplicand belongs to a previously known set of numbers which are stored in a memory chip. We have tried to take advantage of this fact, to ease the bottleneck of the radix-8 architecture, that is, the generation of 3Y. In this manner we try to attain a better overall multiplication time, or at least comparable to the time we could obtain using radix-4 architecture [4]. y7 y7 y 6 y 3 y2 y1 y0 Y ------------------------------------------------------------- s8 s7 s 6 s3 s2 s1 s0 Figure 2: 8-bit previous add In fact, only a 8-bit adder is needed to generate the bit positions from s1 to s8. Bits s0 and s8 are directly known because s0=s0 and s6=y8 (sign bit of the 2s-complement number; 3Y and Y have the same sign). If in the memory from where we take the numbers just two additional bits are stored together with each value of the set of numbers, we can decompose the previous add in three shorter adds that can be done in parallel. In this way, the delay is the same of a 4-bit adder: y 3 y 2 y 1 y 0 y 4 y 3 y 2 y 1 c 1 ------------------------------------------- s 4 s 3 s 2 s 1 y 7 y 6 y 5 y 4 y 7 y 7 y 6 y 5 c 4 --------------------------------------------- s 8 s 7 s 6 s 5 Figure 3: Modified previous add. Bits which are going to be stored are the two intermediate carry signals c 1 and c 4. Before each word of the set of numbers is stored in the memory, the value of its intermediate carries has to be obtained and stored beside it. In this way, they are immediately available when it is required to perform the previous add to get the multiple 3Y of one of the numbers that belongs to the set. The increment in memory requirements is relatively small, and the gain in time is obvious because we substitute a 8 -bit adder by two 4-bit adders which can operate in parallel. In order to get the minimum delay in the previous adder we use high-speed adders. This recoding scheme applied to a parallel multiplier halves the number of partial products so the multiplication time and the hardware requirements decrease. Triplets are taken beginning at position x -1 and continuing to the MSB with one bit overlapping between adjacent triplets. If the number of bits in X (excluding x -1 ) is odd, the sign (MSB) is extended one position to ensure that the last triplet contains 3 bits. In every step we will get a signed digit that will multiply the multiplicand to generate a partial product entering the Wallace reduction tree [2]. This gain is possible at the expense of somewhat more complex operations in every step. However, that the required multiples of Y {0, Y, 2Y} are available by merely shifting Y to the left. Although the algorithms and operations specified above seem rather arbitrary at the first sight, they are based on meaningful number systems [10]. The time taken to compute the sum is then avoided which results in a good improvement in speed.radix-8 Booth encoding multipliers mainly follows the table 3.1.,which clearly explains that the encoding is done is done so that complexity reduces which leads to easy and fast calculations. ISSN: 2320 8007 1503

Modification in Carry save Adder: High-speed addition and multiplication has always been a fundamental requirement of high-performance processors and systems. In digital adders, the speed of addition is limited by the time required to propagate a carry through the adder. The sum for each bit position in an elementary adder is generated sequentially only after the previous bit position has been summed and a carry propagated into the next position. In order to achieve the fast computations, fast carry save adder using carry select adders. Carry Select Adder is used in many computational systems to moderate the problem of carry propagation delay by independently generating multiple carries and then selects a carry to generate the sum. The concept of the carry-select adder is to compute alternative results in parallel and subsequently selecting the correct result with single or multiple stage hierarchical techniques. In order to enhance its speed performance, the carry-select adder increases its area requirements. The goal of fast addition is achieved using Radix-8 Booth encoded multiplier using fast carry save adders, it is possible to perform the addition simultaneously by partitioning the bits into lower and higher parts which is shown in the below Fig. As a result of the addition, partial sum and carry terms are separately generated. And the bits of higher part simultaneously performs addition by using two carry select adders with c in =0 and c in =1.If the c temp of the lower part is 0 or 1 it will select by using the mux. The final result is obtained as sum and carry generated by using the carry save adder and carry select adders. The main advantage of this logic is that each group computes the partial results in parallel and the Muxes are ready to give the final result immediately with the minimum delay of the Mux. When the Cin of each group arrives, the final result will be determined immediately. Thus the maximum delay is reduced in the carry propagation path. Figure4: Radix-8 Booth encoded multiplier using fast carry save adder In carry-select adders both sum and carry bits are calculated for the two alternatives: input carries 0 and 1. Once the carry-in is delivered, the correct computation is chosen (using a MUX) to produce the desired output. Therefore instead of waiting for the carry-in to calculate the sum, the sum is correctly output as soon as the carry-in gets there. IV. Experimental Results The multiplier unit design applying the proposed radix-8 Booth encoding. Multiplier was specified in VERILOG, Simulated in Xilinx12.1The basic operation of it is, multiplier and multiplicand are the input signals and the product is the output signal. Product of the multiplier and multiplicand is mainly based on the formulae X.Y 2 n -1 which is faster compared to the Radix-8 Booth encoded multiplier using carry save adder. Where, X=100 Y=21555 100.21555 2 8-1 Product=58380. Figure5: Xilinx output ISSN: 2320 8007 1504

A full custom design has been chosen in order to reduce the operation delay which is our main goal. So we have applied all the possible simplifications in the design for every multiplier component. Table 2: Comparison Table System Multiplier type Delay(ns) Existing System Proposed System Radix-8 Booth Encoded modulo multiplier using Carry Save Adder. 46.735ns A Faster Carry Save Adder in Radix-8 Booth encoded multiplier 44.632ns V. Conclusion It has been performed the design, and simulation of a 8x8 bit, radix-8, multiplier unit for multimedia and DSP application. The delay is decreased and the speed & power is increased when we use FCSA in radix-8 booth encoded multiplier compare to the CSA in radix-8 booth encoded multiplier. In this paper Fast Carry Save adder is designed and simulated using Verilog HDL [7]. The simulation results and timing analysis of the multiplier are implemented using Xilinx 9.1.The design is optimized for speed using Xilinx, Device Family is Spartan 3E XC3S1200E with speed grade4. VI. Future scope Montgomery modular multiplication algorithm is a well-known method that is employed in efficient modular multiplication architectures and therefore is widely used in elliptic curve applications. The complexity of Montgomery multiplier makes the testing process a big challenge. A methodology for developing testing modules is introduced. Including a self-testing block in the multiplier's system will be beneficial and will reduce the time and effort for testing. A selftesting block will perform Montgomery multiplication of hardwired numbers and compare the result with predefined values. A flag bit can be used to indicate an error. References [1]. Ramya Muralidharan, Student Member, IEEE, and Chip- Hong Chang, Senior Member, IEEE, Radix-8 Booth Encoded Modulo 2n-1 Multipliers with adaptive delay for high dynamic range residue number system, IEEE Transactions on circuits and systems, Vol. 5 no. 5, May 2011. [2]. C.S. Wallace A suggestion for a fast multiplier. IEEE Trans.On Computers, vol.13, pp, 14-17, 1964. [3]. Y.MareswaraRao1, Mr. A. Madhusudan, Radix4 Configurable Booth Multiplier for Low Power and High Speed Applications, IOSR Journal of Electronics and Communication Engineering (IOSR-JECE) ISSN: 2278-2834, ISBN: 2278-8735. Volume 4, Issue 2 (Nov. - Dec. 2012), PP 31-37. [4]. S. Shafiulla Basha1, Syed. Jahangir Badashah2, Design and implementation of Radix-4 based high speed multiplier for alu s using minimal partial products, International Journal of Advances in Engineering & Technology, July 2012. IJAET ISSN: 2231-1963. [5]. G. Dimitrakopoulos and V. Paliouras, A novel architecture and a systematic graph-based optimization methodology for modulo multiplication, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 2, pp. 354 370, Feb. 2004. [6]. S. M. Nowick, K. Y. Yun, A. E. Dooply, and P. A. Beerel, Speculative Completion for the Design of High- Performance Asynchronous Dynamic Adders, In Proc. 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 97),Eindhoven, The Netherlands, April 1997, pp 210-223. [7]. S. Sutherland, Verilog a Guide to the New Features of the Verilog Hardware Description Language, Kluwer Academic Publishers 2001. [8]. S. Tahmasbi Oskuii, P. G. Kjeldsberg, and O. Gustafsson Transition activity aware design of reduction-stages for parallel multipliers, in Proc. 17th Great Lakes Symp. On VLSI, March 2007, pp.120 125. [9]. Yan shi. Fundamentals of Digital Electronics, The Higher Education Press, Beijing, 4th edition 2002. [10]. J. P. Wang, S. R. Kuang, and S. C. Liang, High-accuracy fixedwidth modified Booth multipliers for lossy applications, IEEE Trans.Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 1, pp. 52 60, Jan.2011 ISSN: 2320 8007 1505