Reduced Complexity Wallace Tree Mulplier and Enhanced Carry Look-Ahead Adder for Digital FIR Filter

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1 Reduced Complexity Wallace Tree Mulplier and Enhanced Carry Look-Ahead Adder for Digital FIR Filter Dr.N.C.sendhilkumar, Assistant Professor Department of Electronics and Communication Engineering Sri Indu College of Engineering and Technology Sheriguda Hyderabad 70 Abstract: Improvement of Digital FIR filter is vital role in the field of Digital Signal Processing in order to reduce the area, delay and power. MAC (Multiplication and Accumulation) unit of Finite Impulse Response (FIR) filter has been designed using efficient Multiplier and adder circuits for Optimized APT (Area, Power and Timing) product. In this paper, the design of direct form FIR filter with efficient MAC unit has been presented. Initially, full adder and half adder structures are shrunk down by reducing number of gates. This compact Full adder and half adder structures are incorporated into reduced Wallace Multiplier and improved Carry look-ahead Adder. Reduced Wallace tree multiplier and enhanced carry lookahead adder for digital FIR filter has been proposed in this paper. The proposed 16-bit Carry look-ahead adder has been improved. Consequently the delay of enhanced Carry look ahead Adder is reduced. Generation of carry output is performed using number of OR gates in a sequential manner. All these enhanced architectures are incorporated into the Digital FIR Filter to reduce the area, delay and power utilization. Simulation results are done by using Modelsim 6.3C and synthesized by Xilinx ISE 10.1i design tool. Keywords: Finite Impulse Response (FIR) filter, Multiplication and Accumulation unit (MAC), Reduced Wallace tree multiplier, Carry Look-ahead Adder. 1. Introduction Finite impulse response digital filter is the most important component in communication systems and applications of digital signal processing. Improvements of wireless standards and mobile computing applications have largely demands on low power digital signal processing (DSP) architectures. One of the most important DSP operations for signal processing application is Finite Impulse Response (FIR) filter. FIR filter is a type of digital filter has linear phase and stability characteristics. A large endeavours have been implemented the direct form FIR filter to improve the performance of digital FIR filter. The fundamental of input-output relationship of the Linear Time Invariant (LTI) FIR filter can be expressed as following equation (1) N 1 k k 0 n x n k y c (1) 166

2 Where N denotes the length of FIR filters, c_k represents the filter coefficients and x (nk) denotes the time-shifted input data samples. Most of the applications, in order to attain the high spectral suppressions or noise reduction, FIR filter with huge number of tabs are important. Wallace Tree Reduction is selected for re-arranging the partial product generation. To reduces the complexity of bit products and gives two row matrixes. At last, an efficient adder is required to perform the opretion of addition. Wallace tree is not selected in low power applications because of excess wiring usage that result in extra circuitry and increase in power consumption in the multiplier. Adders are logic circuits designed to perform high speed arithmetic operations and are important in digital systems because of their intensive use in basic operations such as subtraction, multiplication and division. It is widely used in generic computer because it is very important for adding data in the processor. The speed of execution is the most important factor that needs to be considered for appraising the quality of an adder.a carry look ahead adder is a type of adder used in digital logic. It improves the speed by reducing the amount of time required to determine carry bits. It can be contrasted with the simpler, but usually slower, ripple carry adder for which the carry bit is calculated alongside the sum bit, and each bit must wait until the previous carry has been calculated to begin calculating its own result and carry bits. Regular Wallace and reduced Wallace Multipliers are designed using different high speed adders. But it consumes more area, power and less delay.so compact full adder, half adder and ICSA adder are incorporated into Wallace to improve the efficiency of our multiplier. In this paper, reduced Wallace tree multiplier and enhanced carry look ahead has been designed. The main aim of this work is to reduce the area, power and delay. 2. Literature Survey The design of Carry-Look ahead/ Carry-Select Adders have been described in [Yuke Wang, et al, 2002]. In this paper, a new implementation of high-speed 56-bit adder is introduced. The new adder generates the complement Ling s carries for CSAs to select the appropriate sums. Moreover, it directly implements group carry propagates and groups carry generators without using independent carry generator / propagate signals. The 16 bit carry select adder with low area and power has been described in [prof. Mary Joseph and Renji Narayanan, 2014]. The simple and efficient gate level modification helps to reduce the area and power of CSLA. In this paper the proposed design of 16-bit regular SQRT CSLA is compared with modified version of SQRT CSLA. A Suggestion for a Fast Multiplier has been described in [C.S. Wallace, 1964]. The design is developed for a multiplier which generates the product of two numbers using purely combinational logic i.e., in one gating step. A Reduced complexity Wallace Multiplier Reduction has been briefly presented in [Ron S. Waters, et al, 2010]. Wallace high-speed multipliers use Full Adders (FAs) and Half Adders (HAs) in their reduction phase. Half adders do not reduce the number of partial product bits. Therefore, minimizing the number of half adders used in a multiplier reduction will reduce the complexity. 167

3 Lin Jieshan and Huang Shizhen, 2009, analyzed the basic structure and hardware characteristics of the FIR digital filter. Further, they designed method of the FIR filter on the basis of the FIR filter structure. They focused on the introduction of the overall framework of the FIR digital filter adopting the finite state machine as well as the principle of each module of the design. The design was implemented by use of the Verilog hardware description language and each module was verified and simulated by Quartus 8.0 and ModelSim-Altera. [Luu, X.V.et al, 2014] explained a design of unsigned 32-bit multiplier. This architecture consists of a modified Radix-4 Booth encoder, a modified Wallace tree adder and a carry look ahead adder. The altered wallace tree adder sums all the partial products with their complement carry to find the final multiplier. It is done by dividing the summing process into three computation areas :signed area, MSB area and LSB area. The signed area is computed separately with MSB and LSB areas computation. In the MSB and LSB areas computation, a parallel architecture was designed to find the optimum delay. The multiplier can be applied for many implementations which require high-speed property. 3. Reduced Full Adder and Half Adder Structure Half adder and Full adder is the main building block of every adder and multipliers unit. Hence the design of efficient half adder and full adder is performed to reduce the number of gates in order to achieve less area, delay and power utilization. Structure of reduced half adder is given in Figure 1 which reduces one AND gate and one INVERTER compared to existing full adder structure. Structure of reduced full adder is shown in Figure 2 which reduces one AND gate and one OR gate compared to conventional full adder. This compact full adder and half adder can be used in various adder and multiplier to achieve less area, delay and power consumption. Figure 1. Reduced Half Adder 168

4 Figure 2.Reduced Full Adder 4. Carry Look-Ahead Adder A rapid method of adding numbers is called carry-look ahead. This method does not need the carry signal to propagate stage by stage, causing a bottleneck. Instead it uses additional logic to expedite the propagation and generation of carry information, allowing speedy addition at the expense of more hardware requirements. The carry look-ahead logic uses the concepts of generating and propagating the carry bit. Reduced half adder and reduced full adder which is used to modify the carry look ahead adder. Figure 3 shows the structure of 8-bit carry look ahead adder. Figure 3.8-bit Carry Look-Ahead Adder 169

5 5. Reduced Complexity Wallace Tree multiplier and Enhanced Carry look ahead adder A Wallace multiplier is a parallel multiplier which performs multiplication operation effectively. The architecture of reduced complexity Wallace multiplier consists of less number of half adder and full adder to perform partial products. In reduced complex Wallace multiplier, partial products are generated through N2 AND gates and they are arranged in triangle order. The procedure for producing partial products using reduced complexity Wallace multiplier is as follows: 1. The matrix is divided into three row groups in the reduced complexity Wallace multiplier. 2. All three bit combinations are added using full adder. 3. Single bit and a group of two bits are moved to the next stage directly. In the final stage, it requires effective digital adder structure for doing binary addition process. In existing system, modified Carry look ahead Adder is used for addition process. But this requires more number of chip size and delay for implementation. Hence to improve the performance of reduced complexity Wallace multiplier, still we require efficient adder structure. To fulfill this requirement, carry lookahead adder structure is re-designed in this paper. The modified carry look ahead adder effectively reduces the chip size and delay for addition process. Figure 4 shows the reduced complexity Wallace tree multiplier. Figure 4. Reduced Complexity Wallace Multiplier 6. Proposed direct form FIR filter The structure for direct form FIR filter is shown in Figure 5. This structure consists of multipliers, adders and delay units to perform digital filtering operations. From Figure 5, it is clear that the performance of direct form FIR filter is mostly depends on MAC unit. The low 170

6 power or area schemes are developed for FIR filter in previous endeavours. To further improve the performance of digital FIR filter, proposed MAC (reduced complexity Wallace multiplier with help of modified carry lookahead adder) unit is incorporated into direct form FIR filter. When comparing direct form FIR filter using existing reduced complexity Wallace multiplier, the proposed direct form FIR filter with reduced Wallace tree multiplier using modified carry lookahead adder based reduced complexity Wallace multiplier provides better results. In order to attain high spectral suppression and/or noise reduction, digital FIR filters with moderately large number of tabs are essential as shown in Figure 5. Figure 5 Structure of direct form FIR filter 7. Results and Discussion In this paper, efficient MAC unit is designed with help of reduced complexity Wallace multiplier and modified Carry lookahead adder. The design of both reduced complexity Wallace multiplier and modified Carrylookahead adder is done by using Verilog Hardware Description Language (Verilog HDL). The simulation results are designed by using ModelSim 6.3C and synthesis results are evaluated by using Xilinx ISE 10.1i design tool. The simulation result of Reduced Wallace tree multiplier is shown in Figure 6. The simulation result of proposed FIR filter with reduced complexity Wallace tree multiplier using carry look ahead adder is shown in Figure 7. Table 1 shows the comparison between Wallace tree multiplier, Reduced Wallace tree multiplier using carry look ahead adder and proposed direct form FIR Filter with Reduced Wallace tree multiplier using carry look ahead adder. The performance evaluation of proposed FIR filter with reduced Wallace tree multiplier using carry look ahead adder is shown in Figure

7 Figure 6 Simulation result of Reduced Wallace Tree Multiplier Figure 7 Simulation result of Proposed FIR filter with reduced complexity Wallace tree multiplier using carry look ahead adder 172

8 Table 1. comparison of Reduced Wallace tree multiplier using carry look ahead adder and proposed direct form FIR Filter with Reduced Wallace tree multiplier using carry look ahead adder Parameters Slices LUTs Delay(ns) Wallace tree multiplier Reduced Wallace tree multiplier using carry look ahead adder Proposed direct form FIR Filter with Reduced Wallace tree multiplier using carry look ahead adder Percentage reduction% Power (mw) Wallace tree multiplier Reduced wallace tree multiplier using carry look ahead addder 50 0 Slices LUTs delay(ns) power(mw) Figure 8.Performance Evaluation of proposed FIR filter with reduced Wallace tree multiplier using carry look ahead adder. 173

9 8. Conclusion In this paper, high speed and area efficient MAC unit is designed with help of reduced complexity Wallace multiplier and modified carrylookahead adder for digital FIR filter. Conventional reduced Wallace tree multiplier with carry look ahead adder is designed in this paper to reduce the chip size and delay for addition process. This modified carry look ahead adder is incorporated into reduced complexity Wallace multiplier to improve the performance of digital multiplication process. The proposed reduced complexity Wallace multiplier offers 43.5% reduction in area, 55.89% reduction in delay and 9.16% reduction in power when compared to existing reduced complexity Wallace multiplier. Further the proposed reduced complexity Wallace multiplier using carry look ahead adder is incorporated into digital FIR filter to improve the digital filtering performance. In future, the proposed MAC based digital filter will be useful to implementation of parallel FIR filter for wireless standard communication, signal and image processing applications. References [1] Yuke Wang, C.Pai and Xiaoyu Song, 2002 The design of Hybrid Carry-Look ahead/ Carry-Select Adders IEEE Transactions on Circuit and Systems, Vol.49, No.1,pp: [2] prof. Mary Joseph and Renji Narayanan, bit carry select adder with low power and area International Journal on Recent and Innovation Trends in Computing and Communication, Vol.2,Issue.5,pp: [3] C.S. Wallace, 1964 A Suggestion for a Fast Multiplier IEEE Transactions on Electronic Computers, pp: [4] Ron S. Waters, Earl E. Swartzlander, 2010 A Reduced complexity Wallace Multiplier Reduction IEEE Transactions on Computers, Vol.59, No.8, and pp: [5] G. Ganesh Kumar and Subhendu K Sahoo, 2015 Implementation of a High Speed Multiplier for High performance and Low power Applications IEEE Conference. [6] Lin Jieshan and Huang Shizhen, An Design of the 16-order FIR Digital Filter Based on FPGA, The 1st International Conference on Information Science and Engineering (ICISE2009), pp.1-4. [7] Luu, X. V. Hoang, T. T. Bui, T. T. & Dinh-Duc, A. V. A high-speed unsigned 32-bit multiplierbased on booth-encoder and Wallace-tree modifications IEEE International Conference onadvanced Technologies for Communications (ATC), pp , [8] Gowrishankar, V. Manoranjitham, D. and Jagadeesh, P. Efficient FIR Filter Design Using Modified Carry Select Adder & Wallace Tree Multiplier International Journal of Science Engineering and Technology Research (IJSETR), Vol. 2, No. 3, pp: , 2013 [9] Dempster, A. G. & Macleod, M. D. Use of minimum-adder multiplier blocks in FIR digital filters IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol.42, No.9, pp ,

10 [10] Chen, J. Chang, C. H. Fen, F. Ding, W. and Ding, J. Novel Design Algorithm for Low Complexity Programmable FIR Filters Based on Extended Double Base Number System IEEE Transaction on Circuits and Systems,Vol. 62, No.1, pp. 1-10,