DESIGN OF HIGH PERFORMANCE MODIFIED RADIX8 BOOTH MULTIPLIER

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1 International Journal of Mechanical Engineering and Technology (IJMET) Volume 8, Issue 8, August 27, pp , Article ID: IJMET_8_8_4 Available online at ISSN Print: and ISSN Online: IAEME Publication Scopus Indexed DESIGN OF HIGH PERFORMANCE MODIFIED RADIX8 BOOTH MULTIPLIER G. Manmadha Rao and T. Satish Kumar Department of Electronics & communication Engineering GMRIT, Rajam, AP, India. ABSTRACT: This paper presents the performance of the multiplier in terms of high speed and low power parameters. However the multiplication operation is present in many parts of a digital system and mostly used in signal processing applications. Booth algorithm is a crucial improvement in the design of both signed and unsigned numbers. Booth multiplier is generally applied for better performance with the help of its encoding and decreasing the number of partial products. As the radix 8 Booth multiplier is slow due to its complexity in nature. To overcome this modified radix 8 booth multiplier is proposed. In the proposed system Carry Look ahead Adder is used to improve the performance of the multiplier operation. The Modified radix8 booth multiplier is proposed to get better performance in terms of speed and area. Key words: Booth Multiplier, Recoding Adder, Partial product generator, Carry Save Adder and Carry Look ahead Adder Cite this Article: G. Manmadha rao and T. Satish kumar, Design of High Performance Modified Radix8 Booth Multiplier, International Journal of Mechanical Engineering and Technology 8(8), 27, pp INTRODUCTION Day by day IC technology is obtaining additional advanced in terms of its performance analysis. A multiplier with high speed and lower power consumption is required in many fields. In the previous methods, multiplier operation was done by the sequential approaches like Additions, subtractions and shift operations. There are 3 main steps to calculate any multiplication [2]-[5]. They are:. Generation of partial products 2. Reduction of number of partial products 3. Addition of partial products. Any efficient multiplier should have high speed, less area and low power consumption editor@iaeme.com

2 Design of High Performance Modified Radix8 Booth Multiplier. Classification of Multipliers: Figure Classification of Multipliers Generally multipliers are distributed as serial and parallel multipliers. Booths multipliers are come under the parallel multipliers. In parallel multipliers, the performance of the multiplication mainly depends on the number of partial products [3]. Booth algorithm is the best way for multiplying of both signed and unsigned numbers..2 Booth multiplier Booth algorithm is efficient way for calculation and reduction of the partial products. The algorithm gives a brief explanation of binary integers in signed -2 s complement representation [2]. The following steps used for implementing the booth algorithm. Let A and B be two binary numbers and having x and y number of bits (x and y are equal) respectively.. From two numbers, choose multiplier (A) and multiplicand (B). 2. Take 2 s complement of the multiplicand (B) and given for encoding then new bits formed. 3. These bits are multiplied with multiplier (A) and to get partial products. 4. Now these Partial products are used as inputs to the recoding adder and produces carry, sum. 5. Carry and Sum will added to the precise adder to get the output. Design of high performance Modified radix8 Booth Multiplier improves speed and simultaneously reduces the power [9] compared to approximate radix8 Booth multiplier. Previously, Booth s algorithmic rule, Wallace Tree methodology etc. []-[3] are used along with adders like Ripple Carry Adders, Carry Save Adders, Carry Look-ahead Adders, etc. for multiplication. However, we proposed modified Radix 8 Booth s algorithm to reduce the delay by reducing the number of partial products..3 Related work In Approximate radix8 Booth multiplier, two neighboring bits are added to condense the ripple carry propagation between the numbers [] (as an alternative of adding bit each time as in a conventional scheme) with the help of duplication bit in recoding adder. For an example, Take any 2- bit addition ( y y +y y,where i is,2,...,5); the addition result is given as editor@iaeme.com

3 G. Manmadha rao and T. Satish kumar = 2 c + 2 y y + 2 y, i i i i + in i i i + i + 2 i + i 2 c out + 2 si si where ( y,y,y ) are the 3 bits of the multiplicand, y i is the duplication bit, C in is the carry-in from the earlier addition, s i and s i+ are the sum bits of the 2-bit addition, and C out is the carry-out of the 2-bit adder[]. A Booth multiplier consists of encoding, partial product generation, partial product accumulation, Recoding Adder and Parallel Prefix Adder stages. In the radix-8 Booth algorithm, first we have 2 s complement of the multiplicand and then given for encoding [8]. Two bits are formed and these bits are multiplied with multiplier and generate partial products. These partial products are given to recoding adder and produces carry and sum as outputs. This recoding adder output is given to the parallel prefix adder to get final product []. The partial products in the radix-2 and radix-4 algorithms can be simply generated by shifting or 2 s complementation. (). Figure 2 Approximate radix-8 Booth multiplier Approximate radix-8 multiplier is better when compared to the radix-4 algorithm. Approximate radix 8 multiplier suffers from additional delay and low speed due to the usage of recoding adder [9]-[]. To overcome this problem, Modified radix8 booth multiplier is proposed. 2. PROPOSED MODEL The proposed Modified radix8 Booth multiplier is as shown in Fig3. This consists of five major modules: Booth encoding, partial product accumulation, Carry Save Adder and Carry Look Ahead Adder editor@iaeme.com

4 Design of High Performance Modified Radix8 Booth Multiplier Figure 3 Block Diagram of Modified Booth Multiplier. Carry Look ahead Adder is a high speed adder, which is commonly used to determine the carry bits in a less time. In parallel adder circuits, the carry of each full adder stage is attached to the carry input of the following higher-order stage; hence it is also called as ripple carry type adder. Computation time can be decreased by Carry propagator and Carry generator. The carry propagator is used to the next level whereas the carry generator is used to generate the output carry regardless of input carry. For large multiplier bits, the performance of the Modified Booth algorithm is used. So the obtained partial products are collected and added by the use of carry save adder. Carry save adder produces carry and sum. These are added through a Carry Look Ahead Adder (CLA) to get the result. 2. Modified Booth s Algorithm One of the efficient techniques that helps in decreasing the number of partial products and calculation levels. Figure 4 Modified Radix-8 Booth Multiplier Booth encoding table represents the number of ones and zeros present in the encoding. The output bits are calculated with the help of multiplicand which gives the information about sign bit, number of zeros and number of ones editor@iaeme.com

5 G. Manmadha rao and T. Satish kumar b2j+ b2j b2j- Operation Sign Twos ones +(multiplicand) +(multiplicand) +(multiplicand) +2(multiplicand) -2(multiplicand) -(multiplicand) -(multiplicand) -(multiplicand) Table Booth encoding For the design of high performance modified radix 8 booth multiplier the following steps are applied. Let the inputs be Multiplier (A) and Multiplicand (B). a) We take 2's compliment for Multiplicand (B), and then the outcomes are given to modified booth encoding algorithm. b) Then 3 bits are produced. c) These bits are multiplied with Multiplier (A). d) Then we obtain the partial products & these given inputs to the carry save adder. e) These carry and sum are added using carry look head adder.. f) Finally, the multiplier output is obtained. 3. RESULTS 3. Simulation output: The results obtained after implementation of modified radix-8 booth multiplier are as shown in Fig5. The obtained timing reports, Area analysis reports, RTL Schematic diagrams are used to evaluate the performance measures of the proposed multiplier for comparison. The simulation output shows the multiplier output along with multiplier and multiplicand signals when CLK=(high), RESET=(low). Figure 5 Waveform for Radix -8 Booth Multiplier editor@iaeme.com

6 Design of High Performance Modified Radix8 Booth Multiplier Here different multipliers with different adders are implemented and calculated respective delay. Proposed multiplier with Carry Save Adder gave the delay (Gate+Path) of 2.899ns, with Carry Look ahead Adder, the delay (Gate+Path) is 9.76ns and with Combination of both Carry Save Adder and Carry Look ahead Adder, the obtained delay (Gate+path) is 7.27ns. Delay Gate delay Path delay Total delay Approximate radix-8 Booth multiplier Multiplier with Carry save adder Multiplier with Carry look head adder Multiplier with CSA and CLA adder 2.23ns.77ns 23.ns.773ns 9.26ns 2.899ns 9.824ns 9.352ns 9.76ns 8.846ns 8.36ns 7.27ns Table 2 Delay Analysis of Multiplier with different addersthe Table 2 illustrated the Gate, Path and Total delays of Multiplier with different adders. Existing method Multiplier with CSA Multiplier with CLA Adder Multiplier with CSA and CLA adder No. of slices No. of LUTS No of IOB s Table 3 Comparison of Area Analysis The number of slices, LUTs and IOB s are calculated and tabulated in Table3 to know the area of multiplier. 4. CONCLUSION In this paper, The Modified Radix- 8 Booth Multiplier considered to have better performance in terms of delay and area compared to existing approximate radix-8 Booth multiplier. The proposed multiplier with CSA, CLA and both adders are found to be better in terms of delay and area compared to approximate radix-8 Booth multiplier. But proposed multiplier with CLA is found to be better compared to CSA. With the help of both the adders in proposed multiplier, better results obtained compared to all the methods. REFERENCES [] Honglan Jiang, Jie Han Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation IEEE Transactions on Computers, Volume. 65, 26. [2] G Ganesh Kumar, Subhendu K Sahoo Implementation of A High Speed Multiplier for High-Performance and Low Power Applications IEEE Transactions, 25. [3] Arish S R.K.Sharma Run-time reconfigurable multi-precision floating point multiplier design for high speed, low-power applications IEEE Tractions, 25. [4] M. Vinod Kumar Naik, Mohammed Aneesh. Y, Design of Carry Select Adder for low power and High Speed VLSI Applications IEEE Transactions, 25. [5] Jiun-Ping Wang, Shiann-RongKuang High-Accuracy Fixed-Width Modified Booth Multipliers for Lossy Applications IEEE Tractions, editor@iaeme.com

7 G. Manmadha rao and T. Satish kumar [6] Y.-H. Chen and T.-Y.Chang, A high-accuracy adaptive conditional-probability estimator for fixed-width booth multipliers, IEEE Transactions on Circuits and Systems I, volume. 59, no. 3, pp , 22. [7] C. Liu, J. Han, and F. Lombardi, A low-power, high-performance approximate multiplier with configurable partial error recovery, in DATE, 24, p. 95. [8] N. Zhu, W. L. Goh, and K. S. Yeo, An enhanced low-power high- speed adder for errortolerant application, in ISIC. IEEE, 29. [9] Kuan-Hung Chen and Yuan-Sun Chu A Low-Power Multiplier with the Spurious Power Suppression Technique IEEE Transactions27. [] Kyung-Ju Cho, Kwang-Chul Lee, Jin-Gyun Chung, Design of Low-Error Fixed-Width Modified Booth Multiplier IEEE Transactions 24. [] Z. Huang and M. D. Ercegovac, High-performance low-power left-toright array multiplier design, IEEE Trans. Comput., volume. 54, no. 3, pp , Mar. 25. [2] J. S. Wang, C. N. Kuo, and T. H. Yang, Low-power fixed-width array multipliers, in Proc. IEEE Symp. Low Power Electron. Des, 24, pp [3] W. C. Yeh and C. W. Jen, High-speed Booth encoded parallel multiplier design, IEEE Trans. Comput, volume. 49, no. 7, pp , Jul.2. [4] P Nagaraju, DVS Chandrababu, T Ravindra and K Narsimha, 6 Bit Multiplier Implementation Using Vedic Mathematics, International Journal of mechanical engineering and Technology, 8(7), 27, pp [5] ShaziaFathima and Dr. Sardar Ali, Design & Performance of Six Pulse Voltage Multipliers, International Journal of Advanced Research in Engineering and Technology (IJARET), Volume 4, Issue 3, April 23, pp editor@iaeme.com