Optimum Analysis of ALU Processor by using UT Technique

Transcription

1 IJSTE - International Journal of Science Technology & Engineering Volume 2 Issue 10 April 2016 ISSN (online): X Optimum Analysis of ALU Processor by using UT Technique Rahul Sharma Deepak Kumar M. Tech Scholar Assistant Professor Department of Electronics and Communication Engineering Department of Electronics and Communication Engineering Vidhyapeeth Institute of Science and Technology Bhopal, MP, India Vidhyapeeth Institute of Science and Technology Bhopal, MP, India Abstract Now a day's, the main challenge in front of VLSI System designer are to design fast processing system. And the ALU are main functional unit in most digital and high performance systems such as FIR filters, digital signal processors and microprocessors etc. So the performance such VLSI circuit is dependent on the performance of the ALU. And the ALU speed is mainly depends on the speed of multiplier. Here, a High-speed multiplier is designed and analyzed which is based on the algorithm named as Urdhva Tiryakbhyam sutra (UT Technique). Traditionally, this well known Technique has been used for fast multiplication. And analyze in terms of Path delay and there by efficiency. The proposed algorithm is developed using VHDL. Implementation has been done using Xilinx14.2, Spartan 6. Keywords: Vedic mathematics, Adder, Multiplication, Urdhva Tiryakbhyam (UT) Technique, Multiplexer I. INTRODUCTION We know that the ALU is a Computation unit that performs various arithmetic (addition, subtraction, multiplication) and logical operations (AND, OR, INVERTER). And that s why the ALU is called heart of microprocessor, microcontroller and digital signal processor. Every technology uses those operations either fully or partially which are performed by ALU. No technology can exist, without those operations which are performed by ALU. The block diagram of ALU is given below in Figure 1. The performance of Fast processing system is dependent on the speed of the ALU. And the ALU speed is mainly depends on the speed of multiplier. Here, a High-speed multiplier is designed and analyzed which is based on the algorithm named as Urdhva Tiryakbhyam sutra (UT Technique). Which provide following features high speed, less power consumption, and less area or even combination of them in one multiplier. This will used in designing of various high speeds, low power, compact VLSI circuits. Fig. 1: Block Diagram of an ALU The organization of paper starts with a brief introduction that describes in the section I. Thereafter, Section II describes the basic methodology of Urdhva Tiryakbhyam technique. Section III describes the ripple carry adder. Section IV describes the design and implementation of proposed multiplier based on UT Technique module in XilinxISE14.2. Section V comprises of Result and Discussion in which computational path delay obtained. Finally Section VI comprises of Conclusion and future work. II. UT TECHNIQUE Urdhva Tiryakbhyam (UT) technique is sutra of Vedic mathematics used for multiply two given numbers in Decimal number system. However, we put forward the multiplication of two binary numbers using this technique. The literal meaning of UT is Vertically and crosswise and the multiplication happens in this fashion. UT is a novel concept through which introduces a parallel execution of partial products and sums which is explained in figure 2. All rights reserved by 499

2 364 * 455 = Fig. 2: Multiplication of two decimal numbers: 364*455 III. RIPPLE CARRY ADDER A Ripple carry adder (RCA) is a parallel adder that produces the arithmetic sum of two binary numbers. It is composed of cascaded full adders for n-bit adder, as shown in figure 3. It is constructed by cascading full adder blocks in series. The carry out of one stage is fed directly to the carry-in of the next stage. This kind of adder is typically known as Ripple Carry Adder because carry ripples to next full adder. For an n-bit parallel adder it requires n full adders. The layout of Ripple Carry Adder is simple, which allows fast design time. Fig. 3: Block Diagram of n- Bit RCA Adder All rights reserved by 500

3 For an n-bit Ripple Carry Adder Sum and Carry Equation are given bellow. S 0 = A 0 B 0 C in (1) C 0 = A 0 B 0 + B 0 C in + C in A 0 (2) S 1 = A 1 B 1 C 0 (3) C 1 = A 1 B 1 + B 1 C 0 + C 0 A 1 (4) S 2 = A 2 B 2 C 1 (5) C 2 = A 2 B 2 + B 2 C 1 + C 1 A 2 (6) S n 1 = A n 1 B n 1 C n 2 (7) C n 1 = A n 1 B n 1 + B n 1 C n 2 + C n 2 A n 1 (8) IV. PROPOSED MULTIPLIER ARCHITECTURE UT Technique based Multiplier is efficient hardware architecture for multiplying two integers, compared to a normal multiplier; it is mostly used for high speed multiplication. The block diagram of 4 4 bit, 8 8 bit UT Multipliers are respectively given below in Figure 4 and Figure 5. Last two output bit P 8, P 9 (for 4 4 Multiplier) and P 16, P 17 (for 8 8 Multiplier) are Garbage Bits. Fig. 4: Block Diagram of Proposed 4 4 UT Multiplier V. RESULTS AND DISCUSSIONS This paper describes the design and implementation of multiplier based on UT Technique using RCA adder module in XilinxISE14.2 Spartan 6 series. Figure 6 shows RTL Schematic of 8-Bit UT Multiplier. And the table1 shows the device utilization summary and computational path delay of proposed UT multiplier at different Bit levels. All rights reserved by 501

4 Fig. 5: Block Diagram of Proposed 8 8 UT Multiplier Table 1 Analysis of Different Bit UT Multipliers UT Multiplier Number of slices Number of 4 input LUTs Number of Bonded IOBs Used Available Used Available Used Available Delay (ns) 2-BIT BIT BIT Fig. 6: RTL Schematic of 8-Bit UT Multiplier All rights reserved by 502

5 VI. CONCLUSION AND FUTURE WORK In this paper we have proposed an extremely effective method of multiplication based on Urdhva- Tiryakbhyam algorithm. With this method we can construct multiplier of any number of bits, and shows the computational benefits given by UT Technique. Since our objective was to reduce the computational path delay for proposed 8x8 bit UT multiplier is found to be ns, hence we achieved our objective. UT multiplier designs are developed using The Ripple Carry Adder. The Ripple Carry Adder is slowest among all the adders because every full adder must wait till the previous full adder generates the carry bit for its input. If design a multiplier with efficient adder, multiplier gives better performance. REFERENCES [1] Seokin Hong and Soontae Kim A Low-Cost Mechanism Exploiting Narrow-Width Values for Tolerating Hard Faults in ALU IEEE Transactions on Computers, Vol. 64, no. 9, September [2] Garima Rawat, Khyati Rathore, Siddharth Goyal, Shefali Kala and Poornima Mittal, Design and Analysis of ALU: Vedic Mathematics Approach in International Conference on Computing, Communication and Automation, IEEE, [3] M. Ramalatha, K. Deena, Dayalan,Dharani High Speed Energy Efficient ALU Design usingvedic Multiplication Techniques ACTEA IEEE [4] Pushpalata Verma, K. K. Mehta, Implementation of an Efficient Multiplier based on Vedic Mathematics Using EDA Tool, International Journal of Engineering and Advance Technology, Vol.1, no. 5, June, [5] Abhishek Gupta, Utsav Malviya, Vinod Kapse, A novel approach to design high speed arithmetic logic unit based on ancient Vedic multiplication technique, International Journal of Engineering Research and Applications, April Journal of Modern Engineering Research, Vol. 2, no. 4, July, [6] Poornima M, Shivaraj Kumar Patil, Shivukumar, Shridhar K P, Sanjay H, Implementation of multiplier using Vedic algorithm, International Journal of Innovative Technology and Exploring Engineering Vol. 2, no. 6, May, [7] Suchita Kamble, N. N. Mhala, VHDL implementation of 8- bit ALU, IOSR Journal of Electronics and Communication Engineering, Vol. 1, no. 1, May,2012. [8] Rahul Nimje, Sharda Mungale, Design of arithmetic unit for high speed performance using vedic mathematics, International Journal of Engineering Research and Applications 13 April All rights reserved by 503