Implementation of 256-bit High Speed and Area Efficient Carry Select Adder

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1 Implementation of 5-bit High Speed and Area Efficient Carry Select Adder C. Sudarshan Babu, Dr. P. Ramana Reddy, Dept. of ECE, Jawaharlal Nehru Technological University, Anantapur, AP, India Abstract Implementation of high speed, power-efficient and less area designs plays a vital role in many applications ad are research areas of design interest in VLSI. Technology is shrinking from nanometer to micrometer technology in order to meet these design issues. Adder is one of the designs which are used in many applications like DSP s, ALU s, subtractions and high speed multiplications. In the traditional adder designs, the main design area is concentrated on the power factor and not on the speed performance. But the performance of any design can be increased to a great extent by improving the speed of operation of the design. So this paper mainly focuses on the high speed adder design which is nothing but Carry Select Adder (CSLA). CSLA is one of the adder designs which improve the speed of addition operation to a great extent when compared to traditional adder designs. This increased speed and less area application design can be implemented by modifying the Regular adder design by replacing some of the gates with the implemented complex BEC logic which leads to Modified Carry Select Adder design. Based on this design idea,, 4, 8 and 5-bit Modified CSLA design have been developed and compared with Regular adder design. Based on this design approach the delay reduces to 5.8 ns and area to 8 when compared to delay of the Regular design of 4.4 ns and area of 89 LUT s of 5-bits. Keywords Adder, Area Modified CSLA, RCA, Regular CSLA, Speed I. Introduction In electronics, an adder or summer is a digital circuit that performs addition of numbers. In many computers and other kinds of processor applications, adders are used not only in the arithmetic logic unit, but also in other parts of the processor, where they are used to calculate addresses, table indices, etc []. Although adders can be constructed for many numerical representations, such as binary-coded decimal or excess-, the most common adders operate on binary numbers. In cases where two s complement or ones complement is being used to represent negative numbers, it is trivial to modify an adder into a subtraction []. For high performance designs, processors with the high-speed addition and multiplication have always been a fundamental requirement. The speed of addition majorly depends upon carry propagation time which is propagated from the lower group bits to the next higher group []-[5]. In electronics, a carry-select adder is a particular way to implement an adder, which is a logic element that computes the (n+)-bit sum of two n-bit numbers []-[8]. The carry-select adder is simple but rather fast, having a gate level depth of ( n). The carry select adder generally consists of two ripple carry adders and a multiplexer. Adding two n-bit numbers with a carry-select adder design is done with two adders in order to perform the calculation twice, one time with the assumption of the carry being zero and the other assuming one. After the two results are calculated, the correct sum, as well as the correct carry, is then selected with the multiplexer once the correct carry is known. Table : Asymptotic Time and Area of Different Adder TIME AREA RCA O(n) O(n) CLA O(log n) O(n log n) PARALLEL- PREFIX CLA O( log n) O(n log n) CSA O n O(n) This work in brief is structured as follows. Section II deals with the delay and area evaluation methodology of the multiplexer block with its corresponding delay and area values. Section III deals with the structure and function of BEC logic and its corresponding function table and logic equations. Section IV presents the implementation architecture of the Regular CSLA of 5-bits. The implementation architecture of the Modified SQRT CSLA is presented in Sections V. In section VI simulation results and corresponding design tools are explained and finally the paper is concluded in section VII. II. Multiplexer Block and its Delay and Area Calculation In this we calculate and explain how the delay and area affects the total design using the theoretical approach and will show how the delay and area will affect our total CSLA implementation. Using AND, OR and INVERTER, any complex design can be implemented. The delay and area calculation methodology considers each gate will be having delay equal to unit and area equal to unit. From the design longest path is calculated and it shows the maximum delay of the implementation from starting of input bits to ending of output bits. The total number of AOI gates gives the gate count for area calculation. Figure shows the : design implementation using AOI gates only. Table shows the gates and area counts obtained for different designs. From the table it is clear that area and delay increases if the design includes more number of gates. Fig. : : Logic with Delay and Area Table : Delay and Area Evaluation of Basic designs Design Delay Area XOR : Half Adder Full Adder International Journal of Electronics & Communication Technology

2 ISSN : -79 (Online) ISSN : -954 (Print) -bit BEC -bit I/P 4: -bit O/P -bit RCA Fig. : -bit BEC with 4: Multiplexer Fig. shows the basic structure of addition operation which is used in Modified CSLA design having -bit input data. Here a -bit BEC logic, -bit RCA and a 4: multiplexer are used for the adder implementation. The input carry is a binary value having ( or ) which is generated by lower order group bits. For = input carry the addition performed by ripple carry adder is selected and for C in = the the data from the BEC is selected. The resultant among the two is selected based on carry in signal generated from the previous group. The total delay of the carry generated by this group depends on multiplexer delay and signal generated from the previous group. The -bit output from the multiplexer are the final sum obtained, and the carry signal from the multiplexer is used as a selection line to the multiplexer in higher order group. This is the major logic block in the Modified CSLA design. III. Structure and Function of Binary to Excess- Logic This section explains the BEC logic design and its importance in our presented design. The basic idea of this implementation is to replace RCA with C in = Regular CSLA with BEC in order to get less area and increased speed of operation when compared with traditional designs. The BEC logic of different bits can be designed using Boolean expressions and hence it provides better alternation of the adder design. BEC logic can be designed using the equations of different order bits which are shown below. For the design of -bit adder by using the traditional RCA, it requires FA which occupies an area of 5 gates (*) and the delay of 8 (*). But for the same -bit adder implementation using BEC requires only gates and it has only 5 gate delays, which is a good alternation of adder design. So, this logic can be replaced in RCA with = in Regular design so that it increases the speed of operation and having less area. In order to replace the n-bit RCA in Regular design, n+ bit BEC logic is required. The structure and of a -bit BEC are shown in fig.. IJECT Vo l., Is s u e 4, Oc t - De c The expressions for the -bit BEC logic are shown below X = ~B X = B^B X = B^ (B & B) X = B^ (B & B & B) X4 = B4^ (B & B & B & B) X5 = B5^ (B & B & B & B & B4) The Boolean expressions shown above are implemented in gate level using the AND, INVERTER and XOR gates. These Boolean expressions can be increased to any number of bits according to our application and the corresponding RCA is replaced with this new BEC logic design. By comparing the BEC logic design with Regular -bit adder RCA design using the Xilinx version, the area and delay of the BEC design is less when compared with Regular RCA design, which makes the BEC design is more suitable for the fast processing and less area design applications. IV. Implementation of 5-BIT Regular SQRT CSLA A traditional carry select adder can be implemented in two different modes, namely uniform block mode and variable block mode [9]. In uniform block mode the data bits are divided into groups which are of uniform(equal) size for entire design, similarly in variable block mode the data bits are divided into different groups of variable(not equal) sizes. Among the two modes of design variable mode is highly recommended design, because the propagation time of carry in this mode takes less when compared with uniform design. The implementation architecture of Regular 5-bit SQRT Carry Select Adder is shown in Figure 4. The design is first divided into different groups of variable sizes. Each group has some bit length of different sizes []. These bit lengths are developed using two Ripple Carry Adder (RCA) and a multiplexer to each group excluding the Group, because it is having only one RCA corresponding to that group, so there is no need of multiplexer to select the data. Starting from the Group, it contains only one -bit RCA, which adds up the data input bits which are supplied and the input carry and results a sum [:] and also the carry out bit. The carry out which is generated by Group will act as a selection line for the next higher group in the series which is nothing but Group. Based on the selection line from Group, the multiplexer selects the corresponding upper RCA (C in =) or lower RCA (C in =). Similarly the pattern continues for the remaining groups depending on the Cout. The delay and the corresponding area values are tabulated in Table. Fig. : -Binary to Excess- Converter International Journal of Electronics & Communication Technology 5

3 A[55:4] B[55:4] A[8:5] B[8:5] A[4:] B[4:] A[:] B[:] :4 RCA 8:5 RCA 4: RCA : RCA 55:4 RCA 8:5 RCA 4: RCA 44 4: C C 8 :5 8:4 4 Cout SUM[55:4] SUM[8:5] SUM[4:] Fig. 4: Implementation of Regular 5-bit SQRT CSLA Architecture C C SUM[:] V. Implementation of 5-Bit Modified SQRT CSLA The implementation for the proposed method is designed for 5- bit and this is named as Modified 5-bit SQRT CSLA. When compared with Regular design the Modified design is obtained by replacing RCA in Regular design with = with a complex BEC logic [-4]. The greatest advantage of this BEC logic is that, it has a feature that it can perform the similar addition operation as that of the RCA with = in Regular design meeting the design constraints. Fig. 5 shows the Modified block diagram of 5-bit SQRT CSLA. The Modified method can be implemented by first dividing the complete architecture into various groups of variable size or uniform size. Here it is also implemented using the variable size bit pattern which is having the advantage of less delay when compared with uniform size pattern. The same architecture division is performed in the Modified method as that of Regular method in order to differentiate both the designs. Here the main difference in the design comes from the BEC logic design which is instantiated in the Regular design and the use of second multiplexer for carry bits in each group in order to get the carry bit output with less delay. Based on the design considerations Group contain only one RCA, having input of lower significant bit and a carry in bit and produces sum [:] and carry out as an output bits, and multiplexer of higher group has selection input from the lower group carry output bit. The delay calculation of this Modified design is calculated as follows C is the carry output from Group has the delay of five gate delays which is acted as input to multiplexer. Based on this value it is clear that C arrival time is earlier than the results computed by the RCA and BEC, so it has to wait until the results are computed, after the results are computed, C will select the corresponding results which leads to some delay at the Group. For the remaining groups the arrival time of mux selection input time is later than the RCA and BEC results computation time and also a second set multiplexer selects the carry bit computation which leads to speed of operation. So, these steps progresses for higher order bits and computes results in less time. The Modified CSLA architecture is implemented first for Full Adder and Multiplexers of 8:4, :5, and : up to 4: were designed. Then,, 4, 5 up to -bit ripple carry adder was designed, and corresponding BEC logic also implemented. GROUP 8 A [55:4] B [55:4] GROUP A [8:5] B [8:5] 4 4 GROUP GROUP A [4:] B [4:] A [:] B [:] Cout : 55:4 RCA : 8:5 RCA : 4: RCA : RCA -BIT BEC 4: BIT BEC :5 4-BIT BEC 8:4 SUM [55:4] SUM [8:5] Fig. 5: Implementation of Modified 5-Bit SQRT CSLA Architecture International Journal of Electronics & Communication Technology SUM [4:] SUM [:]

4 ISSN : -79 (Online) ISSN : -954 (Print) IJECT Vo l., Is s u e 4, Oc t - De c Table : Comparison Table for Regular & Modified CSLA Sl. No. Adders Delay (ns) Area. bit. bit. 4 bit Regular.7 4 Modified Regular.9 9 Modified Regular Modified Fig. : RTL Schematic Diagram of Regular 5-bit CSLA 4. 8 bit 5. 5 bit Regular Modified Regular Modified VI. Simulation Results The simulation is done both for Regular and Modified methods having different bit patterns (,, 4, 8 and 5-bits). These are designed using verilog code which is a hardware description language for writing codes. The functional simulation which is used for functionality checking of the design whether it has met the constraints are not using the simulator tool Modelsim [5]. For this implementation the total architecture is divided into independent modules and is programmed independently. After the complete architecture is coded, all these modules are instantiated in the top module. This top module is simulated in the Modelsim software for checking the functionality by running the program. After functional simulation constraints have met, the different bit size V files are synthesized using Xilinx ISE 9.i version []. This can be done by importing the simulated V (verilog) files into the synthesized tool and the corresponding values of delay and area are noted by running the program. If check syntax is checked with no errors the design is synthesized successfully and can view the RTL schematic and technology diagram of the designs. Similarly this method is implemented for all the bit patterns (,, 4, 8 and 5). Table shows the delay and area values obtained after synthesizing all the different size Modified CSLA codes using the Xilinx ISE 9.i synthesizer. By comparing the Regular and Modified CSLA of various bits which includes delay and area comparisons clearly shows that the delay values of the Modified CSLA decreases gradually from -bit to 5-bit when compared with Regular method. Similarly the table also shows the area comparison for the various bit patterns from -bit to 5-bit. The values of areas noted in the table shows that the area (which is calculated as number of (LUT s and SLICES) values are nearly equal from - bit to 4-bit, which then decreases rapidly from 8-bit method. For 5-bit method the area still more decreases when compared with Regular method. Fig. 7: RTL Schematic Diagram of Modified 5-bit CSLA Fig. and 7 shows the RTL Schematic diagrams of 5-bit Regular and Modified CSLA implementation. From the figures we can notice that the design is divided into blocks which are coded in the verilog program as RCA and BEC blocks. The multiplexers are synthesized between the RCA and BEC. The wires are connected between each and every block, so that adder operation is implemented. The hardware complexity can be clearly noticed in the Regular design of Figure which having more wire connections which increases delay and having more number of gates when compared with Regular method. VII. Conclusion An efficient approach is presented in this paper which been an alternative implementation for less area and high speed application of adder design. This has been attained by modifying the logic blocks in Regular design architecture which leads to Modified CSLA architecture. The results shows that the area and delay of the Modified design will still decreases for higher order bits, because many applications works on large number of data bits. The reduction in area and delay is obtained by replacing the RCA with BEC and using another multiplexer for the fast propagation of carry in the Regular architecture. The results which are obtained for various bit patterns shows that using Modified method the area and delay will decrease rapidly thus leads to be a good alternative design for adder implementation. References [] O. J. Bedrij, Carry-select adder, IRE Trans. Electron. Comput., pp [] Kim Y, Kim LS, 4-bit carry-select adder with reduced area, Electron. Lett., Vol. 7, No., pp. 4 5, May, May. [] Padma Devi, Ashima Girdher, Improved Carry Select Adder with Reduced Area and Low Power Consumption, International Journal of Computer Applications, Vol., No. 4, June. [4] Burch, J. B., Long, D. E., Efficient Boolean Function Matching, Proc. Int l Conf.,. [5] B. Ramkumar, H. M. Kittur, P.M. Kannan, ASIC implementation of modified faster carry save adder, Eur. J. Sci. Res., Vol. 4, No., pp [] Hauck, C., Cheng, C.,"VLSI Implementation of a Portable MHz -Bit RISC. International Journal of Electronics & Communication Technology 7

5 [7] E. Abu-Shama, M. Bayoumi, ANew cell for low power adders, inproc.int. Midwest Symp. Circuits and Systems, 995, pp [8] D. G. Chinnery, K. Keutzer, Closing the gap between ASIC and custom: An ASIC perspective, Proceedings of the 8th Design Automation Conference, Las Vegas, NV, June, [9] ST-C Instruction Set Reference Manual, STMicroelectronics, 7-TRN-7-, November 997. [] T.Y. Ceiang, M. J. Hsiao, Carry select adder using single ripple carry adder, Electron. Lett, Vol. 4, No., pp., Oct 998. [] IEEE Std. 4-, IEEE Standard Verilog r_ Hardware Description Language, pp. 85. [] C. E. Cummings, Nonblocking assignments in verilog synthesis, coding styles that kill!, SNUG-, San Jose, CA,. [] Das K., Brown R.,"Evaluation of Circuit Approaches in Partially Depleted SOI-CMOS, IEEE Int. SOI Conference, pp [4] J. M. Rabaey,"Digtal Integrated Circuits A Design Perspective", Upper Saddle River, NJ: Prentice-Hall,. [5] Nève A., Flandre D., Branch-Based Logic for High Performance Carry-Select Adders in.5 um Bulk and Silicon-On-Insulator CMOS Technologies, PATMOS, pp [] [Online] Available: C. Sudarshan Babu received his B.Tech Degree in Electronics & Communication Engineering from St. Johns College Of Engineering & Technology, Andhra Pradesh, India. Presently he is doing his M.Tech in Digital Systems and Computer Electronics (DSCE) specialization in the Department of Electronics & Communication Engineering from Jawaharlal Nehru Technological University, Anantapur, India. His research interest includes Low Power VLSI, Micro Processors and Digital Communications. 8 International Journal of Electronics & Communication Technology