IMPLEMENTATION OF AREA EFFICIENT AND LOW POWER CARRY SELECT ADDER USING BEC-1 CONVERTER

Transcription

1 IMPLEMENTATION OF AREA EFFICIENT AND LOW POWER CARRY SELECT ADDER USING BEC-1 CONVERTER Hareesha B 1, Shivananda 2, Dr.P.A Vijaya 3 1 PG Student, M.Tech,VLSI Design and Embedded Systems, BNM Institute of Engineering and Technology, Bangalore, India 2 Associate Professor, VLSI Design and Embedded Systems, BNM Institute of Engineering and Technology, Bangalore, India 3 HOD of Electronics and Communication, VLSI Design and Embedded Systems, BNM Institute of Engineering and Technology, Bangalore, India Abstract Presently a days Carry Select Adder (CSLA) is one of the quickest adders utilized as a part of numerous data-processing processors to perform quick number juggling capacities. From the structure of the CSLA, obviously there is extension for lessening the area and power utilization in the CSLA. This work utilizes a productive gate-level adjustment to altogether lessen the area and power of the CSLA. Taking into account this change 8, 16, 32, and 64-b square-root CSLA (SQRT CSLA) architecture have been produced and contrasted and the regular SQRT CSLA architecture. The proposed plan has decreased area and power as contrasted and the regular SQRT CSLA with just a slight increment in the delay. This work assesses the execution of the proposed outlines as far as delay, area, power, and their items by hand with legitimate exertion and through specially craft and design in tsmc 0.18-micro meter CMOS process technology. The outcomes examination demonstrates that the proposed CSLA structure is superior to the regular SQRT CSLA. Keywords SQRT CSLA(square root carry select adder), BEC-1(Binary to excess-1 converter), RCA(Ripple carry adder), MUX(Multiplexer) I. INTRODUCTION The arithmetic logic unit (ALU) is the essential part of the every microprocessor and determines its throughput. The core of the every ALU is adder, so that high performance Adder is essential for each and every microprocessor s to increases their speed. However, the high data activity associated with this unit results in high power and thermal density leading increased cooling costs. Thus there is a need for breakthrough ideas in VLSI design methodology to reduce the adder power consumption while maintaining the high performance target. There are several ways to design an Adder. Ripple carry adder has the very most compact design but it has slowest in speed. If the Ripple carry adder is N-bit, then the delay is linearly proportional to an N. Thus for large number of bits the Ripple carry adder gives the highest delay of all adders. Whereas the Carry look-ahead adder is the fastest adder but it will consumes more area. If there is an N-bit adder, Carry look-ahead adder is fast for N<=4, but for more than that highest number of bits the delay will increases more than that other adders, therefore for larger number of bits, Carry select adder gives large delay than the other adders, because of the existing of an large number of logic gates. Carry select adder consumes less area with longer delay Ripple carry adder and then the larger area with shorter delay Carry look-ahead adder. In electronic application, adders are most widely used. It has used in many more applications like multipliers, digital signal processing to execute various algorithms FIR, IIR and FFT and it also known that millions of instruction per second were performed in microprocessors. While designing a multiplier the important constraint will be a speed of operation. Due to the device portability miniaturization of the device should be very high and the consumption of power should be low. The main concern of the quickly developing mobile industry is not only about the faster units, but also lesser area and power will be the major constraints for designing a digital circuit. In order to All rights Reserved 134

2 portability and battery life of an electronic device to fundamental aspects are to reduce power consumed and area miniaturization. Many researches have been conducted on VLSI system design in which the most significant domain is area designing and efficient power system for high speed data-path logic systems. Addition of speed is measured by the time taken by the carry to propagate through adders which is one of the limitations in a digital adder. In an adder the sum will be generated for each bit. Compare to all others various adder, the carry select adder is intermediate regarding area and speed. By independently generating multiple carries the problems in carry propagation delay can be alleviate and this is selected for generating the sum in CSLA which is used in many systems for computation. By substituting Cin=0 and Cin=1 partial sum and carry are generated by using multiple pairs of Ripple Carry Adders (RCA) which is not area efficient in CSLA, thus by multiplexer final sum and carry are selected. To achieve low area and power consumption in a regular CSLA instead of using RCA with C in =1, Binary to Excess-1 Converter (BEC) is utilized which is the concept behind this project. Logic gates utilized by the BEC are less when compared to n-bit full adder (FA) structure which is the main advantage for this project. Two ripple carry adders and a multiplexer are the basic building block for a carry-select adder. To perform the calculation twice two adders are used (ripple carry adder) for addition of two n-bit numbers.in step one calculation the carry is assumed to be zero and the in step two the carry is assumed to be one. Once the correct carry is known by selecting multiplexer, the correct sum and carry are selected after the two results are calculated.in each carry select block the number of bits variable or uniform. For a block size of n in case of uniform the optimal delay occurs. In order to calculate the carry out just in time, delay has to be added in the block size, from addition inputs A and B to the carry out, equal to that of the multiplexer chain leading into it in variable inputs. To yield equal number of MUX delay, the square root of the number of bits being added is equal to the square root of the number of bits being added in an ideal full adder elements per block in a uniform sizing,delay (o( n)delay is derived from uniform sizing. Fig 1 3-Bit Binary to Excess-1 Converter Fig 2 Delay and Area Evaluation of an XOR Gate Table 1 Function Table of 3-Bit BEC B[2:0] X[2:0] All rights Reserved 135

3 Table 2Delay and Area count of the blocks of CSLA Adder Blocks Delay Area XOR 3 5 2:1 Mux 3 4 Half Adder 3 6 Full Adder 6 13 II. BINARY TO EXCESS-1 CONVERTOR (BEC) BEC is the circuit used to add a 1 to the input numbers. 3-bit BEC circuit will be shown in Fig 1. And the truth table is shown in table 1. The Binary to excess-1 converter is used to reduce the gate level, in order to reduce the power and area, use n+1 Binary to excess-1 converter replaced by an n RCA. Fig 1 shows 3-bit Binary to excess-1 converter. The BEC output(b2, B1 and B0) will be given to an 6:3 mux, and RCA with Cin=0 will given to another input for the mux. Then these two produces a partial outputs in parallel, then mux will be decided whether BEC output or the direct inputs depending upon the control signal Cin. The main importance of the usage of the BEC-1 converter is to reduce the silicon area. The Boolean expression of the 3-bit BEC are shown below: X 0 = ~B 0 X 1 = B 0 B 1 X 2 = B 2 (B 1 B 0 ) III. DELAY AND AREA CALCULATION The XOR gate can be implemented by AND, OR and Inverter(AOI) are shown in Fig 2. the delay contributed by each gate can be shown by numeric values, parallel operations can be performrd by a dotted line between the gates. All the gates would be made up of AND, OR and Inverter, in an evaluation methodology of delay and area, 1 unit of an area will be having an one unit of delay. The maximum delay can be calculated by add up the number of gates in a longest path. Thestructureofthe16-bregular SQRT CSLAisshowninFig.3.It hasfivegroupsofdifferentsizerca.thedelayandareaevaluationof eachgroupareshowninfig.4,inwhichthenumeralswithinspecify the delay values, e.g., sum2 requires 10 gate delays. The stepsleading to the evaluation are asfollows. 1. The group2 has two sets of 2-bit RCA. Based on the consideration of delay value is the arrival time of selection input C 1 of 6:3 multiplexer is earlier than S 3 and later than S 2. Thus, S 3 is summation of C 2 and multiplexer and S 2 is summation of C 1 and multiplexer. 2. Except for group2, the arrival time of multiplexer selection input is always greater than the arrival time of data outputs from the RCA s. Thus, the delay of group3 to group5 is determined, respectively as All rights Reserved 136

4 {C 6, Sum [6:4]} = C 3 + Multiplexer {C 10, Sum [10:7]} = C 6 + Multiplexer {C out, Sum [15:11]} = C 10 + Multiplexer 3. The one set of 2-bit RCA in group2 has 2 FA for Cin=1and another set has 1 FA and 1 HA for Cin=0 Based on the area count of Table I, the total number of gate counts in group2 is determined as follows: Gate Count =57(FA+HA+Mux) FA=39(3 13) HA=6(1 6) Mux=12(3 4) 4. Similarly, the estimated maximum delay and area of the other groups in the regular SQRT CSLA are evaluated and listed in Table III. Fig. 6. Delay and area evaluation of modified SQRT CSLA: (a)group2, (b) group3, (c) group4, and (d) All rights Reserved 137

5 TABLE 3Area count of regular SQRT CSLA groups Word Size Adder Area (no. Of Gates) 8-bit MCSLA bit MCSLA bit MCSLA bit MCSLA 1307 utilizing BEC for RCA with to improve the area and power is appeared in Fig.5. We again split the structure into five groups. The deferral and region estimation of every group are appeared in Fig. 6. The strides prompting the assessment are given here. 1. The group2 has one 2-bit RCA which has 1FA and 1 HA for Cin = 0. Rather than another 2- bit RCA with a 3-bit BEC is utilized which adds one to the yield from 2-bit RCA. Taking into account the thought of deferral qualities is the landing time of determination information C1 [time (t) = 7] of 6:3 multiplexer is sooner than the S3 [t = 9] and C3 [t = 10] and later than S2 [t = 4]. In this manner the sum3 and last C3 (yield from multiplexer) are relying upon S3 and multiplexer and fractional C3 (contribution to multiplexer) and multiplexer, separately. The sum2 relies on upon C1 and multiplexer. IV. DELAY AND AREA EVALUATION METHODOLOGY OF MODIFIED 16-BIT SQRT CSLA 1. The structure of the proposed 16-b SQRT CSLA utilizing BEC for RCA with to improve the area and power is appeared in Fig.5. We again split the structure into five groups. The deferral and region estimation of every group are appeared in Fig. 6. The strides prompting the assessment are given here. 2. The group2 has one 2-bit RCA which has 1FA and 1 HA for Cin = 0. Rather than another 2-bit RCA with a 3-bit BEC is utilized which adds one to the yield from 2-bit RCA. Taking into account the thought of deferral qualities is the landing time of determination information C1 [time (t) = 7] of 6:3 multiplexer is sooner than the S3 [t = 9] and C3 [t = 10] and later than S2 [t = 4]. In this manner the sum3 and last C3 (yield from multiplexer) are relying upon S3 and multiplexer and fractional C3 (contribution to multiplexer) and multiplexer, separately. The sum2 relies on upon C1 and multiplexer. Fig.5 Modified 16-b SQRT CSLA. The parallel RCA with Cin=1 is replaced with All rights Reserved 138

6 Fig. 6. Delay and area evaluation of modified SQRT CSLA: (a)group2, (b) group3, (c) group4, and (d) group5. 3. For the remaining group's the entry time of multiplexer choice info is constantly more prominent than the landing time of information inputs from the BEC's Thus, the postponement of the remaining groups relies on upon the landing time of multiplexer choice info and the multiplexer delay. 4. The territory count of the altered CSLA is gotten from the accompanying strides. From the structure of the MCSLA 8-bit, 16-bit, 32-bit and 64-bit region is figured. 5. The area count of the group2 is determined as Gate Count=43(FA+HA+Mux+BEC) FA=13(1 13) HA=6(1 6) Mux=12(3 4) BEC: AND=1 NOT=1 XOR=10(2 5) TABLE 4Area count of modified SQRT CSLA Word Size Adder Area (no. Of Gates) 8-bit MCSLA bit MCSLA bit MCSLA bit MCSLA All rights Reserved 139

7 Word size 16 bit 32-bit International Journal of Modern Trends in Engineering and Research (IJMTER) 6. Similarly, the assessed most extreme postponement and zone of alternate groups of the adjusted SQRT CSLA are assessed and recorded in Table IV. Comparing Tables III and IV, it is clear that the proposed 64-bit modified SQRT CSLA saves 412 gate areas than the 64-bit regular SQRT CSLA,with small increasing in the gate delays. To further evaluate the performance, we have resorted to Cadence implementation andsimulation. Table 5Comparison of Regular and Modified CSLA Word size Carry select adder Area(in um 2 ) Power(in µw) Delay(in ns) 8 bit Existing system Proposed system bit 32-bit Existing system Proposed system Existing system Proposed system bit Existing system Proposed system Fig. 8.(a)Reduction in the cell area, total power, and delay of existing and modified sqrt CSLA V. CONCLUSION A straight forward methodology is proposed in this paper to diminish the area and power of SQRT CSLA architecture. The decreased number of gates of this work offers the immense favorable position in the diminishment of area furthermore the overall power. The looked at results demonstrate that the modified SQRT CSLA has a marginally bigger delay, yet the area and power of the 64-b modified SQRT CSLA are fundamentally lessened by 21.3% and 20.35% separately. This shows the accomplishment of the strategy and not a minor tradeoff of delay for power and area. The modified CSLA architecture is in this way, low area, and low power, straightforward and proficient for VLSI equipment usage. It is fascinating to test the outline of the modified 128-b SQRT All rights Reserved 140

8 REFERENCES [1] Anitha Kumari R D, Nayana N D, Low power and Area Efficient Carry Select Adder, National Conference on Electronics, Communication and Signal Processing, NCECS [2] Bedrij O.J, Carry-select adder, IRE Trans. Electron. Comput., pp , [3] Ceiang T Y and Hsiao M J, Carry-select adder using single ripple carry adder, Electron. Lett., vol. 34, no. 22, pp , Oct [4] Jeong.W and Roy.K, Robust high-performance low power adder, Proc. of the Asia and South Pacific Design Automation Conference, pp , [5] He Y, Chang C H, and Gu J, An area efficient 64-bit square root carry select adder for low power applications, in Proc. IEEE Int. Symp. Circuits Syst., 2005, vol. 4, pp [6] Hosseinghadiry M, Mohammadi H and Nadisenejani M, '' Two New Low Power High Performance Full Adders with Minimum Gates", World Academy of Science, Engineering and Technology [7] KeivanNavi and NedaKhandel, The Design of a High-Performance Full Adder Cell by Combining Common Digital Gates and Majority Function, European Journal of Scientific Research, ISSN X Vol.23 No.4 (2008), pp [8] Kim Y and Kim L S, 64-bit carry-select adder with reduced area, Electron.Lett., vol. 37, no. 10, pp , May All rights Reserved 141