OPTIMIZATION OF PERFORMANCE OF DIFFERENT VEDIC MULTIPLIER

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1 OPTIMIZATION OF PERFORMANCE OF DIFFERENT VEDIC MULTIPLIER 1 KRISHAN KUMAR SHARMA, 2 HIMANSHU JOSHI 1 M. Tech. Student, Jagannath University, Jaipur, India 2 Assistant Professor, Department of Electronics and Communication, Jagannath University, Jaipur, India ABSTRACT The basic objective of this work is mainly to optimization of performance of Vedic multiplier. In this work we are basically worked for reducing the delay in case of its operation. We used the pipeline technique to reduce the delay. The 4 4 Vedic multiplier module using Urdhva Tiryakbhyam Sutra uses four 2 2 Vedic multiplier modules. Urdhva Tiryakbhyam Sutra is most powerful Sutra, giving minimum delay for multiplication of all types of numbers, either small or large. Urdhva Tiryakbhyam Vedic method for multiplication which strikes a difference in the real process of multiplication itself. It causes parallel generation of intermediate products, removes unwanted multiplication steps with zeros and scaled to higher bit levels. The main focus is on the speed/delay of the multiplication operation on 4 bit multipliers which are modeled using VHDL, A hardware description language. The 4 4 Vedic multiplier is coded in VHDL, synthesized and simulated using Xilinx ISE 9.2e software. The synthesis results show that the computation time for calculating the product of 4x4 bits is ns for Ripple Carry Adder. KEYWORDS: Vedic Multiplier, Ripple Carry Adder, VHDL Simulation, pipeline technique. 1. INTRODUCTION Vedic mathematics is part of four Vedas (books of wisdom). It is part of Sthapatya Veda (book on civil engineering and architecture), which is an upa veda (supplement) of Atharva Veda. It covers explanation of several modern mathematical terms including arithmetic, geometry (plane, co ordinate), trigonometry, quadratic equations, factorization and even calculus. INTERNATIONAL JOURNAL OF SCIENCE, ENGINEERING AND TECHNOLOGY

2 Vedic mathematics [1] is the ancient Indian method of mathematics which mainly deals with Vedic mathematical formula and their application to various branches of mathematics. Vedic mathematics was reconstructed from the ancient Indian scriptures (Vedas) by Sri Bharati Krisna Tirthaji ( ) after his eight years of research on Vedas [1]. According to his research, Vedic mathematics is mainly based on sixteen principles which are termed as Sutras. These Sutras along with their brief meanings are enlisted below alphabetically. 1) (Anurupye) Shunyamanyat If one is in ratio, the other is zero. 2) Chalana Kalanabyham Differences and Similarities. 3) Ekadhikina Purvena By one more than the previous one. 4) Ekanyunena Purvena By one less than the previous one. 5) Gunakasamuchyah The factors of the sum is equal to the sum of the factors. 6) Gunitasamuchyah The product of the sum is equal to the sum of product. 7) Nikhilam Navatashcaramam Dashatah All from 9 and the last from 10. 8) Paraavartya Yojayet Transpose and adjust. 9) Puranapuranabyham By the completion or Non completion. 10) Sankalana vyavakalanabhyam By addition and by subtraction. 11) Shesanyankena Charamena The remainders by the last digit. 12) Shunyam Saamyasamuccaye When the sum is the same that sum is zero. 13) Sopaantyadvayamantyam The ultimate and twice the penultimate. 14) Urdhva Tiryagbyham Vertically and crosswise. 15)Vyashtisamanstih Part and Whole. 16) Yaavadunam Whatever the extent of its deficiency. This is a very interesting field and presents some effective algorithms which can be applied to various branches of engineering such as computing and digital signal processing. This paper presents simple digital multiplier architecture [6] based on the ancient Vedic mathematics Sutra (formula) called Urdhva Tiryakbhyam INTERNATIONAL JOURNAL OF SCIENCE, ENGINEERING AND TECHNOLOGY

3 (Vertically and Cross wise) Sutra in ripple carry adder is used. In this paper we conclude that Vedic multiplier with pipe line techniques is faster than the multiplier without pipe line. 2. URDHVA TIRYAKBHYAM SUTRA Urdhva Tiryakbhyam (Vertical & Crosswise) algorithm can be generalized for n x n bit number. This Multiplier has the advantage that has the number of bits increases, gate delay and area increases very slowly as compared to other multipliers. Therefore it is time, space and power efficient. It is demonstrated that this architecture is quite efficient in terms of silicon area/speed [2]. Since in this multiplier the partial products and their sums are calculated in parallel, the multiplier is independent of the clock frequency of the processor. Therefore the multiplier will require the same amount of time to calculate the product and hence is independent of the clock frequency. By adopting the Vedic multiplier, structure. Due to its regular structure, it can be easily layout in microprocessors and designers can easily circumvent this power of multiplier. It can easily be increased by increasing the input and output data bus widths since it has a quite a regular problems to avoid catastrophic device failures. The net advantage is that it reduces the need of microprocessors to operate at increasingly high clock frequencies. While at higher clock frequency generally results in increased processing power, its disadvantage is that it also increases power dissipation which results in higher device operating temperatures. 2.1 SPEED Vedic multiplier is faster than array multiplier and Booth multiplier. As the number of bits increases from 8x8 bits to 16x16 bits, the timing delay is greatly reduced for Vedic multiplier as compared to other multipliers. Vedic multiplier has the greatest advantage as compared to other multipliers over gate delays and regularity of structures.[2] 2.2 MULTIPLICATION PROCESS OF 4X4 VEDIC MULTIPLIER Figure 1: Line diagram of two 4 bit numbers INTERNATIONAL JOURNAL OF SCIENCE, ENGINEERING AND TECHNOLOGY

4 Algorithm for 4 x 4 bit Vedic multiplier Using Urdhva Tiryakbhyam (Vertically and crosswise) for two Binary numbers [3] Parallel Computation Methodology 1. CP X0 = X0 * Y0 = A Y0 2. CP X1 X0 = X1 * Y0+X0 * Y1 = B Y1 Y0 3. BLOCK IMPLEMENTATION OF 4 4 VEDIC MULTIPLIER The architecture of 4x4 Vedic multiplier using Urdhva Tiryakbhyam Sutra is shown in Fig.1. The 4x4 Vedic multiplier architecture is implemented using four 2x2 Vedic multiplier modules, three 4 bit ripple carry adder and one 15 bit register. The first step in the design of 4 4 block will be grouping the 2 bit of each 4 bit input. These pair terms will form vertical and crosswise product terms. Each input bit pair is handled by a separate 2 2 Vedic the schematic of a 4 4 block designed using 2 2 blocks. The partial products represent the Urdhva vertical and cross product terms.[10] 3. CP X2 X1 X0 = X2 * Y0 +X0 * Y2 +X1 * Y1 = C Y2 Y1 Y0 4.CP X3X2X1X0=X3*Y0+X0*Y3+X2*Y1+X1*Y2= D Y3Y2Y1Y0 5.CP X3 X2 X1 = X3 * Y1+X1 * Y3+X2 * Y2 = E Y3 Y2 Y1 6.CP X3 X2 = X3 * Y2+X2 * Y3 = F Y3 Y2 7 CP X3 = X3 * Y3 = G Y3 Figure 2: Block Diagram of 4 bit Urdhva multiplier with Ripple Carry Adder INTERNATIONAL JOURNAL OF SCIENCE, ENGINEERING AND TECHNOLOGY

5 4. IMPLEMENTATION OF 4 4 MULTIPLIER In this work, 4x4 bit Vedic multiplier is designed in VHDL (Very High Speed Integrated Circuits Hardware Description Language). Logic synthesis and simulation was done using EDA (Electronic Design Automation) tool in XilinxISE9.2e Project Navigator and ISE simulator integrated in the Xilinx package. The performance of circuit is evaluated on the Xilinx family Spartan3, device XC3S50, package pq208 and speed grade 5. The RTL schematic of 4x4 bit Vedic multiplier is shown in Fig. 3 while the simulation results obtained are shown in Fig. 5 for verification. Figure 4: Technology view of 4 bit Vedic multiplier Figure 5: Simulation Results of 4 bit multiplier 5. RESULTS TABLE 1: Comparison of multipliers in terms of delay Vedic Multiplier techniques Delay(ns) Figure 3: RTL view of 4 bit Urdhva Multiplier Vedic without Multiplier pipeline technics Vedic Multiplier with pipelining technics INTERNATIONAL JOURNAL OF SCIENCE, ENGINEERING AND TECHNOLOGY

6 6. CONCLUSIONS The conclusions of this research I have design High Speed and low Delay ripple carry Adder. In this research I used XILINX 9.2e design suit software. In this paper the important characteristic of Vedic multiplier has been discussed. The time delay of Vedic multiplier reduces using pipelining techniques. In this work we divided complete multiplier circuit into two parts, so its total time delay divided in two parts. 7. FUTURE WORK ENHANCEMENTS In future, we can optimize power for this work and we can divide the multiplier in 3 section. Using the concept of pipeline, we can design the high speed multiplier having large number of bits included in the multiplication. We can also use the other adder architecture having less carry propagation delay as compared to ripple carry adder. ACKNOWLEDGMENT I would like to express my sincere gratitude to my project guide Mr. Himanshu Joshi for giving me the opportunity to work on this topic. It would never be possible for us to take this project to this level without his innovative ideas and his relentless support and encouragement. Special thanks to my family for their moral support and kindness. Sincere thanks to all my friends. REFERENCES [1] Gaurav Sharma Delay Comparison of 4 by 4 Vedic Multiplier based on Different Adder Architectures using VHDL, ISSN: , Jaipur June [2] G. Vaithiyanathan, K. Venkatesan, S. Sivaramakrishnan, S. Siva and S. Jayakumar Simulation and Implementation of Vedic Multiplier Using VHDL Code, ISSN: , January 2013 [3] Implementation of Vedic Multiplier for Digital Signal Processing, International Conference on VLSI, Communication & Instrumentation (ICVCI) 2011, Proceedings published by International Journal of Computer Applications (IJCA). [4] Swami Bharati Krishna Tirtha, Vedic Mathematics, Delhi: Motilal Banarsidass Publishers, [5] D. Goldberg, Computer Arithmetic, in Computer Architecture: A INTERNATIONAL JOURNAL OF SCIENCE, ENGINEERING AND TECHNOLOGY

7 Quantitative Approach, J.L. Hennessy and D.A. Patterson ed., pp. A1 A66, San Mateo, CA: Morgan Kaufmann, [6] A. D. Booth, A Signed Binary Multiplication Technique, Qrt. J. Mech. App. Math.,, vol. 4, pp , 1951 [7] A.P. Nicholas, K.R Williams, J. Pickles, Application of Urdhava Sutra, Spiritual Study Group, Roorkee (India),1984. [8] Ming Chen Wen, Sying Jyan Wang, and Yen Nan Lin,.Low Power Parallel Multiplier with Column Bypassing., Electronics letters, 10,12 May 2005 Volume 41, Issue Page(s): [9] Harpreet Singh Dhillon and Abhijit Mitra, A Reduced Bit Multiplication Algorithm for Digital Arithmetic s, International Journal of Computational and Mathematical Sciences 2;2 Spring [10] Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, 2nd Edition. McGraw Hill Publishing Companies. INTERNATIONAL JOURNAL OF SCIENCE, ENGINEERING AND TECHNOLOGY