ECE 538 VLSI System Testing Krish Chakrabarty System-on-Chip (SOC) Testing ECE 538 Krish Chakrabarty 1 Outline Motivation for modular testing of SOCs Wrapper design IEEE 1500 Standard Optimization Test access mechanism design and optimization Test scheduling Exploiting port scalability to test embedded cores at multiple data rates Virtual TAMs Matching ATE data rates to scan frequencies of embedded cores Conclusions ECE 538 Krish Chakrabarty 2 1
Motivation System-on-chip (SOC) integrated circuits based on embedded intellectual property (IP) cores are now commonplace SOCs include processors, memories, peripheral devices, IP cores, analog cores Low cost, fast time-to-market, high performance, low power Manufacturing test needed to detect manufacturing defects Manufacturing! cost! Test cost! ECE 538 Krish Chakrabarty 3 System-on-Chip (SOC) Test access is limited Test sets must be transported to embedded logic ECE 538 Krish Chakrabarty 4 2
0 Shorten production cycles, and increasing complexity of modern electronic systems has forced designers to employ reuse based designs approaches. 0 System-on-Chip (SOC) is an example of such reuse based design approach where pre-designed, pre-verified cores are integrated into a system. SOC CPU2 RAM RAM T DSP Tests T I/O DSP CPU1 I/O T CPU1 T CPU2 ECE 538 Krish Chakrabarty 5 IC design and test development Core provider Core design and test development IC provider IC manufacturing IC testing System integrator SOB design and test development SOB manufacturing System integrator SOC design and test development SOC manufacturing SOB testing SOC testing ECE 538 Krish Chakrabarty 6 3
0 Test access mechanism (TAM) 0 An ATE is used to transport the test stimuli to the SOC. The produced responses are transported back to the ATE where they are compared with the expected responses. 0 Memory cores are usually tested using a built-in self-test Test responses Test stimuli CPU2 RAM RAM Expected test responses TAM ATE DSP CPU1 SOC I/O ATE ECE 538 Krish Chakrabarty 7 Modular Testing Test embedded cores using patterns provided by core vendor (test reuse) Test access mechanisms (TAMs) needed for test data transport: TAMs impact test time and test cost Test wrappers translate test data supplied by TAMs TAM optimization and test scheduling are critical ITRS 05: Test data volume and testing time in 2010 will 30X that for today s chips Automatic Test! Equipment (ATE)! SOC Embedded core Embedded core TAM Embedded core Wrapper TAM ECE 538 Krish Chakrabarty 8 4
Test Access Problem Plug-and-Play" 110011010" 010010100" 101000100" 101010000" 110011010" 010010100" 101000100" 101010000" 110011010" 010010100" 101000100" 101010000" 110011010" 010010100" 101000100" 101010000" Tester" 110011010" 010010100" 101000100" 101010000" 110011010" 010010100" 101000100" 101010000" 1. How to isolate cores?" 2. How to get patterns to cores?" ECE 538 Krish Chakrabarty 9 Test Scheduling Test scheduling determines sequence of core tests on the TAMs Avoid test resource conflicts Minimize testing time Ineffective scheduling can increase tester data volume: Idle bits Idle bits" Schedule" Core 1! Core 2" Core 4" Time" Core 5! ECE 538 Krish Chakrabarty 10 5
Test Planning Optimizing test access to cores and scheduling test hardware Test hardware planning! Test software planning! Core import! Core integration! Test wrapper! & TAM design! Top-level DFT! Test control blocks! IEEE 1149.1! Core test import! Top-level ATPG! Glue logic, soft cores! Test wrappers! Test scheduling! Test assembly! ECE 538 Krish Chakrabarty 11 IEEE 1500 Core Test Standard Goals Define test interface between core and SOC Core isolation Plug-and-play protocols Scope Standardize core isolation protocols and test modes TAM design Type of test to be applied Test scheduling ECE 538 Krish Chakrabarty 12 6
IEEE 1500 Wrapper Wrapper Modes: (1) Normal; (2) Serial Test; (3) 1-N Test; (4) Bypass; (5) Isolation; (6) Extest Marinissen et al., On IEEE P1500's Standard for Embedded Core Test, Journal of Electronic Testing: Theory and Applications, vol. 18, Aug 2002 ECE 538 Krish Chakrabarty 13 Wrapper Boundary Cells ECE 538 Krish Chakrabarty 14 7
Wrapper Usage ECE 538 Krish Chakrabarty 15 Wrapped Embedded Cores ECE 538 Krish Chakrabarty 16 8
Wrapper Operation Modes (I) Normal Mode Serial Bypass Mode ECE 538 Krish Chakrabarty 17 Wrapper Operation Modes (II) Serial Internal Test Mode Serial External Test Mode ECE 538 Krish Chakrabarty 18 9
Wrapper Operation Modes (III) Parallel Internal Test Mode Parallel External ECE 538 Krish Chakrabarty 19 Test Wrapper Optimization Priority 1: Balanced Wrapper Scan Chains Core" Core" 4 FF! 8 FF! Wrapper! 4 FF! 8 FF! Wrapper! Unbalanced! Balanced! Minimize length of longest wrapper scan in/out chain ECE 538 Krish Chakrabarty 20 10
Reducing TAM Width Priority 2: Minimize wrapper scan chains created Scan chain 32 FF! I" I" 8 FF! O" I" 8 FF! O" 4 Wrapper scan chains! I" 8 FF! Scan chain 32 FF! 2 Wrapper scan chains! I" I" I" I" 8 FF! 8 FF! 8 FF! O" O" ECE 538 Krish Chakrabarty 21 Longest wrapper scan chain" Two-Priority Wrapper Design Algorithm TAM width" 1. Minimize length of longest wrapper scan in/out chain 2. Minimize number of wrapper scan chains Design_wrapper algorithm uses the BFD heuristic for Bin Design ECE 538 Krish Chakrabarty 22 11
Test Access Mechanisms Types of TAMs Multiplexed access [Immaneni, ITC 90] Reuse system bus [Harrod, ITC 99] Transparent paths [Ghosh, DAC 98] Isolation rings [Whetsel, ITC 97] Test Bus [Varma, ITC 98] Test Rail [Marinissen, ITC 98] C1" C2" C3" Multi-! plexed! C1" C2" C3" Daisy-! chain! C1" C2" C3" Distri-! bution! ECE 538 Krish Chakrabarty 23 1. Partial isolation rings! 2. Multiplexing! TAM Design Core A! Core B! ECE 538 Krish Chakrabarty 24 12
TAM Design 3. Core Transparency! Core A! Core B! ECE 538 Krish Chakrabarty 25 Test Bus Architecture Architecture Schedule: Serial A B C D E F Combination of multiplexing and distribution Supports only serial schedule Core-external testing is cumbersome or impossible ECE 538 Krish Chakrabarty 26 13
TestRail Architecture Combination of Daisychain and Distribution architectures Cores connected to a TestRail can be tested simultaneously as well as sequentially Multiple wrappers can be activated simultaneously for Extest TestRails can be either fixed-width or flexible-width Fixed-width TestRails Flexible-width TestRails C1" C2" C3" C1" C2" C3" w 1 " w 2 " C1" C2" W" C1" C2" ECE 538 Krish Chakrabarty 27 Step-by-Step Approach to Wrapper/TAM Co-optimization 1. P W : Wrapper design 2. P AW : Core assignment + P W 3. P PAW : TAM width partitioning + P AW 4. P NPAW : Number of TAMs + P PAW W 3 " W 2 " W 1 " TAMs! IP" IP" IP" Wrapper! Wrapper! Wrapper! ECE 538 Krish Chakrabarty 28 14
Mathematical Programming Model for TAM Partitioning Variable x ij = 1, if core i assigned to TAM j Testing time of core i on TAM width w j = T i (w j ) Testing time on TAM j = Σ i T i (w j ) x ij Objective: Minimize T = max j Σ i T i (w j ) x ij Constraints 1. Σ i x ij = 1, every core connected to exactly one TAM 2. Σ i w j = W, total TAM width is W 3. w j w max, maximum width of any TAM is w max ECE 538 Krish Chakrabarty 29 TAM Design and Test Scheduling Given the test set parameters for the cores and the total TAM width W Assign a part of W to each core, design a wrapper for each core, and determine the test schedule, Such that W is not exceeded at any time and Testing time is minimized ECE 538 Krish Chakrabarty 30 15
Architectures Determine Schedules Slide provided by Erik Jan Marinissen, Philips Research Labs ECE 538 Krish Chakrabarty 31 Rectangle Model for Test Buses Three test buses Each core on same bus gets equal, fixed TAM width Bus 1! Core 1! Core 3! Core 9! Core 8! Bus 2! Core 2! Core 4! Bus 3! Core 5! Core 6! Core 7! ECE 538 Krish Chakrabarty 32 16
Rectangle Representation Testing time T i (w j ) for Core i and TAM width j Rectangle R ij Set of rectangles R i for each core Collection of rectangles R for SOC Set R i of rectangles for Core i T i (w j ) Collection R w j ECE 538 Krish Chakrabarty 33 Rectangle Packing Problem Given collection R of rectangle sets for the SOC cores, Select one rectangle R ij for each Core i Pack the selected rectangles into a bin of fixed height, Such that bin width is minimized Collection R Height Core 1 Core 2 Width Core 3 ECE 538 Krish Chakrabarty 34 17
Packed Bin = TAM Design + Test Schedule Rectangle area = tester " memory for core test" Empty space = wasted " tester memory" Bin height = " total TAM width" Core 2" Core 1" Core 8" Core 4" Core 3" Core 5" Core 7" Core 6" Bin width = SOC testing time" ECE 538 Krish Chakrabarty 35 Preferred TAM Widths Testing time Preferred TAM width TAM width Pareto-optimal width Only Pareto-optimal TAM widths are considered Procedure: Tests are scheduled at current time in decreasing order of preferred TAM width until no TAM width remains ECE 538 Krish Chakrabarty 36 18
Non-Preferred Rectangles: Fill Idle Time Next_time" Core 3! Core 3! Total TAM width" Core 2-P! Core 1-P! Core 2-P! Core 1-P! Core 2! Core 3-P! Core 1! Current_time" ECE 538 Krish Chakrabarty 37 Increasing Current TAM Widths Total TAM width" Core 4-P" W_available" Core 1-P" Core 3" Core 3-P" Core 2-P" Current_time" Current_time" Current_time" Modify current rectangle that will benefit the most from an increase in TAM width If idle time is inevitable, advance Current_time and repeat procedure from the start ECE 538 Krish Chakrabarty 38 19
Preemption Core 2" Core 8" Core 4" Core 8" Core 7" Core 5" Core 1" Core 3" Core 6" 1. Break up a long test to fill in idle time gaps in schedule" 2. Break up a test to avoid a potential conflict" ECE 538 Krish Chakrabarty 39 Power Constraints 1. Excessive test concurrency can burn the SOC" 2. Cores that do not operate together may be " tested together " Power consumption" Core 2" Core 1" Core 8" Core 8" Core 5" Core 4" Core 7" Core 3" Core 6" ECE 538 Krish Chakrabarty 40 20
Precedence Relationships 1. Memory BIST before external test" 2. Tests that detect more faults applied first" 3. Shorter tests first" Example: Core 4 must complete before Core 6 begins" Core 2" Core 8" Core 4" Core 5" Core 7" Core 1" Core 3" Core 6" ECE 538 Krish Chakrabarty 41 ITC 2002 SOC Test Benchmarks Initiative led by Philips Research Labs and Duke University http://www.hitech-projects.com/itc02socbenchm/ Freely downloadable through Internet Currently 12 SOC benchmarks 5 from academic contributors 7 from industrial contributors Awareness, Interest, Usage E-mail reflector with 43 subscribers Awareness panel session at TECS 02: How Useful Are The ITC 02 SOC Test Benchmarks? Panel report in IEEE Design & Test of Computers 10/2002 Special session at ITC 02 + papers in other sessions Numerous papers using the benchmarks in journals and conferences Extensions added by others (layout data, power consumption data, functional interconnects., etc.) ECE 538 Krish Chakrabarty 42 21
Current-Generation ATEs Port scalability features Digital speeds of up to 2.5 Gbps Application flexibility Every port of a tester, consisting of multiple channels, can configured at a desired data rate ECE 538 Krish Chakrabarty 43 Virtual TAMs Embedded core test frequency is limited by scan frequency Scan frequencies are low to meet power, routing, and clock skew constraints Virtual TAMs allow use of high frequency ATE pins How can we match fast ATE data rates to slow scan frequencies? ECE 538 Krish Chakrabarty 44 22
Bandwidth Matching ATE" High frequency Bandwidth" ATE lines Matching" Low frequency ATE lines 10 low frequency" lines to the cores" ATE pins : W ATE = 4" ATE frequency factor : n = 4" High frequency pins U = 2" Virtual TAM" ECE 538 Krish Chakrabarty 45 Implementation of Bandwidth Matching Low-speed TAM SOC ATE U Serial-In/ Parallelout Registers U U U U Embedded core U U U U Parallel-In/ Serialout Registers High-speed TAM (n = 4) W ATE -U Low-speed TAM ECE 538 Krish Chakrabarty 46 23
Selection of U and n Testing of SOC is often dominated by the testing time of bottleneck cores Testing time of SOCs containing bottleneck cores does not decrease for TAM widths greater than W* The lower bound on test time in such SOCs is T* corresponding to TAM width W* ECE 538 Krish Chakrabarty 47 SOCs with Bottleneck Cores SOC W* (bits) T* (clock cycles) u226 48 5333 d281 48 3926 g1023 40 14794 p34392 36 544579 t512505 36 5228420 h953 16 119357 f2126 16 335334 q12710 16 2222349 ECE 538 Krish Chakrabarty 48 24
Relationship of U, n and W* U and n should be chosen such that total virtual TAM width W does not exceed W* ECE 538 Krish Chakrabarty 49 Variation of U with n ECE 538 Krish Chakrabarty 50 25
U vs n for ITC 02 Benchmarks SOC p34392! W*=36" SOC h953! W*=16" SOC d281! SOC g1023! W*=48" W*=40" ECE 538 Krish Chakrabarty 51 Multiple-Speed TAM Architectures Exploit port-scalability of ATEs Facilitate efficient use of high data-rate tester channels Unlike virtual TAMs, avoid on-chip hardware overhead Reduce testing time of bottleneck cores fast" ATE! slow" SOC! ECE 538 Krish Chakrabarty 52 26
Problem Formulation Dual-speed optimization problem Given:! f.r ATE! V! r SOC! Embedded! cores! W-V! Determine the wrapper design, TAM width and test data rate for each! core, and the SOC test schedule such that:! the total number of TAM wires utilized at any moment does not exceed W the number of TAM wires driven at the high data rate does not exceed V the SOC testing time is minimized ECE 538 Krish Chakrabarty 53 Selection of Data Rate for a Core Testing time" r fast" Testing time" f.r TAM width" Core 5 in SOC p93791 TAM width" f =2 V=10 T = 14026.9μs f =1 W-V=23 T = 11398.9μs ECE 538 Krish Chakrabarty 54 27
Matching Core Scan Frequencies to ATE Data Rates Core A! Core B! Core C! Core D! Baseline! Case 1! TAM width! f = 40MHz! A! B! C! D! f = 80MHz! T = 456 μs! w 1 = 8 f 1 = 40MHz! w 2 = 2, f 2 = 40MHz! Test time! ECE 538 Krish Chakrabarty 55 Matching Core Scan Frequencies to ATE Data Rates Core A! Core B! Core C! Core D! f = 40MHz! f = 80MHz! Baseline! Case 2! TAM width! T = 275 μs! A! C! D! B! w 1 = 8 f 1 = 80MHz! w 1 = 2, f 2 = 40MHz! Test time! ECE 538 Krish Chakrabarty 56 28
Matching Core Scan Frequencies to ATE Data Rates Core A! Core B! Core C! Core D! f = 40MHz! f = 80MHz! TAM width! A! B! C! D! w 1 = 5 f 1 = 80MHz! f 2 = 40MHz! w 1 = 5 T = 246 μs! Test time! ECE 538 Krish Chakrabarty 57 Given Problem Statement Test data parameters for N embedded cores Maximum scan frequency f i * for each core i SOC-level TAM width W Determine The number of TAM partitions B Width w j and scan frequency f j of each TAM partition j Assignment of cores to TAM partitions Such that TAM frequency does not exceed the maximum scan frequency of any core assigned to that TAM partition The overall test time is minimized The sum of the widths of all the TAM partitions does not exceed W ECE 538 Krish Chakrabarty 58 29
Solution Techniques Lower bound on test time based on geometric arguments (rectangle packing) Integer linear programming Exact optimization method, limited to small problem instances Fast heuristic method Scalable, close to optimal results ECE 538 Krish Chakrabarty 59 Comparison with Baseline (X 100) p22810! (5 frequencies: 10 to 50 MHz)! 300 Test time (μs)! 250 200 150 100 50 37%! LB baseline proposed 0 16 24 32 40 48 56 64 TAM Width ECE 538 Krish Chakrabarty 60 30
(X 100) 12 Test time (μs)! 10 8 6 4 2 0 Comparison with Exact Method and Baseline d695! (2 frequencies: 40 MHz and 50 MHz)! 16 24 32 40 48 56 64 ILP TAM Width baseline proposed ECE 538 Krish Chakrabarty 61 Conclusions Test reuse and test time minimization are necessary to reduce test cost for SOCs Wrapper/TAM optimization and test scheduling can reduce test time for core-based SOCs Virtual TAMs offer several advantages for SOC testing On-chip TAM wires are not limited by the number of available pins on the SOC Better utilization of high-speed ATE channels reduces testing times TAM architectures can be designed to match portscalable ATE channels to different scan frequencies of embedded cores ECE 538 Krish Chakrabarty 62 31