Altera 5SGXEA7K2F40C2ES Stratix V TSMC 28 nm HP Gate Last HKMG CMOS Process Process Review FEOL Analysis 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7 Canada Tel: 613-829-0414 www.chipworks.com
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Process Review FEOL Analysis Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profiles 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Package and Die 2.2 Die Features 3 Process Analysis 3.1 Analysis Locations 3.2 General Device Structure 3.3 Flip-Chip Solder Pad 3.4 Dielectrics 3.5 Isolation 3.6 Metallization 3.7 Vias and Contacts 3.8 Transistor Overview 3.9 NMOS Transistors 3.10 PMOS Transistors 3.11 Peripheral I/O Transistors 3.12 Wells and Substrate 4 Critical Dimensions 4.1 Horizontal Dimensions 4.2 Vertical Dimensions 5 References 6 Statement of Measurement Uncertainty and Scope Variation About Chipworks
Overview 1-1 1 Overview 1.1 List of Figures 2 Device Overview 2.1.1 Stratix V FPGA Package Top 2.1.2 Stratix V FPGA Package Bottom 2.1.3 Stratix V FPGA Package Edge 2.1.4 Stratix V FPGA Package X-Ray Plan View 2.1.5 5SGXEA7K2F40C2ES Die Photograph 2.1.6 Die Markings 2.2.1 Die Corner A 2.2.2 Die Corner B 2.2.3 Die Corner C 2.2.4 Die Corner D 2.2.5 Minimum Pitch Flip-Chip Pads 2.2.6 Flip-Chip Pad 2.2.7 Large Inductors 2.2.8 Small Inductors 2.2.9 Logic NAND gate 3 Process Analysis 3.1.1 Die Analysis Locations 3.2.1 General Structure of 5SGXEA7K2F40C2ES 3.2.2 Die Edge 3.3.1 Flip-Chip Solder Bump Pad 3.3.2 Flip-Chip Solder Bump Pad Edge 3.4.1 Passivation SEM 3.4.2 ILD 11, ILD 10, and ILD 9 SEM 3.4.3 ILD 8 TEM 3.4.4 ILD 7 SEM 3.4.5 ILD 6 TEM 3.4.6 ILD 5 TEM 3.4.7 ILD 4 TEM 3.4.8 ILD 3 TEM 3.4.9 ILD 2 TEM 3.4.10 ILD 1 TEM 3.4.11 PMD TEM 3.5.1 STI TEM 3.6.1 Minimum Pitch Metal 12 SEM 3.6.2 Minimum Pitch Metal 11 SEM 3.6.3 Metal 11 Liner TEM 3.6.4 Minimum Pitch Metal 10 and Metal 8 SEM 3.6.5 Minimum Pitch Metal 9 TEM 3.6.6 Metal 9 Liner TEM 3.6.7 Minimum Pitch Metal 7 SEM 3.6.8 Minimum Pitch Metal 6 TEM
Overview 1-2 3.6.9 Minimum Pitch Metal 4 TEM 3.6.10 Minimum Pitch Metal 3 TEM 3.6.11 Minimum Pitch Metal 2 TEM 3.6.12 Minimum Pitch Metal 1 TEM 3.6.13 Metal 1 Liner TEM 3.7.1 Minimum Pitch Via 11 SEM 3.7.2 Minimum Pitch Via 10s, 9s, and 8s SEM 3.7.3 Minimum Pitch Via 4 TEM 3.7.4 Minimum Pitch Via 3 TEM 3.7.5 Via 1 TEM 3.7.6 Contact to NMOS Source/Drain TEM 3.7.7 Bottom of Contact to PMOS Source/Drain TEM 3.7.8 Contact to Gate Metal TEM 3.8.1 Minimum NMOS Contacted Gate Pitch TEM 3.8.2 Minimum PMOS Contacted Gate Pitch TEM 3.8.3 Transistor Sidewall Spacer TEM 3.9.1 NMOS Logic Transistor Overview TEM 3.9.2 NMOS Transistor Gate Wrap TEM 3.9.3 NMOS Gate Metals and Dielectrics TEM 3.9.4 NMOS Gate Dielectric and Work Function Metal 3.10.1 PMOS Logic Transistor Gate Overview TEM 3.10.2 PMOS Transistor Gate Wrap TEM 3.10.3 PMOS Gate Metals and Dielectrics TEM 3.10.4 PMOS Gate Dielectric and Work Function Metal TEM 3.10.5 N/PMOS Gate Transition Cross-Sectional TEM 3.10.6 Isolated PMOS Transistor TEM 3.10.7 Group of Three PMOS Transistors TEM 3.10.8 Detail of Group of Three PMOS Transistors TEM 3.10.9 Group of Eleven PMOS Transistors TEM 3.10.10 SiGe Tub TEM 3.10.11 Germanium Profile of SiGe Tub TEM-EDS 3.11.1 Peripheral NMOS Transistor TEM 3.11.2 Peripheral NMOS Transistor Edge TEM 3.11.3 Peripheral NMOS Gate Dielectric and Work Function Metal TEM 3.12.1 N-Type Dopant SIMS 3.12.2 P-Type Dopant SIMS 3.12.3 Logic Region SCM
Overview 1-3 1.2 List of Tables 1 Overview 1.4.1 Device Identification 1.5.1 Device Summary 1.6.1 Process Summary 2 Device Overview 2.2.1 Die and Bond Pad Sizes 3 Process Analysis 3.4.1 Dielectric Thicknesses 3.6.1 Metallization Vertical Dimensions 3.6.2 Metallization Horizontal Dimensions 3.7.1 Via and Contact Dimensions 3.8.1 Transistor Horizontal Dimensions 3.8.2 Transistor and Silicide Vertical Dimensions 3.12.1 Die Thickness and Well Depths 4 Critical Dimensions 4.1.1 Die and Bond Pads 4.1.2 Metallization Horizontal Dimensions 4.1.3 Via and Contact Dimensions 4.1.4 Transistor Horizontal Dimensions 4.2.1 Dielectric Vertical Dimensions 4.2.2 Metallization Vertical Dimensions 4.2.3 Transistor and Silicide Vertical Dimensions 4.2.4 Die and Well Vertical Dimensions
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