Arrays of digital Silicon Photomultipliers Intrinsic performance and Application to Scintillator Readout Carsten Degenhardt, Ben Zwaans, Thomas Frach, Rik de Gruyter Philips Digital Photon Counting NSS-MIC Conference, November 2 nd, 2010
How to replace old-fashioned PMTs? Take the digital SiPM 1 pixel Increase integration 2 x 2 pixel on one chip Assemble arrays 8 x 8 pixels on one PCB 2
Digital Photon Counting The Concept Intrinsically, the SiPM is a digital device: a single cell breaks down or not analog SiPM digital SiPM (dsipm) TDC and photon counter Digital Cells www.hamamatsu.com Summing all cell outputs leads to an analog output signal and limited performance Digital output of Number of photons Time-stamp Integrated readout electronics is the key element to superior detector performance 3
Digital silicon photomultiplier technology The principle 4
Digital silicon photomultiplier technology The principle 5
Digital silicon photomultiplier technology The principle 6
Digital silicon photomultiplier technology The principle 7
The digital SiPM array Features 8 x 8 digital SiPMs (on 4 x 4 chips) 6400 diodes per pixel ~ 11 cm 2 4-side tiling possible Inputs 1.8 V, 3.3 V, 30 V JTAG (test and configuration) 200 MHz reference clock External trigger input Outputs 100 MHz serial data (photon count, timestamp) Event detect trigger 8
Measurement setup (1) dsipm array electronic trigger dsipm array Clock, Config, Data FPGA board Coincidence detection FPGA board Clock, Config, Data USB connection PC 9
Counts (arb. u.) Intrinsic timing performance 70000 60000 (44 ± 1) ps FWHM 50000 40000 30000 20000 10000 0-100 -80-60 -40-20 0 20 40 60 80 100 Timestamp difference (ps) Timing jitter over full delay range: 44 ps FWHM 10
Measurement setup (2) dsipm array psec-laser dsipm array Clock, Config, Data FPGA board Coincidence detection FPGA board Clock, Config, Data USB connection PC 11
Counts Timing performance 30000 20000 10000 0-120 -80-40 0 40 80 120 Timestamp difference (ps) Timing jitter over full delay range: 59 ps FWHM 12
Measurement setup (3) dsipm array LYSO scintillator array dsipm array Clock, Config, Data FPGA board 22 Na Coincidence detection FPGA board Clock, Config, Data USB connection PC 13
Scintillator readout Floodmap LYSO array, 8 x 8 crystals, 4 mm x 4 mm pitch, 22 mm length 14
Counts Scintillator readout Energy resolution 1000 800 Data: selecthist1_b Model: GaussFWHM Weighting: y No weighting 600 400 12.1 % FWHM Chi^2/DoF = 257.69355 R^2 = 0.99701 y0 7.9796 ±2.88312 A 842.21326 ±6.96861 w 120.76367 ±1.23718 xc 992.78691 ±0.46404 200 0 LYSO array, 8 x 8 crystals, 4 mm x 4 mm pitch, 22 mm length 0 511 Energy (kev) Saturation was corrected 15
Pixels Scintillator readout Energy resolution LYSO array, 8 x 8 crystals, 4 mm x 4 mm pitch, 22 mm length Saturation was corrected 10 5 0 10,5 11,0 11,5 12,0 12,5 13,0 13,5 14,0 Energy resolution (%) 16
Counts Scintillator readout Timing resolution 1500 LYSO array, 8 x 8 crystals, 4 mm x 4 mm pitch, 22 mm length Data: TDCsum_B Model: GaussFWHM Weighting: y No weighting 1000 328 ps FWHM Chi^2/DoF = 651.41009 R^2 = 0.99071 Summed timing of all 8 x 8 crystals y0 6.55998 ±2.8013 A 1202.17597 ±14.01351 w 0.31772 ±0.00409 xc 0.01529 ±0.00172 500 Timing mainly limited by photon statistics (CRT with 3x3x5 mm 3 LYSO: 153 ps) 0-1 0 1 Timestamp difference (ns) 17
Counts Scintillator readout Timing resolution Two sources 8.3 cm apart Dt = 570 ps 8.6 cm 1800 1200 600 0-1,5-1,0-0,5 0,0 0,5 1,0 1,5 Timestamp difference (ns) 18
Small crystal readout LYSO array, 30 x 30 crystals, 1 mm x 1 mm pitch, 10 mm length Log scale Data analysis by P. Düppenbecker, see talk M03-4 19
Summary Arrays of 8 x 8 digital SiPMs operational Intrinsic timing resolution: 59 ps FWHM Performance with LYSO scintillator arrays ~12 % FWHM energy resolution 328 ps FWHM coincidence timing resolution Mainly limited by number of detected photons 20
Next Steps Optimize the detection (crystal coupling, anti-reflection coating, fill-factor, ) Build detector modules Work together with partners to explore further applications 21
Talk N58-1 (Thu, Nov 4 th, 8:00am, Ballroom G) T. Frach, The Digital Silicon Photomultiplier Prototype System Architecture and Performance Evaluation Visit us at Booth #105 22