PCB Routing Guidelines for Signal Integrity and Power Integrity

PCB Routing Guidelines for Signal Integrity and Power Integrity Presentation by Chris Heard Orange County chapter meeting November 18, 2015 1

Agenda Insertion Loss 101 PCB Design Guidelines For SI Simulation Examples and Tools Power Integrity Examples www.cshconsulting.net chris.heard100@gmail.com. 2

Insertion Loss 101 3

What is Insertion Loss? Insertion loss is the loss of signal amplitude resulting from the insertion of a device in a transmission line and is expressed in decibels (db) www.cshconsulting.net chris.heard100@gmail.com. 4

Datarate and Fundamental Frequency The 10Gbps Signal Sinusoid Datarate = 10Gbps = 10e9 Time Between Crossings = 1 / 10e9 100pS Period of Sinusoid = 200pS Frequency of Sinusoid = 1 / 200pS = 5e9 200pS The Fundamental Frequency = 5e9 = 5GHz Also called the Nyquist Frequency www.cshconsulting.net chris.heard100@gmail.com. 5

10Gbps Example 1V 0.1V 100pS How much insertion loss does this path have? 20 * log (0.1 / 1.0) = -20dB of Insertion Loss (at 5GHz) www.cshconsulting.net chris.heard100@gmail.com. 6

Voltage vs Material in Volts FR4 Hight Tg Nelco 4000-13 Megtron-6 1.20 1.00 0.80 Volts 0.60 FR4: 0.1V Meg6: 0.4V (4x better) 0.40 0.20 Nelco 4000-13 Megtron-6 FR4 0.00 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 20.0 22.0 24.0 26.0 28.0 30.0 32.0 34.0 36.0 38.0 40.0 Frequency (GHz) www.cshconsulting.net chris.heard100@gmail.com. 7

Loss vs Frequency Loss vs Material in db FR4 High Tg Nelco 4000-13 Megtron-6 0-5 FR4: -20dB Meg6: -8dB (12dB better) -10-15 Loss (db) -20-25 -30-20.0 db 5.0 GHz Megtron-6-35 -40 FR4 Nelco 4000-13 -45-50 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 20.0 22.0 24.0 26.0 28.0 30.0 32.0 34.0 36.0 38.0 40. Frequency (GHz) www.cshconsulting.net chris.heard100@gmail.com. 8

PCB Design Guidelines For SI 9

Routing Through Antipads Do Not Rout traces by antipads without any overhang. Ensure 3.0mil of Ground plane overhang when routing through Antipads. 3.0mil 10

Joining Antipads: 1 Do not join Antipad Voids together. Separate the via pairs so that the antipad voids do not join. 11

Joining Antipads: 2 IPASS Connector P N P In this case the space between P and N signals is larger than the space to the next pair. This will increase crosstalk between pairs. Arrange pins in a G-S-S- G format. Use the ground pins to achieve isolation between diff pairs. 12

Antipads too Close Antipads too close causing no ground plane for diff pair. Reduced size of antipad allows for adequate ground plane overhang 13

Skew Compensation: 1 This method of increasing length causes crosstalk and impedance issues for any signal over 500MHz Lengthen Trace within the antipad region as shown. Trace can connect to pad at these locations. Keep lengthened trace within the antipad opening. 14

Skew Compensation: 2 At least 50 mil separation to reduce coupling between jogs. 4.35 mil trace to maintain impedance. 8.75 mil space 4.25 mil normal trace width 10 mils 4.35 mil trace to maintain impedance. This is the recommended approach The wider trace widths need to be calculated with a field solver for each application. 15

Transition Vias Without Grounds No Ground Vias for the diff pair. Ground vias added as described in prelayout simulation results. 16

Transition Vias: Proper Design Units mm 0 1 2 3 GND Via GND Via Ground Vias are spaced properly. Antipads and Drill sizes are specified. Antipad Dia 0 40.0mil Finished Dia Drill Dia Pad Dia Antipad Dia Oval Dogbone 8.0mil 9.8mil 20.0mil 40.0mil 40.0mil Diff Port Zo 100 Layer Escape 6 Line Width 6mil EtchBack 0.1mil Line Space 6.70mil Material RogersTheta Dk 3.9 Df 0.01 Layers 8 Thickness 91.7 mil 17

Drill Size Versus Finished Size Pad Stack Drill Diameter shows the Finished Diameter. Fab Drawing attempts to correct the problem by stating what drill size to use Signal Integrity Tools import the Drill Size from the Padstack, making simulation results look better than they actually are. Drill size in PCB Design Padstack should match Drill size desired. It s not OK to allow the PCB Fabricator to pick a drill size. 18

Specify Drill Size for Transition Vias and AC Caps Drill Chart doesn t specify the drill size, but the finished size only Drill size matches actual drill availability. Tolerance allows to be plated shut. Note 12 calls out the drill size. www.cshconsulting.net chris.heard100@gmail.com. 19

Reliefs Under AC Caps Add a relief under AC Capacitors on the adjacent ground plane to increase impedance for 0402 Caps on 1mm pitch Relief can be individual rectangles or a full rectangle encompassing both capacitors. Either way it must be simulated and verified. It is stackup and material dependent! 1 2 Cap Pads 21 x 18 L2 Clearance 25 x 60 20

SMT Pad Transitions No Ground Vias for the diff pair. No clearance under pads. Ground vias added as described in pre-layout simulation results. Clearance under pads on adjacent plane layer only, increase impedance for a better match to 100ohms 21

Thermal Reliefs on Press Fit Connectors Do Not use Thermal Reliefs on Press Fit Connectors. Change Thermal Reliefs to Direct Connections to the plane. 22

Rectangular or Oval Antipads on High Speed Connectors Do Not use simple round antipads on high speed connectors (Example: AirMax) Change to rectangular or oval shape described in pre-layout simulation results. 23

Routing Over Ground Plane Edges Do Not Rout Over and Ground Plane Edge Move the etch away from the ground plane edge or increase the size of the ground plane edge. Diff pair should be >30mil (8H) from edge of plane. H=Distance from Signal Layer to reference plane layer 24

Diff Pairs Not Centered in Routing Channels Diff pairs running over antipad edges Diff pair centered in the channel. 25

Diff Pairs Spaced Too Close 6-9-6 diff pair spaced 10mils apart. Needs 25-30mils of spacing (4H). Diff pairs spaced by 30mils 26

Take Advantage of Unused Ground Planes Move diff pairs up to adjacent channel to avoid the nearby Tx pair and to make use of a better ground reference. Diff pairs moved away from nearby oval antipads to minimize coupling to other BGA signal pads. 27

Diff Pair Spacing on Top and Bottom Layers Microstrip surface pairs are 12mil between P and N. Diff pairs are spaced 16mil apart. This causes lots of crosstalk. 12.0mil 16.0mil They need to be 50-75mil apart! (10H) Move diff pairs to inner layers and use closer spacing between P and N (8mil). Or use 50-75mil spacing between pairs on the surface. 28

Splitting Up Diff Pairs: 1 Avoid separating diff pairs to get around vias. Keep the pair coupled together at all times. 29

Splitting Up Diff Pairs: 2 Avoid separating diff pairs to get around vias. 3-4-3 : 102 ohms 3-21-3: 112 ohms Keep the pair coupled together at all times. Widen the line in areas where the lines pull apart. 30

Serpentine Spacing Serpentines are 13mils apart. Diff pairs are 8.75mils apart. This causes about 0.2% of crosstalk on to itself, which is too high. Increase spacing to 17mils or more (4H) H=Distance from Signal Layer to reference plane layer 31

Haphazard Ground Via Locations Ground Vias are positioned randomly. Ground Vias placed matching pre-layout simulations 32

Floating Ground Islands on Signal Layers Gnd Etch added to signal layer and connected only at the ends with vias. This is an attempt to lower crosstalk. Remove all Ground Islands on signals layers. By the time the island is added, the traces are far enough apart anyway. 33

Routing Over Splits: 1 Traces crossing over a split in the ground plane on an adjacent layer Remove the split in the ground plane or move the traces to a layer that has a continuous plane. 34

Routing Over Splits: 2 DQS DDR3 signal runs down the split in the plane shown in red box. Remove the split in the ground plane or move the traces to a layer that has a continuous plane. 35

Blind Vias: Antipads Too Large. Example 1 DQ signals running over massive voids on Layer 2 due to blind via connections. Alternate the use of standard through holes with Blind Vias. 36

Blind Vias: Antipads Too Large. Example 2 0.8mm ball pitch Large Joined Voids present on L5, 7,9,12,14,16. All traces in this area will couple together. Signals on L6,8,10,11,13, 15 all couple together Alternate the use of standard through holes with Blind Vias. 37

Blind Vias: Out of Control Signal Paths Red and Yellow signal paths are not coupled or consistent. Ground Vias provide no isolation between signal vias throughout the board because they are Blind vias from L1-L3 www.cshconsulting.net chris.heard100@gmail.com. 38

Copper Utilization Traces are routed at minimum spacing with tons of copper available on either side. Use these unused areas Spread Traces out to take advantage of the unused copper and reduce crosstalk in the process 39

Backdrilling at 6Gbps Long stubs under connecting layers cause resonance. Backdrill to multiple depths keeping stubs less than 30mils (at 6Gbps) SIG 2.1 3.35 PLANE 1.3 3.50 SIG 0.65 4.45 PLANE 0.65 3.50 SIG 0.65 4.45 PLANE 0.65 3.50 SIG 0.65 4.45 PLANE 0.65 3.50 PLANE 0.65 2.70 PLANE 0.65 3.00 PLANE 0.65 2.70 PLANE 0.65 3.00 PLANE 0.65 2.70 PLANE 0.65 3.00 PLANE 0.65 4.45 SIG 0.65 3.50 PLANE 0.65 4.45 SIG 0.65 3.50 PLANE 0.65 4.45 SIG 0.65 3.50 PLANE 1.3 3.35 SIG 2.1 Top to L3 with backdrilling Top to L5 with backdrilling Top to L7 with backdrilling Top to L16 with backdrilling Top to L18, no backdrilling Top to L20, no backdrilling 40

Simulation Examples and Tools 41

Channel Modeling - Process and Tools BGA Package BGA Via PCB Via Via Connector Via Etch BGA Package PCB Etch AC Cap PCB Etch Via Connector Via Backplane Channel Models created in Hspice Or ADS S-parameters of connector, footprint, etch Connector Models Provided by Connector Vendor in Touchstone format. PCB Footprints / Via Models Simulated in Ansoft HFSS PCB Etch Models De-Embedded S-parameter Model generated in HFSS www.cshconsulting.net chris.heard100@gmail.com.

Measurement Statistical Eye: 6.25Gbps Measurement vs. Simulation 0.76UI 240mV Simulation (from LinkEye) 0.70UI 162mV www.cshconsulting.net chris.heard100@gmail.com. 43

ADS Schematic: 1 Million Bit-By-Bit Simulation 44

Statistical Eye: 12.5Gbps 1 Million Bit-By-Bit Simulation Amplitude: 336mV Width: 63ps Width: 0.79UI 45

Via Model Example: Return Loss Improvements 46

Via Model: Transition Via As Designed Finished Dia Drill Dia Pad Dia Antipad Dia Oval Dogbone 8.0mil 11.7mil 18.0mil 34.0mil 20.0mil Diff Port Zo 100 Layer Escape 1 and 5 Line Width EtchBack Line Space 3.50mil 0.1mil 8.0mil Material Thickness EM888 Dk 3.5 Df 0.008 Layers 14 61.5 mil 47

Via Model: Transition Via Modified Finished Dia Drill Dia Pad Dia Antipad Dia Oval Dogbone 8.0mil 11.7mil 18.0mil 45.0mil 35.0mil Default Stub Backdrill Dia Backdrill Hole? 20.0mil 20.0mil Yes Diff Port Zo 100 Layer Escape 1 and 5 Line Width EtchBack Line Space 3.50mil 0.1mil 8.0mil Material Thickness EM888 Dk 3.5 Df 0.008 Layers 14 61.5 mil 48

IL, RL and TDR: Transition Via As Designed 0 Differential Insertion and Return Loss: SEB1-TransVia TDR: SEB1-TransVia -5 110-16dB at 5.0GHz. 105-10 Marginal 100 Magnitude (db) -15-20 -25 Goal Ohms 95 90 85 80 75 ohms. -30 75 70-35 -40 0 2 4 6 8 10 12 14 16 18 20 Frequency (GHz) sdd12 sdd11 Simulated Differential TDR 65 0 0.05 0.1 0.15 0.2 0.25 0.3 Time(nS) 49

IL, RL and TDR: Transition Via Modified 0 Differential Insertion and Return Loss: SEB1-TransVia-R1 TDR: SEB1-TransVia-R1-5 110-38dB at 5.0GHz. 105-10 Excellent 100 Magnitude (db) -15-20 Goal Ohms 95 90 85 95 ohms. -25 80-30 75 70-35 -40 0 2 4 6 8 10 12 14 16 18 20 Frequency (GHz) sdd12 sdd11 Simulated Differential TDR 65 0 0.05 0.1 0.15 0.2 0.25 0.3 Time(nS) 50

Via Model: 0.8mm BGA Finished Dia Drill Dia Pad Dia Antipad Dia 6.0mil 9.8mil 18.0mil 26.0mil Diff Port Zo 100 Layer Escape 10 Line Width EtchBack Line Space 3.45mil 0.1mil 4.6mil Material Thickness FR408HR Dk 3.86 Df 0.0147 Layers 14 98.0 mil Max Freq. Adapt Freq. 20 GHz 10 GHz 51

Via Model: 0.8mm BGA-R1 With 32/30 Antipad and 22mil clearance under BGA Pads Finished Dia Drill Dia Pad Dia Antipad Dia Oval Dogbone 6.0mil 9.8mil 18.0mil 32.0mil 30.0mil Diff Port Zo 100 Layer Escape 10 Line Width EtchBack Line Space 3.45mil 0.1mil 31.5mil Material Thickness FR408HR Dk 3.86 Df 0.0147 Layers 14 98.0 mil Max Freq. Adapt Freq. 20 GHz 10 GHz 52

IL, RL and TDR: 0.8mm BGA This is not acceptable performance at 10Gbps 0 Differential Insertion and Return Loss: U26 BGA L10 Out TTM 105 TDR: U26-BGA-L10-Out-TTM -5 100 78.1 to 100.1 ohms -10-15 95 Magnitude (db) -20-25 -13.3dB @ 5.0GHz Ohms 90 85-30 -35 Sdd12 Sdd11 Goal -40 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Frequency (GHz) 80 U26-BGA-L10-Out-TTM 75 0 0.1 0.2 0.3 0.4 Time (ns) 53

IL, RL and TDR: 0.8mm BGA-R1 With 32/30 Antipad and 22mil clearance under BGA Pads This is acceptable. Differential Insertion and Return Loss: U26 BGA L10 Out R1 TTM 0 105 TDR: U26-BGA-L10-Out-R1-TTM -5-10 100 86.5 to 100.4 ohms -15-18.5dB @ 5.0GHz 95 Magnitude (db) -20-25 Ohms 90 85-30 -35 Sdd12 Sdd11 Goal -40 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Frequency (GHz) 80 U26-BGA-L10-Out-R1-TTM 75 0 0.1 0.2 0.3 0.4 Time (ns) 54

Via Model Example: Alternating Layers 55

Via Model: BGA-L14 Layer 14 Layer 14 Rx (Victim) Rx1 Finished Dia Drill Dia Pad Dia Antipad Dia Oval Dogbone 6.0mil 9.8mil 20.0mil 30.0mil 30.0mil Diff Port Zo 95 Layer Escape 14 Line Width EtchBack Line Space 3.90mil 0.1mil 6.0mil Material Layers 16 Thickness N4000-13-SI Dk 3.35 Df 0.011 76.0 mil Max Freq. Adapt Freq. 40 GHz 20 GHz 56

Via Model: BGA-L14-R1 Alternate layer assignments Layer 3 Layer 14 Rx (Victim) Rx1 Finished Dia Drill Dia Pad Dia Antipad Dia Oval Dogbone 6.0mil 9.8mil 20.0mil 30.0mil 30.0mil Default Stub Backdrill Dia Backdrill Hole? 20.0mil 20.0mil Yes Diff Port Zo 95 Layer Escape 3 and 14 Line Width EtchBack Line Space 3.90mil 0.1mil 6.0mil Material Layers 16 Thickness N4000-13-SI Dk 3.35 Df 0.011 76.0 mil Max Freq. Adapt Freq. 40 GHz 20 GHz 57

IL, RL and TDR: BGA L14 Bottom Layer Has Great Return Loss 0 Differential Insertion and Return Loss: U131 BGA L14 110 TDR: U131-BGA-L14-5 105 83.2 to 95.7 ohms -10 100 Magnitude (db) -15-20 -25-18.7dB @ 7.0GHz Ohms 95 90 85-30 80-35 Sdd12 Sdd11 Goal -40 0 5 10 15 20 25 30 35 40 Frequency (GHz) 75 U131-BGA-L14 70 0 0.1 0.2 0.3 0.4 Time (ns) 58

IL, RL and TDR: BGA L14 R1 Layer 3 with Backdrilled Stub a Lower Impedance 0 Differential Insertion and Return Loss: U131 BGA L14 R1 110 TDR: U131-BGA-L14-R1-5 105 77.9 to 95.3 ohms -10 100 Magnitude (db) -15-20 -25-15.9dB @ 7.0GHz Ohms 95 90 85-30 80-35 Sdd12 Sdd11 Goal -40 0 5 10 15 20 25 30 35 40 Frequency (GHz) 75 U131-BGA-L14-R1 70 0 0.1 0.2 0.3 0.4 Time (ns) 59

Next and Fext: BGA L14 Crosstalk between the Vias is high. 0 Next Crosstalk Contributors: U131 BGA L14 Next1= 1,3. 0 Fext Crosstalk Contributors: U131 BGA L14 Fext1= 1,4. -10-10 -28.4dB @ 7.0GHz -27.2dB @ 7.0GHz -20-20 -30-30 Magnitude (db) -40-50 -60 Magnitude (db) -40-50 -60-70 -70-80 -80-90 Next1 Goal -100 0 5 10 15 20 25 30 35 40 Frequency (GHz) -90 Fext1 Goal -100 0 5 10 15 20 25 30 35 40 Frequency (GHz) 60

Next and Fext: BGA L14 R1 9dB (2.8x) Reduction in FEXT 0 Next Crosstalk Contributors: U131 BGA L14 R1 Next1= 1,3. 0 Fext Crosstalk Contributors: U131 BGA L14 R1 Fext1= 1,4. -10-10 -33.9dB @ 7.0GHz -36.1dB @ 7.0GHz -20-20 -30-30 Magnitude (db) -40-50 -60 Magnitude (db) -40-50 -60-70 -70-80 -80-90 Next1 Goal -100 0 5 10 15 20 25 30 35 40 Frequency (GHz) -90 Fext1 Goal -100 0 5 10 15 20 25 30 35 40 Frequency (GHz) 61

Via Model Example: Very Low Crosstalk 62

Via Model: Amphenol XCedeHDPlus Finished Dia Drill Dia Pad Dia AntiPad Height AntiPad Width 14.2mil 17.7mil 30.0mil 44.0mil 70.0mil Default Stub Backdrill Dia Backdrill Hole? 14.2mil 29.2mil Yes Diff Port Zo 100 Layer Escape 20 Line Width EtchBack Line Space 5.25mil 0.1mil 9.8mil Material Thickness MyMeg6 Dk 3.2 Df 0.0067 Layers 26 126.1 mil Max Freq. Adapt Freq. 40 GHz 20 GHz 63

IL, RL and TDR: Amphenol XCedeHDPlus Differential Insertion and Return Loss: Sim0481-XCedeHDPlus-DC-L20-ShimRiser 0 110 TDR: Sim0481-XCedeHDPlus-DC-L20-ShimRiser -10 105 86.5 to 101.3 ohms -20-14.8dB @ 12.5GHz 100 Magnitude (db) -30 Ohms 95-40 90-50 Sdd12 Sdd11 Goal -60 0 5 10 15 20 25 30 35 40 Frequency (GHz) 85 Sim0481-XCedeHDPlus-DC-L20-ShimRiser 80 0 0.1 0.2 0.3 0.4 Time (ns) 64

Next and Fext: Amphenol XCedeHDPlus 6.2x Lower than BGA Alternating Layer Example Next Crosstalk Contributors: Sim0481-XCedeHDPlus-DC-L20-ShimRiser 0 Fext Crosstalk Contributors: Sim0481-XCedeHDPlus-DC-L20-ShimRiser 0 Next1= 1,3. Next2= 1,7. Next3= 1,5. Next4= 3,5. Fext1= 1,4. Fext2= 1,8. Fext3= 1,6. Fext4= 3,6. -10-10 -55.2dB @ 12.5GHz -51.7dB @ 12.5GHz -20-20 -30-30 Magnitude (db) -40-50 -60 Magnitude (db) -40-50 -60-70 -70-80 Next1 Next2 Next3-90 Next4 Goal -100 0 5 10 15 20 25 30 35 40 Frequency (GHz) -80 Fext1 Fext2 Fext3-90 Fext4 Goal -100 0 5 10 15 20 25 30 35 40 Frequency (GHz) 65

Etch Model Example: Mitre vs. Curved vs. Right Angle 66

Straight Etch and Mitred Bend 1.0 long, 6mil line, 9 mil space 67

Curved Bend and Right Angle Bend 1.0 long, 6mil line, 9 mil space 68

Insertion Loss Comparison 0 Insertion Loss-Curved Trace Study Magnitude (db) -0.25-0.5-0.75-1 -1.25-1.5-1.75-2 -2.25-2.5-2.75 Sdd12-Straight Sdd12-Mitred Sdd12-Curved Mitred and Curved Straight (best) Rt. Angle (worst) Sdd12-Right Angle -3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Frequency (GHz) Higher is better in this chart. After about 8GHz, the right angle bend is worse than the others. Mitred and Curved are about the same all the way out to 20GHz. Straight is best at all frequencies www.cshconsulting.net chris.heard100@gmail.com.

Return Loss Comparison Magnitude (db) -15-16 -17-18 -19-20 -21-22 -23-24 -25-26 -27-28 -29-30 -31-32 -33-34 -35-36 Rt. Angle Curved Mitred Return Loss-Curved Trace Study Rt. Angle Curved Mitred -37 Sdd11-Mitred -38 Sdd11-Curved -39 Sdd11-Right Angle -40 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Frequency (GHz) Lower is better in this chart. After about 7GHz, the Right Angle bend is worse. Mitred and Curved are about the same all the way out to 15GHz Anything under -25dB is considered great! www.cshconsulting.net chris.heard100@gmail.com. 70

TDR Comparison 103 Time Domain Wave Form Ohms 102 101 100 99 98 Rt. Angle Mitred Curved Right Angle Mitred Curved 97 0 0.1 0.2 0.3 0.4 0.5 0.6 Time (ns) Flatter is better in this chart. The Right Angle bend can be seen very clearly with the ~98ohm dip. The Curved and Mitred have very much the same TDR profile. www.cshconsulting.net chris.heard100@gmail.com. 71

Power Integrity Example 1 72

Example CPU CORE VOLTAGE Layout Input Power Inductor at 0.86V Assume a Total of 4 Amps DC evenly distributed at all the CPU CORE VOLTAGE pins at the device. 73

Stackup: With FaradFlex Embedded Capacitor Layers Width Space Zo (ohms) 1 SIG 2 3.60 mil 5.90 mil 96.7 5.40 mil 49.9 3.20 Dk= 4.01 2 GND 0.6 4.50 Dk= 4.41 3 SIG 0.6 3.40 mil 8.60 mil 99.4 4.20 mil 48.2 4.60 Dk= 4.39 4 GND 0.90 0.6 FaradFlex. Dk=4.6 5 0.8V 1.3 3.90 TU-862 HF 6 0.8V 1.3 0.90 7 GND 0.6 FaradFlex. Dk=4.6 4.60 Dk= 4.39 8 SIG 0.6 3.40 mil 8.60 mil 95.4 5.40 mil 49.9 4.50 Dk= 4.41 9 GND 0.6 3.20 Dk= 4.01 10 SIG 2 3.60 mil 5.90 mil 96.0 Thickness Over Copper = 40.5 mils Thickness Over Soldermask = 42.1 mils 74

Stackup: Without FaradFlex Width Space Zo (ohms) 1 SIG 2 3.60 mil 5.90 mil 96.7 5.40 mil 49.9 3.20 Dk= 4.01 2 GND 0.6 4.50 Dk= 4.41 3 SIG 0.6 3.40 mil 8.60 mil 99.4 4.20 mil 48.2 4.60 Dk= 4.39 4 GND 0.6 4.50 Dk= 4.39 5 0.8V 1.3 6 0.8V 1.3 3.90 TU-862 HF 4.50 Dk= 4.39 7 GND 0.6 4.60 Dk= 4.39 8 SIG 0.6 3.40 mil 8.60 mil 95.4 4.50 Dk= 4.41 9 GND 0.6 3.20 Dk= 4.01 5.40 mil 49.9 10 SIG 2 3.60 mil 5.90 mil 96.0 Thickness Over Copper = 47.7 mils Thickness Over Soldermask = 49.3 mils 75

CPU CORE VOLTAGE: Active Caps Part Number RefDes Capacitance (F) Parasitic L (H) Parasitic R (ohms) EMK105BJ104 C618 1.00E-07 4.30E-10 0.0144259 EMK105BJ104 C705 1.00E-07 4.30E-10 0.0144259 JMK105F105 C706 1.00E-06 1.71E-10 0.0023298 EMK105BJ104 C727 1.00E-07 4.30E-10 0.0144259 EMK105BJ104 C739 1.00E-07 4.30E-10 0.0144259 EMK105BJ104 C743 1.00E-07 4.30E-10 0.0144259 JMK105F105 C744 1.00E-06 1.71E-10 0.0023298 JMK105F105 C748a 1.00E-06 1.71E-10 0.0023298 EMK105BJ104 C752 1.00E-07 4.30E-10 0.0144259 CL21A476MQMNRN C758 4.70E-05 5.97E-10 0.00247449 CL21A476MQMNRN C762 4.70E-05 5.97E-10 0.00247449 C0603C106K9PAC C768 1.00E-05 7.86E-10 0.00390001 CL21A476MQMNRN C1603 4.70E-05 5.97E-10 0.00247449 CL21A476MQMNRN C1604 4.70E-05 5.97E-10 0.00247449 EMK105BJ104 C1606 1.00E-07 4.30E-10 0.0144259 CL21A476MQMNRN C1607 4.70E-05 5.97E-10 0.00247449 TMK105BJ103 C1927 1.00E-08 4.70E-10 0.0317317 TMK105BJ103 C1928 1.00E-08 4.70E-10 0.0317317 TMK105BJ103 C1929 1.00E-08 4.70E-10 0.0317317 TMK105BJ103 C1930 1.00E-08 4.70E-10 0.0317317 TMK105BJ103 C1931 1.00E-08 4.70E-10 0.0317317 TMK105BJ103 C1952 1.00E-08 4.70E-10 0.0317317 TMK105BJ103 C1953 1.00E-08 4.70E-10 0.0317317 TMK105BJ103 C1954 1.00E-08 4.70E-10 0.0317317 TMK105BJ103 C1955 1.00E-08 4.70E-10 0.0317317 TMK105BJ103 C1956 1.00E-08 4.70E-10 0.0317317 TMK105BJ103 C1957 1.00E-08 4.70E-10 0.0317317 Cap Value (uf) Quantity 0.01 11 0.1 7 1.0 3 10 1 47 5 Totals 27 76

CPU CORE VOLTAGE Plane SI Wave Import Voltage Source (0.86v, 0.001ohm) & Caps Current Sinks & Caps IC200 Port 77

Capacitor Plots 78

Example CPU CORE VOLTAGE: Zo vs Freq With Faradflex Layers Power Plane Impedance at IC200. Files: Toshiba KVDRIVE 1007 AO1 FaradFlex AC PlaneOnlyToshiba KVDRIVE 1007 AO1 FaradFlex AC PlaneandCaps 1e+006 Plane Only 100000 Plane With Caps Goal 10000 1000 Impedance (ohms) 100 10 1 0.1 Goal: 0.021ohm @ 100.0MHz. 0.01 0.001 0.001 0.01 0.1 1 10 100 1000 Frequency (MHz) 79

Example CPU CORE VOLTAGE: Zo vs Freq With Faradflex Layers and No 0.01uF Caps 1e+006 100000 Plane Only Plane With Caps Goal 10000 1000 Impedance (ohms) 100 10 1 0.1 Goal: 0.021ohm @ 100.0MHz. 0.01 0.001 0.001 0.01 0.1 1 10 100 1000 Frequency (MHz) 80

Example CPU CORE VOLTAGE: Zo vs Freq Without Faradflex Layers 1e+006 100000 Plane Only Plane With Caps Goal 10000 1000 Impedance (ohms) 100 10 1 0.1 Goal: 0.021ohm @ 100.0MHz. 0.01 0.001 0.001 0.01 0.1 1 10 100 1000 Frequency (MHz) 81

Example CPU CORE VOLTAGE Current Plot 82

Layer 6 Example CPU CORE VOLTAGE Voltage Plot: IR Drop: 1.5mV, 4A. 0.375mΩ 83

Layer 7 Voltage Plot: GND IR Drop: 0.681mV 84

Power Integrity Example 2 85

Backplane 12V Current 6A At Each Power Connector 12V Connectors from Power Supply 78 amps total. www.cshconsulting.net chris.heard100@gmail.com. 86

Voltage Plot. Gnd Plane: 15mV Total 15mV Drop 87

Voltage Plot: +12V Plane: 80mV Total 12.0V 80mV Drop Too High 11.92V 64.0A 0.58A 13.3A www.cshconsulting.net chris.heard100@gmail.com. 88

+12V Current Density www.cshconsulting.net chris.heard100@gmail.com. 89