Integration, Architecture, and Applications of 3D CMOS Memristor Circuits

Integration, Architecture, and Applications of 3D CMOS Memristor Circuits K. T. Tim Cheng and Dimitri Strukov Univ. of California, Santa Barbara ISPD 2012 1

3D Hybrid CMOS/NANO add-on nanodevices layer CMOS layer CMOS stack bottom nanowire level top nanowire level similar two-terminal nanodevices at each crosspoint CMOS stack + nano add-on nanowire crossbar of two-terminal devices (memristors) 2

Resistive Switching Memristive Devices (latching switches, a.k.a. resistive switches, a.k.a. programmable diodes, a.k.a. memristive switches) +Wide range of material systems and physical phenomena Current ( ua ) 200 100 50 nm hp 0 + Pt 100 TiO 2 V <50 ns TiO x Pt 200 2 1 0 1 2 Voltage ( V ) 3 J. Yang Iet al. Natue Nano, (2008)

Area Distributed CMOL Interfaces interface via ( pin ) nanodevices (latching switches) gold nanowire levels (nanoimprint) interface pins Tip radii 2-10 nm CMOS stack (just a cartoon) MOSFET Si wafer K. Likharev (2004, 2005); D. Strukov and K. Likharev (2006) http://www.oxfordplasma.de/ process/sibo_wtc.htm 4

AFOSR MURI HyNano: 3D Hybrid CMOS Nano Circuits 5

The HyNano Team Michael Chabinyc Materials, UCSB Tim Cheng ECE, UCSB (Director) Marivi Fernandez Serra Physics, Stony Brook Konstantin K. Likharev Physics, Stony Brook Wei Lu EECS, Michigan Susanne Stemmer Materials, UCSB Dmitri Strukov ECE, UCSB Luke Theogarajan ECE, UCSB Qiangfei Xia ECE, UM Amherst 6

Project Overview information processing APPLICATIONS 3D hybrid memories 3D hybrid SoC ARCHITECTURES/CIRCUITS 3D CMOS/nano circuits w. area distributed interface mixed signal CrossNets Optical lithography a Si e beam metal oxide nanoimprint reproducible, high performance, high endurance devices MATERIALS organic DEVICES solid electrolyte compact models drift diffusion and ab initio modeling 7

Thrust Area #1: Application/Architecture/Ckt Exploration Memory arrays for high performance computing CMOL based FPGA Neuromorphic networks for bio inspired information processing Evolvable analog circuits Tunable bias network for analog design Weighted multiply and add circuits High precision Digital to Analog converter 8

CMOL Interface Integrating CMOS with Crossbar Memory Array interface via ( pin ) nanodevices (latching switches) gold nanowire levels (nanoimprint) interface pins CMOS stack (just a cartoon) MOSFET Si wafer

Addressing Crossbar Memory Array There are two types of pins Blues and Reds Each array of pins has its own decoding scheme Double decoding scheme: An array of N 2 blue pins uniquely accessed with 2N control signals. Another 2N control signals for the corresponding N 2 red pins

Double Decoding Scheme Four decoders: demux memory cell array select decoder select decoder mux/demux data I/O 11

Crossbar Construction Top View

Crossbar Construction Top View

Crossbar Construction Side View interface via ( pin ) nanodevices (latching switches) gold nanowire levels (nanoimprint) interface pins CMOS stack (just a cartoon) MOSFET Si wafer

Crossbar Construction Top View

Crossbar Construction Bottom Level

Crossbar Construction Top Level

Crossbar Construction

Crossbar Construction

Crossbar Construction Connectivity Domain

Crossbar Construction

Crossbar Construction

Unused Address Space The red pin can only interact with blue pins in its connectivity domain Address space provided by yellow cells is wasted!

Key Geometric Parameters Distance between nanowires is 2F NANO Size of cell is 2βF CMOS β 2 = r 2 + 1 where r is an odd integer > 1. Crossbar is tilted by an angle α equal to ArcTan(1/r) with respect to the pins. # of reachable crosspoints per wire segment is r 2 1

Crossbar Construction Bottom Level

Adding a Second Crossbar Layer Connectivity domain in the first crossbar layer Connectivity domain in the second crossbar layer The mapping is done through pin translation wires Blue pins are common to all crossbar layers. Red pins are "redefined" for each layer using the pin translation wires.

First layer of red pins.

First layer of red and blue pins.

Layer of (bluish) wires connected to the blue pins.

Single (orange) wire connected to a red pin. The cross points with the bottom wires are shown in green.

First complete crossbar layer.

A single pin translation wire (in yellow).

Every orange wire is translated into another point using the same type of pin translation wire.

The first crossbar layer with its pins translation wires are then buried in SiO 2

We start to build the next crossbar layer (bluish wires)

We start to build the next crossbar layer (bluish wires)

We add the orange wires (the cross points are formed)

And we add the pins translation wires and repeat the process

Maximum Number of Layers Each layer has N 2 cells. There are r 2 1 cross points per cell. That gives us a total of N 2 (r 2 1) cross points per layer. The double decoding scheme allows us to address up to N 4 locations Which means that we can (potentially) have up to N 2 /(r 2 1) crossbar layers.

How Does it Stand Up as a Memory? Memristor PCM STTRAM DRAM Flash HDD Density (F 2 ) <4 8 16 37 64 6 8 4 6 2/3 Energy per bit (pj) 0.1 3 2 27 0.1 2 10000 1 10x10 9 Read time (ns) 10-100(?) 20 70 10 30 10 50 25000 5 8x10 6 Write time (ns) ~10 50 500 13 95 10 50 200000 5 8x10 6 Retention years years weeks? <<second years years Endurance (cycles) >10 12 10 7 10 15 10 15 10 6 10 4 40

If Successful, 3D Hybrids Can Achieve.. Unprecedented memory density Footprint of a nano device is 4F nano2 /K, for K vertically integrated crossbar layers Potentially up to 10 14 bits on a single 1 cm 2 chip Enormous memory bandwidth Potentially up to 10 18 bits/second/cm 2 At manageable power dissipation With abundant redundancy for yield/reliability 41

Thrust Area #1: Application/Architecture/Ckt Exploration Memory arrays for high performance computing CMOL based FPGA Neuromorphic networks for bio inspired information processing Evolvable analog circuits Tunable bias network for analog design Weighted multiply and add circuits High precision Digital to Analog converter 42

CMOL Based FPGA Programming for xpoint memristors similar to CMOL digital memories Uniform fabric with CMOS inverter cells Crossbar wires for routings cell A B F A+B B A B nanodevices A R ON C wire R pass A+B CMOS inverter 43

Density: CMOS vs. CMOL Metrics (units) 2009 2010 2011 2012 2013 Comments Half-pitch F CMOS (nm) 50 45 40 36 32 In accordance with ITRS Half-pitch F nano (nm) 20 18 16 14 12 - CMOS memories (Gbits/cm 2 ) 6.7 8.2 10.5 13 16 Follows ITRS (with A = 6F 2 CMOS ) CMOL memories (Gbits/cm 2 ) 4 10 23 36 67 Initial progress impacted by q CMOS FPGA (Mgates/cm 2 ) 0.4 0.5 0.6 0.8 1.0 Rescaled from 0.18 μm rules CMOL FPGA (Mgates/cm 2 ) 625 775 1,000 1,200 1,500 - Metrics (units) 2016 2019 2022 2025 2028 Comments Half-pitch F CMOS (nm) 30 28 26 24 22 Grows slower than in ITRS Half-pitch F nano (nm) 10 6 4 3.5 3 - CMOS memories (Gbits/cm 2 ) 18 21 25 29 35 Follows A = 6F 2 CMOS CMOL memories (Gbits/cm 2 ) 100 350 900 1,200 1,700 Spectacular progress at lower q CMOS FPGA (Mgates/cm 2 ) 1.1 1.3 1.5 1.7 2.1 Rescaled from 0.18 μm rules CMOL FPGA (Mgates/cm 2 ) 1,700 2,000 2,300 2,700 3,200-44

Thrust Area #1: Application/Architecture/Ckt Exploration Memory arrays for high performance computing CMOL based FPGA Neuromorphic networks for bio inspired information processing Evolvable analog circuits Tunable bias network for analog design Weighted multiply and add circuits High precision Digital to Analog converter 45

Thrust Areas: # 2: High Performance/ Yield Devices # 3: 3D Hybrids Integration Integrating CMOS with devices of different materials: a Si Metal oxide Organic Solid state electrolyte Using: Nanoimprint E beam lithography Optical lithography Heterogeneous wafer level integration (a) (b) E Beam Crossbar Arrays (Lu) 50 μm 100 μm <20nm Overlay Alignment (Xia) 46

Integrated Crossbar Array/CMOS System PI: Lu Crossbar array Integrated crossbar/cmos chip with probe card attached CMOS Kim et al. Nano Lett., 12, 389 395 (2012). 47

Integrated Crossbar Array/CMOS System 48

Performance of a Si and Metal Oxide Device Array on filament off 100nm Tight distribution from 256 devices measured Devices shown excellent on/off and intrinsic diode characteristics 49

Project Overview information processing APPLICATIONS 3D hybrid memories 3D hybrid SoC ARCHITECTURES/CIRCUITS 3D CMOS/nano circuits w. area distributed interface mixed signal CrossNets Optical lithography a Si e beam metal oxide nanoimprint reproducible, high performance, high endurance devices MATERIALS organic DEVICES solid electrolyte compact models drift diffusion and ab initio modeling 50

BACKUP SLIDES 51

Thrust Area #3: High Performance/ Yield/ Reproducibility Devices a Si (Lu) Metal oxide (Stemmer, Xia) Organic (Chabinyc) Solid state electrolyte (Lu) 52

a Si Memristive Devices and Arrays PI: Lu Current (100nA) 3.0 1st cycle 2.5 After 2nd cycle 2.0 1.5 1.0 0.5 0.0 10-6 10-7 10-8 10-9 10-10 10-11 10-12 -4-2 0 2 4 Voltage -4-2 0 2 4 6 Voltage (V) # of devices 50 40 30 20 10 0 2.6 2.9 3.2 3.5 3.8 4.1 4.4 V th (V) on filament 100nm off Lu et al., Nano Lett. (2008, 2009) 53

Project Organization UCSB CMOS circuit design for CMOL integration MBE fabrication of memristive devices; Organic memristive devices Memristive device modeling Digital and analog 3D hybrid circuit architectures Cheng, Strukov, Theogarajan Stemmer Chabinyc Strukov Cheng, Strukov, Theogarajan U. Michigan UMass Stony Brook University a-si & solid electrolyte devices; 3D integration with CMOS Lu Metal oxide memristive devices; 3D integration with CMOS Xia Ab-initio simulation of memristive devices Fernandez-Serra, Likharev Mixed-signal neuromorphic 3D hybrid circuit architectures Likharev <------- experiment ---------> <---------theory/modeling-------> 54

bottom (nano)wire level Read Crossbar Architecture top (nano)wire level similar two terminal devices at each crosspoint v w Xbar to preserve density Passive (no transistors) but nonlinear I V Common way (from periphery) i v r v w v Write V V V = V r /2 V = V w /2 A CMOS for V V =V r /2 V =V decoding r V =V w and sensing V V =V w /2 July 2011 MURI Kickoff 55

Generic Memory Array Asserting a word line makes the access element to place the contents of the memory element in the bit line. A particular bit is then selected with a MUX. Access element multiplex er decode r Memory element

Generic Memory Array An array of N 2 memory elements can be uniquely accessed using 2N control signals (word+bit lines). Other representation of the same array

Area Distributed CMOL Interfaces (II) Most important feature: pin array tilt by angle = arcsin(f nano / F CMOS ) = arctan(1/r) pin 1 pin 2A 2 F CMOS 2rF nano A B pin 2B 2F nano Every nanowire (and hence every crosspoint) may be addressed from CMOS! K. Likharev (2004, 2005); D. Strukov and K. Likharev (2006) 58

A Possible Solution With this particular connectivity domain geometry (r=3), we can cover all the plane... But that is not always the case. The pin translation wires are another layer of wires on top of the crossbar We can add more crossbar layers by simply inserting a layer of pin translation wires between them.

Crossbar Analysis The crossbar is rotated by an angle α such that: Where r is an integer (an odd integer greater than 1). Once we set r and β (the CMOS cell complexity), the angle α and F nano are fixed as well the length of the wires in the crossbar and the number of memristive devices reachable per wire segment.

Crossbar Analysis The parameter r also sets the maximum, minimum and average paths the electric signals have to propagate to access a bit (a memristive device). This paths are given by: Maximum (worst) case: 2F nano * (r 2 -r + 1) Minimum (best) case: 2F nano * r Average (real) case: 2Fnano * (r 2 + 1)/2

3D Hybrid Integration with Multi Layer Crossbars crosspoint device in 1 st layer crosspoint device in 2 nd layer E 5 via translation layer crossbar layer D 4 C 3 B 2 A ~N 2 β 2 crosspoint devices per layer (out of N 4 total) CMOS layer N data/control lines N 2 access devices/vias 1 A B C D E 1 2 3 4 5 connectivity domain in 1 st layer via translation wires D. Strukov and R. S. Williams (2009) connectivity domain in 2 nd layer 62

APPLICATIONS (Cheng, Likharev, Strukov, Theogarajan) information processing Project Overview 3D hybrid memories ARCHITECTURES/CIRCUITS (Cheng, Likharev, Strukov, Theogarajan) 3D CMOS/nano circuits w. area distributed interface 3D hybrid SoC mixed signal CrossNets Optical lithography (Strukov, Stemmer) a Si (Lu) e beam (Lu) MATERIALS metal oxide (Xia, Stemmer) nanoimprint (Xia, Chabinyc) reproducible, high performance, high endurance devices DEVICES organic solid electrolyte (Chabinyc) (Lu) compact models (Likharev, Strukov) drift diffusion and ab initio modeling (Fernandez Serra, Strukov) 63

IC Applications Continue to Demand More Memory and Higher Bandwidth High Networking GPU, CPU, Chipset & FPGA Memory BT/WiFi Baseband Application Processor Chip Size PM Transceiver Peripheral I/O Controller PA Switch Discrete For most applications running on highend SoCs, amount of available memory and memory bandwidth have been and will continue to be the bottlenecks 100 200 300 400 500 600 I/O High 64

Bistable Two Terminal Devices (latching switches, a.k.a. resistive switches, a.k.a. programmable diodes, a.k.a. memristive switches) Demonstrated with many materials; no clear winner yet; few reproducibility reports, e.g.: Si /α-si / M: Ti / Pt / TiO 2 / Pt: S. H. Jo and W. Lu (2008) Q. Xia et al. (2009); J. Borghetti et al. (2010) 65

Device Requirements Vary for Different Ckts/Architectures/Applications Dynamic range of resistance DC Signal AC Small Tuning Large Memory, FPGA, DAC MAC 66

CMOS CMOL Integration: Initial (a) Demonstration (c) PI: Xia (d) (e) (b) Xia, Strukov et al. (2009) 67