MHz Rail-to-Rail Amplifiers OBSOLETE PRODUCT POSSIBLE SUBSTITUTE PRODUCT EL8 AND EL8 DATASHEET FN74 Rev 7. The EL8, EL8 represent single rail-to-rail amplifiers with a -db bandwidth of MHz and slew rate of 6V/µs. Running off a very low.6ma supply current, the EL8, EL8 also feature inputs that go to.v below the V S - rail. The EL8 includes a fast-acting disable/power-down circuit. With a ns disable and a ns enable, the EL8 is ideal for multiplexing applications. The EL8, EL8 are designed for a number of general purpose video, communication, instrumentation, and industrial applications. The EL8 is available in 8 Ld SOIC and 6 Ld SOT- packages and the EL8 is available in a Ld SOT- package. All are specified for operation over the -4 C to +8 C temperature range. Ordering Information PART NUMBER PART MARKING PACKAGE PKG. DWG. # EL8IS 8IS 8 Ld SOIC MDP7 Features MHz -db bandwidth 6V/µs slew rate Low supply current =.6mA Supplies from V to.v Rail-to-rail output Input to.v below V S - Fast ns disable (EL8 only) Low cost Pb-Free available (RoHS compliant) Applications Video amplifiers Portable/hand-held products Communications devices EL8IS-T7 8IS 8 Ld SOIC MDP7 EL8IS-T 8IS 8 Ld SOIC MDP7 EL8ISZ (Note) 8ISZ 8 Ld SOIC (Pb-free) MDP7 Pinouts EL8 (8 LD SOIC) TOP VIEW EL8ISZ-T7 (Note) 8ISZ 8 Ld SOIC (Pb-free) MDP7 NC 8 ENABLE EL8ISZ-T (Note) 8ISZ 8 Ld SOIC (Pb-free) MDP7 EL8IW-T7 4 6 Ld SOT- MDP8 IN- IN+ - + 7 6 VS+ OUT EL8IW-T7A 4 6 Ld SOT- MDP8 VS- 4 NC EL8IWZ-T7 (Note) EL8IWZ-T7A (Note) BAVA BAVA 6 Ld SOT- (Pb-free) 6 Ld SOT- (Pb-free) MDP8 MDP8 EL8 (6 LD SOT-) TOP VIEW EL8IW-T7 Ld SOT- MDP8 EL8IW-T7A Ld SOT- MDP8 EL8IWZ-T7 (Note) EL8IWZ-T7A (Note) BAWA BAWA Ld SOT- (Pb-free) Ld SOT- (Pb-free) MDP8 MDP8 *Please refer to TB47 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and % matte tin plate PLUS ANNEAL - e termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-. OUT IN+ OUT IN+ + EL8 ( LD SOT-) TOP VIEW + - - VS- 6 VS+ ENABLE 4 IN- VS- VS+ 4 IN- FN74 Rev 7. Page of 4
EL8, EL8 Absolute Maximum Ratings (T A = C) Supply Voltage from V S + to V S -..........................V Input Voltage........................ V S + +.V to V S - -.V Differential Input Voltage................................V Continuous Output Current........................... 4mA Thermal Information Power Dissipation............................. See Curves Storage Temperature........................-6 C to + C Ambient Operating Temperature................-4 C to +8 C Operating Junction Temperature...................... + C Pb-free reflow profile..........................see link below http://www.intersil.com/pbfree/pb-freereflow.asp CAUTION:Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: T J = T C = T A Electrical Specifications V S + = V, V S - = GND, T A = + C, V CM =.V, R L to.v, A V =, Unless Otherwise Specified. PARAMETER DESCRIPTION CONDITIONS MIN (Note ) TYP MAX (Note ) UNIT INPUT CHARACTERISTICS V OS Offset Voltage -8 -.8 +8 mv TCV OS Offset Voltage Temperature Coefficient Measured from T MIN to T MAX µv/ C IB Input Bias Current V IN = V -9-6 µa I OS Input Offset Current V IN = V..6 µa TCI OS Input Bias Current Temperature Coefficient Measured from T MIN to T MAX na/ C CMRR Common Mode Rejection Ratio V CM = -.V to +.V 7 9 db CMIR Common Mode Input Range V S - -. V S + -. V R IN Input Resistance Common Mode. M C IN Input Capacitance. pf AVOL Open Loop Gain = +.V to +.V, R L = k to GND 7 9 db = +.V to +.V, R L = to GND 8 db OUTPUT CHARACTERISTICS R OUT Output Resistance A V = + m V OP Positive Output Voltage Swing R L = k 4.8 4.9 V R L = 4.6 4.7 V V ON Negative Output Voltage Swing R L = mv R L = k mv I OUT Linear Output Current 6 ma I SC (source) Short Circuit Current R L = 7 8 ma I SC (sink) Short Circuit Current R L = ma POWER SUPPLY PSRR Power Supply Rejection Ratio V S + = 4.V to.v 7 9 db I S-ON Supply Current - Enabled.6 6 ma I S-OFF Supply Current - Disabled µa ENABLE (EL8 ONLY) t EN Enable Time ns t DS Disable Time ns V IH-ENB ENABLE Pin Voltage for Power-up.8 V V IL-ENB ENABLE Pin Voltage for Shut-down V FN74 Rev 7. Page of 4
EL8, EL8 Electrical Specifications V S + = V, V S - = GND, T A = + C, V CM =.V, R L to.v, A V =, Unless Otherwise Specified. (Continued) PARAMETER DESCRIPTION CONDITIONS MIN (Note ) I IH-ENB ENABLE Pin Input Current High 8.6 µa I IL-ENB ENABLE Pin Input for Current Low. µa AC PERFORMANCE BW -db Bandwidth A V = +, R F =, MHz A V = -, R F = k, 4 MHz A V = +, R F = k, 6 MHz A V = +, R F = k, 8 MHz BW ±.db Bandwidth A V = +, R F =, MHz Peak Peaking A V = +, R L = k, db GBWP Gain Bandwidth Product MHz PM Phase Margin R L = k, SR Slew Rate A V =, R L =, =.V to 4.V 6 V/µs t R Rise Time.V STEP, % to 8% 4 ns t F Fall Time.V STEP, % to 8% ns OS Overshoot mv step % t PD Propagation Delay mv step ns t S.% Settling Time mv step ns dg Differential Gain A V = +, R F = k, R L =. % dp Differential Phase A V = +, R F = k, R L =. e N Input Noise Voltage f = khz nv/ Hz i N + Positive Input Noise Current f = khz.7 pa/ Hz i N - Negative Input Noise Current f = khz. pa/ Hz NOTE:. Parts are % tested at + C. Over-temperature limits established by characterization and are not production tested. Pin Descriptions PIN TYP MAX (Note ) UNIT EL8IS EL8IW EL8IW NAME FUNCTION NC Not connected 4 4 IN- Inverting input IN+ Non-inverting input 4 VS- Negative power supply NC Not connected 6 OUT Amplifier output 7 6 VS+ Positive power supply 8 ENABLE Enable and disable input FN74 Rev 7. Page of 4
EL8, EL8 Simplified Schematic Diagram V S+ I I R 6 R 7 R 8 Q Q 6 V BIAS Q 7 R IN+ R R Q Q IN- DIFFERENTIAL TO SINGLE ENDED DRIVE GENERATOR OUT V BIAS Q Q 4 Q 8 R 4 R R 9 Typical Performance Curves V S- GAIN (db) - - A V = R L = k V OP-P = V V OP-P = V V OP-P = mv - k M M M G NORMALIZED GAIN (db) - R F = R G = k R F = R G = R F = R G = k - A V = R L = k - k M M M G FIGURE. FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGE LEVELS FIGURE. SMALL SIGNAL FREQUENCY RESPONSE vs R F AND R G NORMALIZED GAIN (db) 4 - -4 R L = k A V = A V = A V = A V = NORMALIZED GAIN (db) 4 - -4 R L = k R F = k A V = - A V = - A V = - -6 k M M M G FIGURE. SMALL SIGNAL FREQUENCY RESPONSE FOR VARIOUS NON-INVERTING GAINS -6 k M M M G FIGURE 4. SMALL SIGNAL FREQUENCY RESPONSE FOR VARIOUS INVERTING GAINS FN74 Rev 7. Page 4 of 4
EL8, EL8 Typical Performance Curves (Continued) A V = V OP-P = mv R L = R L = k 9 A V = R F = R G = k GAIN (db) - R L = GAIN (db) 7 R L = R L = k, - - k M M M G FIGURE. SMALL SIGNAL FREQUENCY RESPONSE FOR VARIOUS R LOAD k M M M G FIGURE 6. SMALL SIGNAL FREQUENCY RESPONSE vs VARIOUS R LOAD GAIN (db) - - A V = R L = k V OP-P = mv C L = pf C L =.pf NORMALIZED GAIN (db) 9 7 A V = R L = k R F = R G = k C L =pf C L = pf C L = 4pF C L = 9pF - k M M M G k M M M G FIGURE 7. SMALL SIGNAL FREQUENCY RESPONSE vs C L FIGURE 8. SMALL SIGNAL FREQUENCY RESPONSE FOR VARIOUS C L 7 R L = R L = k 4 - - A V = R L = k GAIN (db) - R L = PHASE ( ) GAIN (db) - -7 - R L = k 4-9 -9 k k k M M M -4 G - k k k M M M G FIGURE 9. OPEN LOOP GAIN AND PHASE vs FREQUENCY FIGURE. DISABLED OUTPUT ISOLATION FREQUENCY RESPONSE FN74 Rev 7. Page of 4
EL8, EL8 Typical Performance Curves (Continued) - PSRR (db) - - -7-9 PSRR- PSRR+ BANDWIDTH (MHz) 4 4 R L = k A V = A V = - k k k M M M FIGURE. POWER SUPPLY REJECTION RATIO vs FREQUENCY.. 4. 4... V S (V) FIGURE. SMALL SIGNAL BANDWIDTH vs SUPPLY VOLTAGE IMPEDANCE ( ). PEAKING (db)..... R L = k A V = A V =. k k M M M.. 4. 4... V S (V) FIGURE. OUPUT IMPEDANCE vs FREQUENCY FIGURE 4. SMALL SIGNAL PEAKING vs SUPPLY VOLTAGE - - 8 CMRR (db) - -7 I S (ma) 6 4-9 - k M M M.... 4 4.. V S (V) FIGURE. COMMON-MODE REJECTION RATIO vs FREQUENCY FIGURE 6. SUPPLY CURRENT vs SUPPLY VOLTAGE FN74 Rev 7. Page 6 of 4
EL8, EL8 Typical Performance Curves (Continued) DISTORTION (dbc) -6-7 -8-9 - R L = k A V = HD@MHz HD@MHz HD@MHz HD@MHz HD@MHz HD@MHz 4 V O(P-P) (V) DISTORTION (dbc) -7-7 -8-8 -9 f = MHz HD@A V = HD@A V = HD@A V = HD@A V = -9 V O = V P-P FOR A V = V O = V P-P FOR A V = - K K R LOAD ( ) FIGURE 7. HARMONIC DISTORTION vs OUTPUT VOLTAGE FIGURE 8. HARMONIC DISTORTION vs LOAD RESISTANCE DISTORTION (dbc) - -6-7 -8-9 - R L = k V O = V P-P FOR A V = V O = V P-P FOR A V = HD@A V = HD@A V = HD@A V = HD@A V = 4 VOLTAGE NOISE (nv/ Hz) CURRENT NOISE (pa/ Hz), k e N I N + I N - k k k M M FREQUENCY (MHz) FIGURE 9. HARMONIC DISTORTION vs FREQUENCY FIGURE. VOLTAGE AND CURRENT NOISE vs FREQUENCY, A V =, R L = k TO.V,, A V =, R L = k TO.V,...... ns/div ns/div FIGURE. LARGE SIGNAL TRANSIENT RESPONSE - RISING FIGURE. LARGE SIGNAL TRANSIENT RESPONSE - FALLING FN74 Rev 7. Page 7 of 4
EL8, EL8 Typical Performance Curves (Continued), A V =, R L = k TO.V,, A V =, R L = k TO.V.6 V IN...4.6..4. ns/div FIGURE. SMALL SIGNAL TRANSIENT REPONSE µs/div FIGURE 4. OUTPUT SWING, A V =, R L = k TO.V. CH ENABLE INPUT. CH µs/div CH, CH, V/DIV, M=ns FIGURE. OUTPUT SWING FIGURE 6. ENABLED RESPONSES.4 JEDEC JESD-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD CH CH ENABLE INPUT POWER DISSIPATION (W)...8.6.4. 99mW 4mW SOT-/6 JA = + C/W SO8 JA = + C/W CH, CH,.V/DIV, M = ns FIGURE 7. DISABLED RESPONSE 7 8 AMBIENT TEMPERATURE ( C) FIGURE 8. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FN74 Rev 7. Page 8 of 4
EL8, EL8 Typical Performance Curves (Continued) POWER DISSIPATION (W) JEDEC JESD- LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD..9.8.7.6. 9mW.4... 6mW SOT-/6 JA = +6 C/W SO8 JA = +6 C/W 7 8 AMBIENT TEMPERATURE ( C) FIGURE 9. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE Description of Operation and Application Information Product Description The EL8, EL8 are wide bandwidth, single supply, low power and rail-to-rail output voltage feedback operational amplifiers. Both amplifiers are internally compensated for closed loop gain of + of greater. Connected in voltage follower mode and driving a k load, the EL8, EL8 have a -db bandwidth of MHz. Driving a load, the bandwidth is about MHz while maintaining a 6V/µs slew rate. The EL8 is available with a power-down pin to reduce power to µa typically while the amplifier is disabled. Input, Output and Supply Voltage Range The EL8, EL8 have been designed to operate with a single supply voltage from V to.v. Split supplies can also be used as long as their total voltage is within V to.v. The amplifiers have an input common mode voltage range from.v below the negative supply (VS- pin) to within.v of the positive supply (VS+ pin). If the input signal is outside the above specified range, it will cause the output signal to be distorted. The output of the EL8, EL8 can swing rail-to-rail. As the load resistance becomes lower, the ability to drive close to each rail is reduced. For the load resistor k, the output swing is about 4.9V at a V supply. For the load resistor, the output swing is about 4.6V. Choice of Feedback Resistor and Gain Bandwidth Product For applications that require a gain of +, no feedback resistor is required. Just short the output pin to the inverting input pin. For gains greater than +, the feedback resistor forms a pole with the parasitic capacitance at the inverting input. As this pole becomes smaller, the amplifier s phase margin is reduced. This causes ringing in the time domain and peaking in the frequency domain. Therefore, R F has some maximum value that should not be exceeded for optimum performance. If a large value of R F must be used, a small capacitor in the few pf range in parallel with R F can help to reduce the ringing and peaking at the expense of reducing the bandwidth. As far as the output stage of the amplifier is concerned, the output stage is also a gain stage with the load. R F and R G appear in parallel with R L for gains other than +. As this combination gets smaller, the bandwidth falls off. Consequently, R F also has a minimum value that should not be exceeded for optimum performance. For a gain of +, R F = is optimum. For the gains other than +, optimum response is obtained with R F between to k. The EL8, EL8 have a gain bandwidth product of MHz. For gains, its bandwidth can be predicted by the Equation : Gain BW = MHz (EQ. ) Video Performance For good video performance, an amplifier is required to maintain the same output impedance and the same frequency response as DC levels are changed at the output. This is especially difficult when driving a standard video load of because the change in output current with DC level. Special circuitry has been incorporated in the EL8, EL8 to reduce the variation of the output impedance with the current output. This results in dg and dp specifications of.% and., while driving at a gain of. Driving high impedance loads would give a similar or better dg and dp performance. Driving Capacitive Loads and Cables The EL8, EL8 can drive pf loads in parallel with k with less than db of peaking at a gain of +. If less peaking is desired in applications, a small series resistor (usually between to ) can be placed in series with the FN74 Rev 7. Page 9 of 4
EL8, EL8 output to eliminate most peaking. However, this will reduce the gain slightly. If the gain setting is greater than, the gain resistor R G can then be chosen to make up for any gain loss which may be created by the additional series resistor at the output. When used as a cable driver, double termination is always recommended for reflection-free performance. For those applications, a back-termination series resistor at the amplifier s output will isolate the amplifier from the cable and allow extensive capacitive drive. However, other applications may have high capacitive loads without a back-termination resistor. Again, a small series resistor at the output can help to reduce peaking. Disable/Power-Down The EL8 can be disabled and its output placed in a high impedance state. The turn-off time is about ns and the turn-on time is about ns. When disabled, the amplifier s supply current is reduced to µa typically, thereby effectively eliminating the power consumption. The amplifier s power down can be controlled by standard TTL or CMOS signal levels at the ENABLE pin. The applied logic signal is relative to V S - pin. Letting the ENABLE pin float or applying a signal that is less than.8v above V S - will enable the amplifier. The amplifier will be disabled when the signal at ENABLE pin is V above V S -. Output Drive Capability The EL8, EL8 do not have internal short circuit protection circuitry. They have a typical short circuit current of 8mA sourcing and ma sinking for the output is connected to half way between the rails with a resistor. If the output is shorted indefinitely, the power dissipation could easily increase such that the part will be destroyed. Maximum reliability is maintained if the output current never exceeds ±4mA. This limit is set by the design of the internal metal interconnections. Power Dissipation With the high output drive capability of the EL8, EL8, It is possible to exceed the + C absolute maximum junction temperature under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the application to determine if the load conditions or package types need to be modified for the amplifier to remain in the safe operating area. The maximum power dissipation allowed in a package is determined according to Equation : T JMAX T AMAX PD MAX = -------------------------------------------- (EQ. ) JA Where: T JMAX = Maximum junction temperature T AMAX = Maximum ambient temperature JA = Thermal resistance of the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the load, or: For sourcing, Equation : PD MAX = V S I SMAX + V S --------------- (EQ. ) R L For sinking, Equation 4: PD MAX = V S I SMAX + V - S I (EQ. 4) LOAD Where: V S = Total supply voltage I SMAX = Maximum quiescent supply current = Maximum output voltage of the application R LOAD = Load resistance tied to ground I LOAD = Load current By setting the two PD MAX equations equal to each other, we can solve the output current and R LOAD to avoid the device overheat. Power Supply Bypassing and Printed Circuit Board Layout As with any high frequency device, a good printed circuit board layout is necessary for optimum performance. Lead lengths should be as short as possible. The power supply pin must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the V S - pin is connected to the ground plane, a single 4.7µF tantalum capacitor in parallel with a.µf ceramic capacitor from V S + to GND will suffice. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. In this case, the VS- pin becomes the negative supply rail. For good AC performance, parasitic capacitance should be kept to a minimum. Use of wire wound resistors should be avoided because of their additional series inductance. Use of sockets should also be avoided if possible. Sockets add parasitic inductance and capacitance that can result in compromised performance. Minimizing parasitic capacitance at the amplifier s inverting input pin is very important. The feedback resistor should be placed very close to the inverting input pin. Strip line design techniques are recommended for the signal traces. FN74 Rev 7. Page of 4
EL8, EL8 Typical Applications VIDEO SYNC PULSE REMOVER Many CMOS analog to digital converters have a parasitic latch up problem when subjected to negative input voltage levels. Since the sync tip contains no useful video information and it is a negative going pulse, we can chop it off. Figure shows a gain of connections for EL8, EL8. Figure shows the complete input video signal applied at the input, as well as the output signal with the negative going sync pulse removed. B A MHz V P-P k + - MHz + V P-P - +.V -.V k +.V -.V V IN + - V V S+ V S- ENABLE k k k k FIGURE. TWO TO ONE MULTIPLEXER FIGURE. SYNC PULSE REMOVER ENABLE V -.V -.V V -.V V IN.V V V V V A B -V.V V M = ns/div M = µs/div FIGURE. VIDEO SIGNAL MULTIPLEXER Besides the normal power-down usage, the ENABLE pin of the EL8 can be used for multiplexing applications. Figure shows two EL8 with the outputs tied together, driving a back terminated video load. A V P-P MHz sine wave is applied to Amp A and a V P-P MHz sine wave is applied to Amp B. Figure shows the ENABLE signal and the resulting output waveform at. Observe the breakbefore-make operation of the multiplexing. Amp A is on and V IN is passed through to the output when the ENABLE signal is low and turns off in about ns when the ENABLE signal is high. About ns later, Amp B turns on and V IN is passed through to the output. The break-before-make operation ensures that more than one amplifier isn t trying to drive the bus at the same time. FIGURE. SINGLE SUPPLY VIDEO LINE DRIVER The EL8 and EL8 are wideband rail-to-rail output op amplifiers with large output current, excellent dg, dp, and low distortion that allow them to drive video signals in low supply applications. Figure 4 is the single supply non-inverting video line driver configuration and Figure is the inverting video line driver configuration. The signal is AC coupled by C. R and R are used to level shift the input and output to provide the largest output swing. R F and R G set the AC gain. C isolates the virtual ground potential. R T and R are the termination resistors for the line. C, C and C are selected big enough to minimize the droop of the luminance signal. FN74 Rev 7. Page of 4
EL8, EL8 V R F k V IN R T C 47µF R k R G k R k + - R F k C µf C 47µF R V IN R T C 47µF R k R k R G V - + V C µf C 47µF R FIGURE 4. V SINGLE SUPPLY NON INVERTING VIDEO LINE DRIVER FIGURE. SINGLE SUPPLY INVERTING VIDEO LINE DRIVER NORMALIZED GAIN (db) 4 A V = - A V = - - - -4 - -6 K M M M M FIGURE 6. VIDEO LINE DRIVER FREQUENCY RESPONSE FN74 Rev 7. Page of 4
EL8, EL8 Small Outline Package Family (SO) A D h X 4 N (N/)+ E E PIN # I.D. MARK c A SEE DETAIL X B. M C A B (N/) L C e H A SEATING PLANE GAUGE PLANE..4 C. M C A B b A DETAIL X L 4 ±4 MDP7 SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SO6 SO6 (. ) SO SO4 SO8 SYMBOL SO-8 SO-4 (. ) (SOL-6) (SOL-) (SOL-4) (SOL-8) TOLERANCE NOTES A.68.68.68.4.4.4.4 MAX - A.6.6.6.7.7.7.7. - A.7.7.7.9.9.9.9. - b.7.7.7.7.7.7.7. - c.9.9.9..... - D.9.4.9.46.4.66.74.4, E.6.6.6.46.46.46.46.8 - E.4.4.4.9.9.9.9.4, e....... Basic - L........9 - L.4.4.4.6.6.6.6 Basic - h....... Reference - N 8 4 6 6 4 8 Reference - Rev. M /7 NOTES:. Plastic or metal protrusions of.6 maximum per side are not included.. Plastic interlead protrusions of. maximum per side are not included.. Dimensions D and E are measured at Datum Plane H. 4. Dimensioning and tolerancing per ASME Y4.M-994 FN74 Rev 7. Page of 4
EL8, EL8 SOT- Package Family. C D X C E SEATING PLANE. C NX e N. C A-B X (L) A 6 e 4 B. M C A-B D b NX D H E A D. C X A MDP8 SOT- PACKAGE FAMILY MILLIMETERS SYMBOL SOT- SOT-6 TOLERANCE A.4.4 MAX A.. ±. A.4.4 ±. b.4.4 ±. c.4.4 ±.6 D.9.9 Basic E.8.8 Basic E.6.6 Basic e.9.9 Basic e.9.9 Basic L.4.4 ±. L.6.6 Reference N 6 Reference Rev. F /7 NOTES:. Plastic or metal protrusions of.mm maximum per side are not included.. Plastic interlead protrusions of.mm maximum per side are not included.. This dimension is measured at Datum Plane H. 4. Dimensioning and tolerancing per ASME Y4.M-994.. Index area - Pin # I.D. will be located within the indicated zone (SOT-6 only). 6. SOT- version has no center lead (shown as a dashed line). A GAUGE PLANE. c L + - Copyright Intersil Americas LLC -7. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN74 Rev 7. Page 4 of 4