Session 10: Solid State Physics MOSFET 1
Outline A B C D E F G H I J 2
MOSCap MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor: Al (metal) SiO2 (oxide) High k ~0.1 ~5 A SiO2 A n+ n+ p-type Si (bulk) p Drift current flowing between 2 doped regions ( source & drain ) is modulated by varying the voltage on the gate electrode. 3
MOSFET GATE LENGTH, L g OXIDE THICKNESS, T ox Gate Desired characteristics: High ON current Low OFF current Source Substrate Drain CURRENT V T Intel s 32nm CMOSFETs GATE VOLTAGE 4
N-channel vs. P-channel NMOS N+ poly-si PMOS P+ poly-si N+ N+ P+ P+ p-type Si n-type Si For current to flow, V GS > V T Enhancement mode: V T > 0 Depletion mode: V T < 0 Transistor is ON when V G =0V For current to flow, V GS < V T Enhancement mode: V T < 0 Depletion mode: V T > 0 Transistor is ON when V G =0V 5
CMOS Devices and Circuits CIRCUIT SYMBOLS N-channel MOSFET P-channel MOSFET CMOS INVERTER CIRCUIT V DD S V OUT INVERTER LOGIC SYMBOL D V DD V IN D V OUT GND S 0 V DD V IN When V G = V DD, the NMOSFET is on and the PMOSFET is off. When V G = 0, the PMOSFET is on and the NMOSFET is off. 6
Pull-Down and Pull-Up Devices In CMOS logic gates, NMOSFETs are used to connect the output to GND, whereas PMOSFETs are used to connect the output to VDD. An NMOSFET functions as a pull-down devicewhen it is turned on (gate voltage = V DD ) A PMOSFET functions as a pull-up devicewhen it is turned on (gate voltage = GND) V DD input signals A 1 A 2 A N A 1 A 2 A N Pull-up network Pull-down network PMOSFETs only F(A 1, A 2,, A N ) NMOSFETs only 7
CMOS NAND / NOR Gate NAND V DD NOR V DD A B A A B F A B F 0 0 1 0 1 1 1 0 1 1 1 0 B B A F A B F 0 0 1 0 1 0 1 0 0 1 1 0 8
Qualitative Theory of the NMOSFET SiO2 A A n+ n+ 0 0 p The potential barrier to electron flow from the source into the channel region is lowered by applying V GS > V T 9
Qualitative Theory of the NMOSFET n+ n+ p n+ n+ 0 Inversion-layer channel is formed p 0 n+ n+ 0 Electrons flow from the source to the drain by drift, when V DS >0. (I DS > 0) The channel potential ( ) varies from V S at the source end to V D at the drain end. p 10
Qualitative Theory of the NMOSFET n+ n+ p Inversion-layer channel is formed Electrons flow from the source to the drain by drift, when V DS >0. (I DS > 0) The channel potential ( ) varies from V S at the source end to V D at the drain end. 11
MOSFET I-V Curve n+ 0 n+ p 2 1 2 2 12
MOSFET I-V Curve 2 1 2 2 2 Depletion Region Approximation: but 0 0 2 2 2 0 0 0 13
MOSFET I-V Curve 0 Simply call 0 as 0 0 14
MOSFET I-V Curve 2 Linear Saturation Linear Saturation 15
Field-Effect Mobility, µ eff Effective vertical electric filed in the inversion layer for NMOS Scattering mechanisms: Coulombic scattering phonon scattering surface roughness scattering Effective vertical electric filed in the inversion layer for PMOS 16
MOSFET Saturation Region of Operation n+ n+ n+ n+ p ~ p As V D is increased above V G -V T, the length of the pinch-off region increases. The voltage applied across the inversion layer is always V Dsat =V GS -V T, and so the current saturates. If is significant compared to L, then I DS will increase slightly with increasing V DS >V Dsat, due to channel-length modulation 17
Square Law Theory? 2 Depletion Region Approximation: but 0 Linear Saturation n+ n+ 2 2 2 1 0 p 2 2 0 0 18
Modified (Bulk-Charge) I-V Model Linear Saturation Linear Linear 1 Bulk charge factor 1 1 3 Typically 1.1 1.4 Saturation Saturation 2 1 2 19
The Body Effect Note thatv T is a function ofv SB : 2 1 2 2 1 2 2 2 2 2 where is the body effect parameter 1 2 When the source-body pnjunction is reverse-biased, V T is increased. Usually, we want to minimizeg so that I Dsat will be the same for all transistors in a circuit. 20
The Body Effect NAND A B V DD A B F 0 0 1 0 1 1 1 0 1 1 1 0 A B 1 F 0 21
λ: Channel Length Modulation Parameter 1 1 1 n+ n+ p ~ 1 2 1 22
MOSFET: Small Signal Model 2 cut-off frequency: 2 1 23
Sub-Threshold Current 0 0 0 0 24
Sub-Threshold Current 1 Similarly: log 1 1 3 ln 10 1 1 ln 0 60 retrograde lowtemperature 0 25
P-Channel MOSFET The PMOSFET turns on when V GS < V T Holes flow from SOURCE to DRAIN DRAIN is biased at a lowerpotential than the SOURCE V S V G GATE V D P + P + N I D V DS < 0 I DS < 0 I DS increases with V GS -V T V DS (linear region) V B In a CMOS technology, the PMOS & NMOS threshold voltages are usually symmetric about 0, i.e. V Tp = -V Tn 26
PMOSFET I-V Saturation Linear 0 Linear bulk-charge factor Saturation 1 1 3 2 27
CMOS Inverter: Intuitive Perspective CIRCUIT SWITCH MODELS V DD V DD V DD G S R p D V OUT = 0V V OUT = V DD V IN D V OUT G S R n Low static power consumption, since one MOSFET is always off in steady state V IN = V DD V IN = 0V 28
Voltage Transfer Characteristic V OUT N: sat P: sat V DD V DD N: off P: lin C G S D N: sat P: lin V IN G D S V OUT A B D E N: lin P: sat 0 0 N: lin P: off V DD V IN 29
CMOS Inverter Load-Line Analysis I Dn =-I Dp V IN = V DD + V GSp V OUT = V DD + V DSp increasing V IN V IN = 0 V V IN = V DD V IN V DD V DSp =V OUT -V D + V OUT I Dn =-I Dp increasing V IN 0 0 V DSp = - V DD V DD V DSp = 0 V OUT =V DSn 30
Load-Line Analysis: Region A V DD I Dn =-I Dp V IN V Tn V IN V DSp =V OUT -V D + V OUT I Dn =-I Dp 0 0 V DD V OUT =V DSn 31
Load-Line Analysis: Region B I Dn =-I Dp V IN V DD V DSp =V OUT -V D + V OUT V DD /2 /2 > V IN > V Tn IN Tn I Dn =-I Dp 0 0 V DD V OUT =V DSn 32
Load-Line Analysis: Region D I Dn =-I Dp V DD DD V Tp > V IN > V DD /2 Tp IN DD V IN V DD V DSp =V OUT -V D + V OUT I Dn =-I Dp 0 0 V DD V OUT =V DSn 33
Load-Line Analysis: Region E V DD I Dn =-I Dp V IN > V DD V Tp V IN V DSp =V OUT -V D + V OUT I Dn =-I Dp 0 0 V DD V OUT =V DSn 34
MOSFET Scaling MOSFETs have been steadily miniaturized over time 1970s: ~ 10 mm Today: ~30 nm Reasons: Improved circuit operating speed Increased device density --> lower cost per function As MOSFET lateral dimensions (e.g. channel length L) are reduced: I Dsat increases decreased effective R gate and junction areas decrease decreased load C faster charging/discharging (i.e. t d is decreased) Intrinsic Delay 35
Velocity Saturation Velocity saturation limits I Dsat in sub-micron MOSFETS Simple model: 1 / 10 8 10 7 10 6 Carrier velocity vs. electric field GaAs Si electrons holes 2 10 5 10 2 10 3 10 4 10 5 10 6 / 8 10 for in Si 6 10 for in Si If : 1 36
MOSFET I-V with Velocity Saturation In linear region: 1 1 1 MOSFET is Long channel if 1 1 Linear Saturation Long Channel 1.8, 3, 0.25, 45 µ eff =200 cm 2 V 1 s 1,m= 1 + 3T oxe /W T = 1.2 E sat = 2v sat / µ eff = 8 10 4 V/cm 10 1.3 1 1.1 100 0.5 30 0.2 Short Channel 37
I Dsat with Velocity Saturation In saturation region: 2 1 1 Very short channel length: 2 is proportional to rather than is not dependent on To improve modern MOSFETs: high-k dielectric strained Si 38
Short- vs. Long-Channel NMOSFET Short-channel NMOSFET: I Dsat is proportional to V GS -V Tn rather than (V GS -V Tn ) 2 V Dsat is lower than for long-channel MOSFET Channel-length modulation is apparent 39
Velocity Overshoot When L is comparable to or less than the mean free path, some of the electrons travel through the channel without experiencing a single scattering event projectile-like motion ( ballistic transport ) 40
The Short Channel Effect (SCE) roll-off 0.6 0.125 decreases with L Effect is exacerbated by high values of 0.4 0.2 4 0 2 4 6 This effect is undesirable (i.e. we want to minimize it!) because circuit designers would like VT to be invariant with transistor dimensions and bias condition 41
Qualitative Explanation of SCE Before an inversion layer forms beneath the gate, the surface of the Si underneath the gate must be depleted (to a depth ) The source & drain pnjunctions assist in depleting the Si underneath the gate. Portions of the depletion charge in the channel region are balanced by charge in S/D regions, rather than by charge on the gate. Less gate charge is required to invert the semiconductor surface (i.e. decreases) n+ n+ 2 Large L: p depletion region Depletion charge supported by S/D Small L: 42
V T Roll-Off: First-Order Model n+ n+ 2 p 1 2 2 1 2 1 1 2 1 Minimize by reducing reducing increasing (trade-offs: degraded, ) MOSFET vertical dimensions should be scaled along with horizontal dimensions! 43
MOSFET Scaling: Constant-Field Approach MOSFET dimensions and the operating voltage ( ) each are scaled by the same factor 1, so that the electric field remains unchanged. Original device Scaled device n+ n+ p / n+ n+ / / p 44
Constant-Field Scaling Benefits Scaling assumptions Derived scaling behavior of device parameters Derived scaling behavior of circuit parameters Parameter Device dimensions (,,, ) Doping concentration (, ) Voltage () Multiplication factor (k>1) 1 1 Electric field () 1 Carrier velocity () 1 Depletion-layerwidth ( ) 1 Capacitance ( ) 1 Inversion charge density ( ) 1 Current drift () 1 Channelresistance ( ) 1 Circuit delay time (~ ) 1 Power diss. per circuit (~) Power-delay product per circuit () 1 1 Circuitdensity ( 1 ) Power density ( ) 1 45
Failure of Constant-Field Scaling Since cannot be scaled down aggressively, the operating voltage ( ) has not been scaled down in proportion to the MOSFET channel length: Feature Size () Power-Supply Voltage () Gate Oxide Thickness () Oxide Field ( ) 2 5 350 104 1.2 5 250 0 0.8 5 180 8 0.5 3 120 8 0.35 3 100 3 0.25 5 70 6 46
MOSFET Scaling: Generalized Approach Scaling assumptions Derived scaling behavior of device parameters Derived scaling behavior of circuit parameters Parameter Device dimensions (,,, ) Doping concentration (, ) Voltage () Electric field () Depletion-layerwidth ( ) Multiplicationfactor (k>1) 1 1 Capacitance ( ) 1 Inversion charge density ( ) Long ch. Vel Sat. Carrier velocity () 1 Current drift () Circuit delay time (~ ) 1 1 Power diss. per circuit (~) Power-delay product per circuit () Circuitdensity ( 1 ) Power density ( ) Electric field intensity increases by a factor 1 must be scaled up by to suppress shortchannel effects 47
Drain Induced Barrier Lowering (DIBL) As the source and drain get closer, they become electrostatically coupled, so that the drain bias can affect the potential barrier to carrier diffusion at the source junction V T decreases (i.e. OFF state leakage current increases) ln 3 Long 50 100 3 10 Short 48
Punchthrough A large drain bias can cause the drain-junction depletion region to merge with the source-junction depletion region, forming a sub-surface path for current conduction. I Dsat increases rapidly with V DS This can be mitigated by doping the semiconductor more heavily in the subsurface region, i.e. using a retrograde doping profile. n+ n+ p 49
Source and Drain (S/D) Structure To minimize the short channel effect and DIBL, we want shallow (small r j ) S/D regions but the parasitic resistance of these regions increases when r j is reduced., where = resistivity of the S/D regions Shallow S/D extensions may be used to effectively reduce r j with a relatively small increase in parasitic resistance n+ n n n+ p
E - Field Distribution Along the Channel The lateral electric field peaks at the drain end of the channel. can be as high as 10 6 V/cm High E-field causes problems: Damage to oxide interface & bulk (trapped oxide charge V T shift) substrate current due to impact ionization:
Lightly Doped Drain (LDD) Structure Lower pn junction doping results in lower peak E-field Hot-carrier effects are reduced Parasitic resistance is increased
Parasitic Source-Drain Resistance G S R S R D D For short-channel MOSFET, I Dsat0 V GS V T, so that I Dsat is reduced by ~15% in a 0.1 mm MOSFET. V Dsat is increased tov Dsat0 +I Dsat (R S + R D ) 1
Summary: MOSFET OFF State vs. ON State OFF state ( ): is limited by the rate at which carriers diffuse across the source pn junction Minimum subthreshold swing S, and DIBL are issues ON state ( ): is limited by the rate at which carriers drift across the channel Punchthrough is of concern at high drain bias increases rapidly with Parasitic resistances reduce drive current source resistance reduces effective source & drain resistances & reduce effective 54