ROCHESER INSIUE OF ECHNOLOGY MICROELECRONIC ENGINEERING PMOS esting at Dr. Lynn Fuller webpage: http://www.rit.edu/~lffeee 82 Lomb Memorial Drive Rochester, NY 14623-5604 el (585) 475-2035 Fax (585) 475-5041 email: LFFEEE@rit.edu MicroE webpage: http://www.microe.rit.edu Revised 1-20-2017 pmostest.ppt Page 1
OULINE est Chip est Equipment Resistive Structures ransistors Integrated Circuits Ring Oscillator Digital Circuits Shortcourse: Chip Size = 7mm x 7mm 20 rows and 21 columns Page 2
Alignment Marks CD Linewidth, Overlay Van Der Pauw, p+ DS, Metal MOSFE s, Inverters Ring Oscillator CBKR Digital Circuits HE ES CHIP Page 3
PMOS ES CHIP Page 4
ES FACILIY HP4145 Semiconductor Paramater Analyzer Keithley 7001 Switch Matrix Computer ICS Software Camera Ultracision Semi-Automatic Wafer Prober est Fixture and Manual Probe Station Page 5
ES EQUIPMEN Semi-automatic Prober Automatic Prober Page 6
ES EQUIPMEN Manual Prober Page 7
RESISOR ES RESULS R = Rhos L/W L/W = 400/60 R = V/I = 1/slope = 647 W Page 8
VAN DER PAUW ES SRUCURES FOR SHEE RESISANCE I I Rs V1-V2 V1 V2 I I I Rs = (V1-V2) I ln 2 V1 V2 Page 9
VAN DER PAUW ES RESULS 26.4 Ohms Page 10
CBKR AND INVERERS Page 11
CROSS BRIDGE KELVIN RESISANCE ES SRUCURES FOR CONAC RESISANCES Gc V1-V2 V1 I W1 W2 V2 I I Rc = (V1-V2) I ohms Gc = I 1 (V1-V2) W1 x W2 mhos/µm 2 Page 12
500 µm PMOS esting at RI MEAL AND DIFFUSION SERPENINE 100 µm Line width = 15 µm Line Space = 30 µm L/W = 269 Area Covered by metal = 62050 µm 2 R = Rhos L/W Defect density ( in #/cm 2 ) = (# defective x 1612) / (# tested) Page 13
PMOS RANSISORS Layout Photograph Page 14
PMOS RANSISOR ES RESULS Vds + G Vgs - D S Id Page 15
RANSISOR LINEAR REGION V, GM + Vgs - -Id G gm S D Vto Id Vsub Vd = -0.1 Volt Vsub = 0 Body Effect Vsub -1-2 -3 volts -Vg gm = DId/DVg -Ids Non Saturation Region S p G Vsub pmosfe with Vt=-1, since the Drain is at -0.1 volts and the source is at zero. Both drain and source will be on at gate voltages greater than -1.1 volt. the transistor will be in the non saturation region. D -5-4 -3-2 p n Vgs -Vds Page 16
LINEAR REGION ES RESULS Page 17
RANSISOR SAURAION REGION V, GM -Id G S D gm Id Vto + Vgs=Vds - Vsub Vsub = 0-1 -2-3 volts -Vg gm = DId/DVg Body Effect PMOS -Ids S p Saturation Region -5-4 Vgs -3-2 G Vsub -Vds pmosfe with Vt=-1, Drain end is never on because Voltage Gate to Drain is Zero. herefore this transistor is always in Saturation Region if the gate voltage is above the threshold voltage. D p n Page 18
RANSISOR SUB HRESHOLD ID-VGS G S D Id + Vgs=Vds - 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 Id (Amps) Lights On Sub Vt Slope (mv/dec) 10-11 10-12 Vgs Vt he subthreshold characteristics are important in VLSI circuits because when the transistors are off they should not carry much current since there are so many transistors. (typical value about 100 mv/decade) Page 19
INVERERS L = 40µm W = 20µm L = 20µm W = 50µm Page 20
INVERERS VIN Inverter Gain = VOU Wd/Ld Wu/Lu -V Voh VOU Slope = Gain -V VIN VOU VoL 0 0 ViL Vih -V VIN PMOS Inverter with Enhancement Load D 0 noise margin = ViL - Voh D 1 noise margin = Voh - Vih Page 21
INVERER ES RESULS Gain = -2.64 Page 22
RING OSCILLAOR, td Seven stage ring oscillator with two output buffers td = / 2 N td = gate delay N = number of stages = period of oscillation Vout Vout = period of oscillation Page 23
9 SAGE RING OSCILLAOR Vcc Gnd Out Page 24
RING OSCILLAOR OUPU 500ns td = / 2n = 500 ns / 2 / 9 = 28 ns Page 25
DIGIAL CIRCUI ESING Page 26
LAB VIEW SOFWARE Page 27
HARDWARE FOR OUPU 6 Analog Outputs Ribbon Cable erminal Board Page 28
HARDWARE FOR INPU 16 Analog Inputs Ribbon Cable erminal Board Page 29
FINAL SYSEM Page 30
CUSOM SOFWARE INERFACE Click on digital testing icon to invoke the lab view software and this main menu. Click to select the type of test you wish to run. MAIN MENU Page 31
NOR GAE AND NOR FLIP FLOP PMOS 2 INPU NOR PMOS NOR RS Flip Flop Page 32
ESING WO INPU ONE OUPU LOGIC GAES Page 33
FOUR CHOICES FOR SUPPLY VOLAGES CLICK O SELEC ONE CMOS/L Vcc = +5 Volts Page 34
PROBE CARD/WIRE CONNECIONS 18 16 14 12 10 8 20 22 24 2 4 6 Page 35
SWICH MARIX (MANUAL) Wire #17 Supply Outputs Vcc -V Gnd a b c d e f Inputs a b c d e f Wire #8 Page 36
RUN ES Click to Select When Output is High or Low Click to Start est Stop est est Results For Xor Gate Page 37
PMOS INVERER GAIN=4 Page 38
PMOS 2-INPU NOR est for PMOS wo Input NOR, Gain = 4 or 8 Page 39
PMOS 2-INPU XOR Page 40
WAFER MAPS FOR MESA nmos Vt target +1 000000000000000 000050505050000 000000000000000 005060507050700 000000000000000 004040304030300 000000000000000 004040404040400 000000000000000 004050405090600 000000000000000 005050606060700 000000000000000 000050505050000 000000000000000 Row 1 Row 15 Col 1 Col 15 row 1 is the first row in which a full die is located column 1 is the first column in which a full die is locatedd Page 41
WAFER MAPS FOR MESA Code 0 no die 1 value<(arget-40%) 2 (arget-40%)<value<(arget-30%) 3 (arget-30%)<value<(arget-20%) 4 (arget-20%)<value<(arget-10%) 5 (arget-10%)<value<(arget+10%) 6 (arget+10%)<value<(arget+20%) 7 (arget+20%)<value<(arget+30%) 8 (arget+30%)<value<(arget+40%) 9 (arget+40%)<value Page 42
WAFER MAP Example: Given a wafer with test chips located as shown and nmos threshold voltage data encoded and stored in MESA as shown. Reconstruct a wafer map using EXCELL spreadsheet. Page 43
FUURE WORK More Automation Improved Wafer Mapping More Complete esting Page 44
CONCLUSION A test specification has been developed A history data base has been developed esting is very time consuming. It takes us 9 hours to do all the specified tests and even then we only test a few devices on a wafer. Currently we test about 1% of the devices Page 45
REFERENCES 1. LabView Software, National Instruments, http://www.natinst.com Page 46
REVIEW QUESIONS - PMOS ES SPECIFICAION 1. How is Vt and gm found from the transistor family of curves. 2. Is the Vt and gm the same in the non-saturation region as in the saturation region? 3. What is the significance of the sub-threshold slope. What is the difference between sub-threshold slope and subthreshold swing? 4. What is the significance of the noise margin. 5. What is the purpose of the ring oscillator test structure. Page 47
MUX LAYOU AND GAE LEVEL SCHEMAIC 25 ransistors I 0 A A A B I 0 I 1 A BI 1 Q I 2 I 3 B B AB I 2 ABI 3 Page 48
PMOS 4-INPU MULIPLEXER Page 49
MUX ES RESULS A B I3 I2 I1 I0 A B I3 I2 I1 I0 In PMOS logic low is 0 volts, logic high is -Vcc A B I3 I2 I1 I0 A B I3 I2 I1 I0 Page 50
MUX ES RESULS A B I3 I2 I1 I0 A B I3 I2 I1 I0 In PMOS logic low is 0 volts, logic high is -Vcc A B I3 I2 I1 I0 A B I3 I2 I1 I0 Page 51
PMOS FULL ADDER Page 52
PMOS CLOCKED DAA LACH Page 53
PMOS ANALOG MUX Page 54