ACPL-MT Automotive Intelligent Power Module with R 2 Coupler Isolation and Small Outline, Lead Package Data Sheet Lead (Pb) Free RoHS fully compliant RoHS fully compliant options available; -xxxe denotes a lead-free product Description The ACPL-MT consists of a AlGaAs optically coupled to an integrated high gain photo detector. Minimized propagation delay difference between devices make these optocouplers excellent solutions for improving automotive inverter efficiency through reduced switching dead time. Specification and performance plots are given for typical IPM applications. Avago R 2 Coupler isolation products provide the reinforced insulation and reliability needed for critical in automotive and high temperature industrial applications. Schematic Diagram ANODE CATHODE Truth Table LED ON OFF V O L H The connection of a 0. μf bypass capacitor between pins and is recommended. V CC V OUT GND Features Performance specified for common IPM applications over automotive temperature range: -0 C to 2 C Fast maximum propagation delays - t PHL & t PLH = 0 ns Minimized Pulse Width Distortion (PWD = 70 ns) Very high Common Mode Rejection (CMR): kv/μs at V CM = 00 V CTR > % at I F = 0 ma Qualified to AEC-Q00 Test Guidelines Safety approval - UL recognized per UL77 (file no. E) 000 V rms for minute - IEC/EN/DIN EN 077--2 Approved - CSA Approved Applications Automotive IPM isolation for battery management system and motor control Isolated IGBT/MOSFET gate drive AC and brushless dc motor drives Industrial inverters for power supplies and motor controls CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.
Ordering Information Part Number Option (RoHS) Compliant Package Surface Mount Tape & Reel IEC/EN/DIN EN 077--2 Quantity ACPL-MT -000E SO- X 00 per tube -00E X X 00 per tube -00E X X 00 per reel -0E X X X 00 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example : ACPL-MT-00E to order product of SO- Surface Mount package in Tape and Reel packaging with RoHS compliant. Example 2: ACPL-MT-000E to order product of SO- Surface Mount package in tube packaging with RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Package Outline Drawing ACPL-MT-000E Small Outline SO- Package (JEDEC MO-) Land Pattern Recommendation. (0.7). ± 0. (0.7 ± 0.00) MT YWW EE 7.0 ± 0.2 (0.27 ± 0.008) 0. ± 0.0 (0.0 ± 0.002) Extended Datecode for lot tracking 2. (0.0) 2.0 (0.080) 8.27 (0.2). (0.0) 0. (0.02). ± 0.* (0.2 ± 0.00) DIMENSION IN MILLIMETERS (INCHES) 2. ± 0. (0.098 ± 0.00) 0.02 ± 0.02 (0.00 ± 0.00) 0.20 ± 0.02 (0.008 ± 0.00).27 (0.00) BSC 0.7 (0.028) MIN 7 MAX. DIMENSIONS IN MILLIMETERS (INCHES) * MAXIMUM MOLD FLASH ON EACH SIDE IS 0. mm (0.00) NOTE: FLOATING LEAD PROTRUSION IS 0. mm ( mils) MAX. MAX. LEAD COPLANARITY = 0.02 (0.00) 2
Recommended Pb-Free IR Profile Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Note: Non-halide flux should be used Regulatory Information The ACPL-MT is approved by the following organizations: UL Approved under UL 77, component recognition program up to V ISO = 000 V RMS CSA Approved under CSA Component Acceptance Notice #. IEC/EN/DIN EN 077--2 Approved under: IEC 077--2:2007 EN 077--2:200 + A DIN EN 077--2 (VDE 088 Teil 2) IEC/EN/DIN EN 077--2 Insulation Characteristics* Description Symbol Characteristic Unit Installation classification per DIN VDE 00/.89, Table for rated mains voltage 0 V rms for rated mains voltage 00 Vrms for rated mains voltage 00 V rms Climatic Classification /2/2 Pollution Degree (DIN VDE 00/.89) 2 Maximum Working Insulation Voltage V IORM 7 V peak Input to Output Test Voltage, Method b* V IORM x.87=v PR, 00% Production Test with t m = sec, Partial discharge < pc V PR 0 V peak Input to Output Test Voltage, Method a* V IORM x.=v PR, Type and Sample Test, t m =0 sec, Partial discharge < pc I IV I III I II V PR 907 V peak Highest Allowable Overvoltage (Transient Overvoltage t ini = 0 sec) V IOTM 000 V peak Safety-limiting values maximum values allowed in the event of a failure. Case Temperature Input Current Output Power T S I S, INPUT P S, OUTPUT Insulation Resistance at T S, V IO = 00 V R S >09 W * Refer to the optocoupler section of the Isolation and Control Components Designer s Catalog, under Product Safety Regulations section, (IEC/ EN/DIN EN 077--2) for a detailed description of Method a and Method b partial discharge test profiles. 7 20 00 C ma mw
Insulation Related Specifications Parameter Symbol Value Units Conditions Minimum External Air Gap L(0) mm Measured from input terminals to output (Clearance) terminals, shortest distance through air. Minimum External Tracking L(02) mm Measured from input terminals to output (Creepage) terminals, shortest distance path along body. Minimum Internal Plastic Gap 0.08 mm Through insulation distance conductor to (Internal Clearance) conductor, usually the straight line distance thickness between the emitter and detector. Tracking Resistance CTI 200 Volts DIN IEC 2/VDE 00 Part (ComparativeTracking Index) Isolation Group IIIa Material Group (DIN VDE 00) Absolute Maximum Ratings Parameter Symbol Min. Max. Units Storage Temperature T S - 0 C Operating Temperature T A -0 2 C Average Input Current I F(avg) 20 ma Peak Input Current I F(peak) 0 ma (0% duty cycle, < ms pulse width) Peak Transient Input Current I F(tran).0 A (< μs pulse width, 00 pps) Reverse Input Voltage (Pin -) V R Volts Average Output Current (Pin ) I O(avg) ma Output Voltage (Pin -) V O -0. 0 Volts Supply Voltage (Pin -) V CC -0. 0 Volts Output Power Dissipation P O 00 mw Total Power Dissipation P T 0 mw Infrared and Vapor Phase Reflow Temperature See Reflow Thermal Profile below. Recommended Operating Conditions Parameter Symbol Min. Max. Units Power Supply Voltage V CC. 0 Volts Output Voltage V O 0 0 Volts Input Current (ON) I F(on) 0 20 ma Input Voltage (OFF) V F(off) - 0.8 V Operating Temperature T A -0 2 C
Electrical Specifications Over recommended operating conditions unless otherwise specified: T A = -0 C to +2 C, V CC = +. V to 0 V, I F(on) = 0 ma to 20 ma, V F(off) = - V to 0.8 V Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note Current Transfer Ratio CTR 90 % I F = 0 ma, V O = 0. V Low Level Output I OL. 9.0 ma I F = 0 ma, V O = 0. V 2, Current Low Level Output Voltage V OL 0. 0. V I O = 2. ma Input Threshold Current I TH..0 ma V O = 0.8 V, I O = 0.7 ma 2 High Level Output I OH 0 μa V F = 0.8 V Current High Level Supply Current I CCH 0.. ma V F = 0.8 V, V O = Open Low Level Supply Current I CCL 0.. ma I F = 0 ma, V O = Open Input Forward Voltage V F...7 V T A = 2 C, I F = 0 ma.2..8 V I F = 0 ma Temperature Coefficient ΔV F /ΔT A -. mv/ C I F = 0 ma of Forward Voltage Input Reverse Breakdown BV R V I R = 0 μa Voltage Input Capacitance C IN 90 pf f = MHz, V F = 0 V Input-Output V ISO 000 V RMS RH < 0%, t = min, 2, Insulation Voltage T A = 2 C Resistance (Input - Output) R I-O 0 Ω V I-O = 00 Vdc Capacitance C I-O 0. pf f = MHz (Input - Output) *All typical values at 2 C, V CC = V.
Switching Specifications (R L = ) Over recommended operating conditions unless otherwise specified: T A = -0 C to +2 C, V CC = +. V to 0 V, I F(on) = 0 ma to 20 ma, V F(off) = - V to 0.8 V Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note Propagation Delay t PHL 0 200 0 ns C L = 00 pf I F(on) = 0 ma,,, Time to Low V F(off) = 0.8 V, 8-2 Output Level 00 ns C L = 0 pf V CC =.0 V, Propagation Delay t PLH 270 00 0 ns C L = 00 pf V THLH = 2.0 V, Time to High Output Level 0 C L = 0 pf V THHL =. V Pulse Width PWD 200 0 ns C L = 00 pf 9 Distortion Propagation Delay t PLH -t PHL -0 200 0 ns Difference Between Any 2 Parts Output High Level CM H 0 kv/μs I F = 0 ma, V CC =.0 V, 7 7 Common Mode V O >.0 V C L = 00 pf, Transient Immunity V CM = 00 V P-P, Output Low Level CM L 0 kv/μs I F = 0 ma, T A = 2 C 8 Common Mode V O <.0 V Transient Immunity *All typical values at 2 C, V CC = V. Notes:. CURRENT TRANSFER RATIO in per cent is defined as the ratio of output collector current (I O ) to the forward LED input current (I F ) times 00. 2. Device considered a two-terminal device: Pins and shorted together and Pins, and shorted together.. In accordance with UL77, each optocoupler is proof tested by applying an insulation test voltage 800 V RMS for second.. Pulse: f = 20 khz, Duty Cycle = 0%.. Use of a 0. μf bypass capacitor connected between pins and can improve performance by filtering power supply line noise.. The difference between t PLH and t PHL between any two parts under the same test condition. (See IPM Dead Time and Propagation Delay Specifications section.) 7. Common mode transient immunity in a Logic High level is the maximum tolerable dv CM /dt of the common mode pulse, V CM, to assure that the output will remain in a Logic High state (i.e., V O >.0 V). 8. Common mode transient immunity in a Logic Low level is the maximum tolerable dv CM /dt of the common mode pulse, V CM, to assure that the output will remain in a Logic Low state (i.e., V O <.0 V). 9. Pulse Width Distortion (PWD) is defined as t PHL - t PLH for any given device.
LED Drive Circuit Considerations For Ultra High CMR Performance Without a detector shield, the dominant cause of optocoupler CMR failure is capacitive coupling from the input side of the optocoupler, through the package, to the detector IC as shown in Figure. The ACPL-MT improves CMR performance by using a detector IC with an optically transparent Faraday shield, which diverts the capacitively coupled current away from the sensitive IC circuitry. However, this shield does not eliminate the capacitive coupling between the LED and the optocoupler output pin and output ground as shown in Figure. This capacitive coupling causes perturbations in the LED current during common mode transients and becomes the major source of CMR failures for a shielded optocoupler. The main design objective of a high CMR LED drive circuit becomes keeping the LED in the proper state (on or off) during common mode transients. For example, the recommended application circuit (Figure ), can achieve kv/μs CMR while minimizing component complexity. Note that a CMOS gate is recommended in Figure to keep the LED off when the gate is in the high state. Another cause of CMR failure for a shielded optocoupler is direct coupling to the optocoupler output pins through C LEDO in Figure. Many factors influence the effect and magnitude of the direct coupling including: the position of the LED current setting resistor and the value of the capacitor at the optocoupler output (C L ). Techniques to keep the LED in the proper state and minimize the effect of the direct coupling are discussed in the next two sections. CMR with the LED on (CMRL) A high CMR LED drive circuit must keep the LED on during common mode transients. This is achieved by overdriving the LED current beyond the input threshold so that it is not pulled below the threshold during a transient. The recommended minimum LED current of 0 ma provides adequate margin over the maximum I TH of.0 ma (see Figure 2) to achieve kv/μs CMR. The placement of the LED current setting resistor effects the ability of the drive circuit to keep the LED on during transients and interacts with the direct coupling to the optocoupler output. For example, the LED resistor in Figure is connected to the anode. Figure 7 shows the AC equivalent circuit for Figure during common mode transients. During a +dv CM /dt in Figure 7, the current available at the LED anode (Itotal) is limited by the series resistor. The LED current (I F ) is reduced from its DC value by an amount equal to the current that flows through C LEDP and C LEDO. The situation is made worse because the current through C LEDO has the effect of trying to pull the output high (toward a CMR failure) at the same time the LED current is being reduced. For this reason, the recommended LED drive circuit (Figure ) places the current setting resistor in series with the LED cathode. Figure 8 is the AC equivalent circuit for Figure during common mode transients. In this case, the LED current is not reduced during a +dv CM /dt transient because the current flowing through the package capacitance is supplied by the power supply. During a dv CM /dt transient, however, the LED current is reduced by the amount of current flowing through CLEDN. But, better CMR performance is achieved since the current flowing in C LEDO during a negative transient acts to keep the output low. CMR with the LED Off (CMRH) A high CMR LED drive circuit must keep the LED off (V F V F(OFF) ) during common mode transients. For example, during a +dv CM /dt transient in Figure 8, the current flowing through C LEDN is supplied by the parallel combination of the LED and series resistor. As long as the voltage developed across the resistor is less than V F(OFF) the LED will remain off and no common mode failure will occur. Even if the LED momentarily turns on, the 00 pf capacitor from pins - will keep the output from dipping below the threshold. The recommended LED drive circuit (Figure ) provides about 0 V of margin between the lowest optocoupler output voltage and a V IPM threshold during a kv/μs transient with V CM = 00 V. Additional margin can be obtained by adding a diode in parallel with the resistor, as shown by the dashed line connection in Figure 8, to clamp the voltage across the LED below V F(OFF). Since the open collector drive circuit, shown in Figure 9, cannot keep the LED off during a +dv CM /dt transient, it is not desirable for applications requiring ultra high CMRH performance. Figure 20 is the AC equivalent circuit for Figure 9 during common mode transients. Essentially all the current flowing through CLEDN during a +dv CM / dt transient must be supplied by the LED. CMRH failures can occur at dv/dt rates where the current through the LED and CLEDN exceeds the input threshold. Figure 2 is an alternative drive circuit which does achieve ultra high CMR performance by shunting the LED in the off state. 7
IPM Dead Time and Propagation Delay Specifications The ACPL-MT includes a Propagation Delay Difference specification intended to help designers minimize dead time in their power inverter designs. Dead time is the time period during which both the high and low side power transistors (Q and Q2 in Figure 22) are off. Any overlap in Q and Q2 conduction will result in large currents flowing through the power devices between the high and low voltage motor rails. To minimize dead time the designer must consider the propagation delay characteristics of the optocoupler as well as the characteristics of the IPM IGBT gate drive circuit. Considering only the delay characteristics of the optocoupler (the characteristics of the IPM IGBT gate drive circuit can be analyzed in the same way) it is important to know the minimum and maximum turn-on (t PHL ) and turn-off (t PLH ) propagation delay specifications, preferably over the desired operating temperature range. The limiting case of zero dead time occurs when the input to Q turns off at the same time that the input to Q2 turns on. This case determines the minimum delay between LED turn-off and LED turn-on, which is related to the worst case optocoupler propagation delay waveforms, as shown in Figure 2. A minimum dead time of zero is achieved in Figure 2 when the signal to turn on LED is delayed by (t PLH max - t PHL min ) from the LED turn off. Note that the propagation delays used to calculate PDD are taken at equal temperatures since the optocouplers under consideration are typically mounted in close proximity to each other. (Specifically, t PLH max and t PHL min in the previous equation are not the same as the t PLH max and t PHL min, over the full operating temperature range, specified in the data sheet.) This delay is the maximum value for the propagation delay difference specification which is specified at 70 ns for the ACPL-MT over an operating temperature range of -0 C to 2 C. Delaying the LED signal by the maximum propagation delay difference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. The maximum dead time occurs in the highly unlikely case where one optocoupler with the fastest t PLH and another with the slowest t PHL are in the same inverter leg. The maximum dead time in this case becomes the sum of the spread in the t PLH and t PHL propagation delays as shown in Figure 2. The maximum dead time is also equivalent to the difference between the maximum and minimum propagation delay difference specifications. The maximum dead time (due to the optocouplers) for the ACPL-MT is 20 ns (= 70 ns - (-0 ns)) over an operating temperature range of -0 C to 2 C. IO - OUTPUT CURRENT - ma 2 0 2 C 2 C 8-0 C V O =0.V 2 0 0 0 20 I F - FORWARD CURRENT - ma NORMALIZED OUTPUT CURRENT.0.00 0.9 0.90 0.8 I F = 0mA V O = 0.V 0.80-0 -20 0 20 0 0 80 00 20 0 T A - TEMPERATURE - C Figure 2. Typical Transfer Characteristics. Figure. Normalized Output Current vs. Temperature. 8
I OH - HIGH LEVEL OUTPUT CURRENT - ua 2.00.0.00 0.0 Figure. High Level Output Current vs. Temperature. V F =0.8V V CC = V O = 0V 0.00-0 -20 0 20 0 0 80 00 20 0 T A - TEMPERATURE - C I F - FORWARD CURRENT - ma 00.00 I F T A = 2 C 0.00 + V F.00 0.0 0.0.20.0.0.0.0 V F - FORWARD VOLTAGE - VOLTS Figure. Input Current vs. Forward Voltage. I F(ON) =0 ma I f + 0. µf C L * V OUT + V CC = V V O t f 90% 90% t r *TOTAL LOAD CAPACITANCE V THHL 0% 0% V THLH t PHL t PLH Figure. Propagation Delay Test Circuit. B I F A 0. µf V OUT 00 pf* V CC = V + V CM OV Δt δv δt = V CM Δt V FF + *00 pf TOTAL CAPACITANCE V O SWITCH AT A: I F = 0 ma V CC + V CM = 00 V V O SWITCH AT B: I F = 0 ma V OL Typical CMR Waveform. Figure 7. CMR Test Circuit. 9
T P - PROPOGATION DELAY - ns 00 00 00 200 I F = 0mA V CC = V C L = 00pF R L = 20kΩ 00 tplh tphl 0-0 -20 0 20 0 0 80 00 20 0 T A - TEMPERATURE - C t P PROPAGATION DELAY ns 800 00 00 200 I F = 0 ma V CC = V C L = 00 pf T A = 2 C tplh tphl 0 0 20 0 0 0 RL LOAD RESISTANCE KΩ Figure 8. Propagation Delay with External RL vs. Temperature. Figure 9. Propagation Delay vs. Load Resistance. t P PROPAGATION DELAY n 200 000 800 00 00 200 I F = 0 ma V CC = V R L = 20 KΩ T A = 2 C tplh tphl t P PROPAGATION DELAY ns 200 000 800 00 00 200 I F = 0 ma C L = 00 pf R L = T A = 2 C tplh tphl 0 0 00 200 00 00 00 CL LOAD CAPACITANCE pf Figure 0. Propagation Delay vs. Load Capacitance. 0 0 20 2 0 V CC SUPPLY VOLTAGE V Figure. Propagation Delay vs. Supply Voltage. 00 T P - PROPAGATION DELAY - ns 00 00 200 00 0 V CC = V C L = 00pF R L = 20kΩ T A = 2 C tplh tphl 0 20 I F - LED FORWARD CURRENT - ma Figure 2. Propagation Delay vs. Input Current. 0
+ V 0. μf VOUT V CC = V + C LEDP CMOS 0 W 00 pf *00 pf TOTAL CAPACITANCE C LEDN Figure. Recommended LED Drive Circuit. Figure. Optocoupler Input to Output Capacitance Model for Unshielded Optocouplers. + V C LEDP C LED0 0 Ω 0. μf VOUT V CC = V + 00 pf C LEDN CMOS *00 pf TOTAL CAPACITANCE Figure. Optocoupler Input to Output Capacitance Model for Shielded Optocouplers. Figure. LED Drive Circuit with Resistor Connected to LED Anode (Not Recommended). I TOTAL* 00 Ω IF I CLEDP I CLED0 C LED0 V OUT + VR** C LEDP C LED0 V OUT C LEDN 00 pf 00 Ω C LEDN I CLEDN* 00 pf * THE ARROWS INDICATE THE DIRECTION OF CURRENT FLOW FOR +dv CM /dt TRANSIENTS. + V CM * THE ARROWS INDICATE THE DIRECTION OF CURRENT FLOW FOR +dv CM /dt TRANSIENTS. ** OPTIONAL CLAMPING DIODE FOR IMPROVED CMH PERFORMANCE. V R < V F (OFF) DURING +dv CM /dt. + V CM Figure 7. AC Equivalent Circuit for Figure during Common Mode Transients. Figure 8. AC Equivalent Circuit for Figure during Common Mode Transients.
+ V C LEDP C LED0 V OUT Q Q I CLEDN* C LEDN 00 pf * THE ARROWS INDICATE THE DIRECTION OF CURRENT FLOW FOR +dv CM /dt TRANSIENTS. + V CM Figure 9. Not Recommended Open Collector LED Drive Circuit. Figure 20. AC Equivalent Circuit for Figure 9 during Common Mode Transients. + V Figure 2. Recommended LED Drive Circuit for Ultra High CMR. I LED + V 0 Ω CMOS ACPL-MT V CC 0. μf VOUT Q IPM +HV M I LED2 + V 0 Ω CMOS ACPL-MT V CC2 0. μf VOUT2 ACPL-MT ACPL-MT ACPL-MT ACPL-MT ACPL-MT Q2 -HV Figure 22. Typical Application Circuit. 2
I LED I LED V OUT V OUT2 Q ON Q2 OFF Q OFF Q2 ON V OUT V OUT2 Q ON Q2 OFF Q OFF Q2 ON I LED2 t PLH MAX. t PHL MIN. PDD* MAX. = (t PLH- t PHL ) MAX. = t PLH MAX. - t PHL MIN. *PDD = PROPAGATION DELAY DIFFERENCE NOTE: THE PROPAGATION DELAYS USED TO CALCULATE PDD ARE TAKEN AT EQUAL TEMPERATURES. Figure 2. Minimum LED Skew for Zero Dead Time. I LED2 t PLH MIN. t PLH MAX. PDD* MAX. t PHL MIN. t PHL MAX. MAX. DEAD TIME MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER) = (t PLH MAX. - t PLH MIN. ) + (t PHL MAX. - t PHL MIN. ) = (t PLH MAX. - t PHL MIN. ) - (t PLH MIN. - t PHL MAX. ) = PDD* MAX. - PDD* MIN. *PDD = PROPAGATION DELAY DIFFERENCE NOTE: THE PROPAGATION DELAYS USED TO CALCULATE THE MAXIMUM DEAD TIME ARE TAKEN AT EQUAL TEMPERATURES. Figure 2. Waveforms for Deadtime Calculation. For product information and a complete list of distributors, please go to our website: www.avagotech.com Avago, Avago Technologies, the A logo and R 2 Coupler are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright 200-20 Avago Technologies. All rights reserved. Obsoletes 989-28EN AV02-0822EN - December, 20