l Ultra Low OnResistance l PChannel l Surface Mount (IRFR54) l Straight Lead (IRFU54) l Advanced Process Technology l Fast Switching G l Fully Avalanche Rated l LeadFree Description Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve extremely low onresistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. The DPak is designed for surface mounting using vapor phase, infrared, or wave soldering techniques. The straight lead version (IRFU series) is for throughhole mounting applications. Power dissipation levels up to.5 watts are possible in typical surface mount applications. IRFR54PbF IRFU54PbF HEXFET Power MOSFET D S DPak TO252AA V DSS = 0V R DS(on) = 0.205Ω I D = 3A IPak TO25AA PD 9534A Absolute Maximum Ratings Parameter Max. Units I D @ T C = 25 C Continuous Drain Current, V GS @ V 3 I D @ T C = 0 C Continuous Drain Current, V GS @ V 8.2 A I DM Pulsed Drain Current 52 P D @T C = 25 C Power Dissipation 66 W Linear Derating Factor 0.53 W/ C V GS GatetoSource Voltage ± 20 V E AS Single Pulse Avalanche Energy 94 mj I AR Avalanche Current 8.4 A E AR Repetitive Avalanche Energy 6.3 mj dv/dt Peak Diode Recovery dv/dt ƒ 5.0 V/ns T J Operating Junction and 55 to 50 T STG Storage Temperature Range Soldering Temperature, for seconds 300 (.6mm from case ) C Thermal Resistance Parameter Typ. Max. Units R θjc JunctiontoCase.9 R θja JunctiontoAmbient (PCB mount)** 50 C/W R θja JunctiontoAmbient www.irf.com 2/3/04
Electrical Characteristics @ T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS DraintoSource Breakdown Voltage 0 V V GS = 0V, I D = 250µA V (BR)DSS/ T J Breakdown Voltage Temp. Coefficient 0.2 V/ C Reference to 25 C, I D =.0mA R DS(on) Static DraintoSource OnResistance 0.205 Ω V GS = V, I D = 7.8A V GS(th) Gate Threshold Voltage 2.0 4.0 V V DS = V GS, I D = 250µA g fs Forward Transconductance 3.2 S V DS = 50V, I D = 7.8A I DSS DraintoSource Leakage Current 25 V µa DS = 0V, V GS = 0V 250 V DS = 80V, V GS = 0V, T J = 50 C I GSS GatetoSource Forward Leakage 0 V GS = 20V na GatetoSource Reverse Leakage 0 V GS = 20V Q g Total Gate Charge 58 I D = 8.4A Q gs GatetoSource Charge 8.3 nc V DS = 80V Q gd GatetoDrain ("Miller") Charge 32 V GS = V, See Fig. 6 and 3 t d(on) TurnOn Delay Time 5 V DD = 50V t r Rise Time 58 I D = 8.4A ns t d(off) TurnOff Delay Time 45 R G = 9.Ω t f Fall Time 46 R D =6.2Ω, See Fig. D Between lead, L D Internal Drain Inductance 4.5 6mm (0.25in.) nh G from package L S Internal Source Inductance 7.5 and center of die contact S C iss Input Capacitance 760 V GS = 0V C oss Output Capacitance 260 pf V DS = 25V C rss Reverse Transfer Capacitance 70 ƒ =.0MHz, See Fig. 5 SourceDrain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol 3 (Body Diode) showing the A I SM Pulsed Source Current integral reverse G 52 (Body Diode) pn junction diode. S V SD Diode Forward Voltage.6 V T J = 25 C, I S = 7.8A, V GS = 0V t rr Reverse Recovery Time 30 90 ns T J = 25 C, I F = 8.4A Q rr Reverse Recovery Charge 650 970 nc di/dt = 0A/µs t on Forward TurnOn Time Intrinsic turnon time is negligible (turnon is dominated by L S L D ) Notes: Repetitive rating; pulse width limited by max. junction temperature. ( See fig. ) Starting T J = 25 C, L = 6.4mH R G = 25Ω, I AS = 7.8A. (See Figure 2) ƒ I SD 7.8A, di/dt 200A/µs, V DD V (BR)DSS, T J 50 C Pulse width 300µs; duty cycle 2%. This is applied for IPAK, L S of DPAK is measured between lead and center of die contact Uses IRF9530N data and test conditions. ** When mounted on " square PCB (FR4 or G Material ). For recommended footprint and soldering techniques refer to application note #AN994 2 www.irf.com
I D, DraintoSource Current (A) 0 0. VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V 20µs PULSE WIDTH 0.0 T J = 25 C 0. 0 V DS, DraintoSource Voltage (V) I D, DraintoSource Current (A) 0 VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM4.5V 4.5V 20µs PULSE WIDTH 0. T J = 50 C 0. 0 V DS, DraintoSource Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics I D, DraintoSource Current (A) 0 T J = 25 C T J= 50 C V DS= V 20µs PULSE WIDTH 0. 4 5 6 7 8 9 V GS, GatetoSource Voltage (V) R DS(on), DraintoSource On Resistance (Normalized) 2.5 I D = 4A 2.0.5.0 0.5 V GS= V 0.0 60 40 20 0 20 40 60 80 0 20 40 60 T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized OnResistance Vs. Temperature www.irf.com 3
C, Capacitance (pf) 2000 V GS = 0V, f = MHz C iss = C gs C gd, C ds SHORTED C rss = Cgd 600 C oss = C ds Cgd 200 C iss 800 C oss Crss 400 0 A 0 V DS, DraintoSource Voltage (V) V GS, GatetoSource Voltage (V) 20 5 5 I = D 8.4A V DS =80V V DS =50V V DS =20V FOR TEST CIRCUIT SEE FIGURE 3 0 0 20 30 40 50 60 Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. DraintoSource Voltage Fig 6. Typical Gate Charge Vs. GatetoSource Voltage I SD, Reverse Drain Current (A) 0 T J = 50 C T J = 25 C V GS = 0 V 0. 0.2 0.8.4 2.0 2.6 V SD,SourcetoDrain Voltage (V) I I D, Drain Current (A) 00 0 OPERATION IN THIS AREA LIMITED BY R DS(on) us 0us ms TC = 25 C TJ = 50 C Single Pulse ms 0 00 V DS, DraintoSource Voltage (V) Fig 7. Typical SourceDrain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com
5 V DS R D I D, Drain Current (A) 2 9 6 3 0 25 50 75 0 25 50 T C, Case Temperature ( C) R G V GS V Pulse Width µs Duty Factor 0. % D.U.T. Fig a. Switching Time Test Circuit V GS t d(on) t r t d(off) t f % V DD 90% Fig 9. Maximum Drain Current Vs. Case Temperature V DS Fig b. Switching Time Waveforms Thermal Response (Z thjc ) 0. D = 0.50 0.20 0. 0.05 0.02 0.0 SINGLE PULSE (THERMAL RESPONSE) Notes:. Duty factor D = t / t 2 2. Peak T J = P DM x Z thjc TC 0.0 0.0000 0.000 0.00 0.0 0. t, Rectangular Pulse Duration (sec) PDM t t2 Fig. Maximum Effective Transient Thermal Impedance, JunctiontoCase www.irf.com 5
Fig 2a. Unclamped Inductive Test Circuit I AS V DS L R G D.U.T IAS 20V DRIVER tp 0.0Ω V V DD DD A 5V E AS, Single Pulse Avalanche Energy (mj) 500 400 300 200 0 I D TOP 3.5A 4.9A BOTTOM 7.8A 0 25 50 75 0 25 50 Starting T, Junction Temperature ( J C) tp Fig 2c. Maximum Avalanche Energy Vs. Drain Current V (BR)DSS Fig 2b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. V Q G 2V.2µF 50KΩ.3µF Q GS Q GD D.U.T. V DS V G V GS 3mA Charge I G I D Current Sampling Resistors Fig 3a. Basic Gate Charge Waveform Fig 3b. Gate Charge Test Circuit 6 www.irf.com
Peak Diode Recovery dv/dt Test Circuit D.U.T* ƒ Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer V GS R G dv/dt controlled by R G I SD controlled by Duty Factor "D" D.U.T. Device Under Test V DD * Reverse Polarity of D.U.T for PChannel Driver Gate Drive Period P.W. D = P.W. Period [ V GS =V ] *** D.U.T. I SD Waveform Reverse Recovery Current ReApplied Voltage Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt Inductor Curent Body Diode Ripple 5% Forward Drop [ V DD ] [ ] I SD *** V GS = 5.0V for Logic Level and 3V Drive Devices Fig 4. For PChannel HEXFETS www.irf.com 7
DPak (TO252AA) Package Outline Dimensions are shown in millimeters (inches) DPak (TO252AA) Part Marking Information EXAMPLE: THIS IS AN IRFR20 WITH ASSEMBLY LOT CODE 234 ASSEMBLED ON WW 6, 999 IN THE ASSEMBLY LINE "A" Note: "P" in assembly line position indicates "LeadFree" INTERNATIONAL RECTIFIER LOGO AS S E MBLY LOT CODE IRFU20 96A 2 34 PART NUMBER DATE CODE YEAR 9 = 999 WEEK 6 LINE A OR INTERNATIONAL RECTIFIER LOGO AS S EMBLY LOT CODE IRFU20 2 34 PART NUMBER DATE CODE P = DESIGNATES LEADFREE PRODUCT (OPTIONAL) YEAR 9 = 999 WEEK 6 A = ASSEMBLY SITE CODE 8 www.irf.com
IPak (TO25AA) Package Outline Dimensions are shown in millimeters (inches) IRFR/U54PbF IPak (TO25AA) Part Marking Information EXAMPLE: THIS IS AN IRFU20 WITH ASSEMBLY LOT CODE 5678 ASSEMBLED ON WW 9, 999 IN THE ASSEMBLY LINE "A" Note: "P" in as sembly line position indicates "LeadFree" INTERNATIONAL RECT IFIER LOGO ASS EMB LY LOT CODE IRFU20 99A 56 78 PART NUMBER DATE CODE YEAR 9 = 999 WEEK 9 LINE A OR INTERNAT IONAL RECTIFIER LOGO ASSEMBLY LOT CODE IRFU20 56 78 PART NUMBER DATE CODE P = DESIGNATES LEADFREE PRODUCT (OPTIONAL) YEAR 9 = 999 WEEK 9 A = ASSEMBLY SITE CODE www.irf.com 9
DPak (TO252AA) Tape & Reel Information Dimensions are shown in millimeters (inches) TR TRR TRL 6.3 (.64 ) 5.7 (.69 ) 6.3 (.64 ) 5.7 (.69 ) 2. (.476 ).9 (.469 ) FEED DIRECTION 8. (.38 ) 7.9 (.32 ) FEED DIRECTION NOTES :. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA48 & EIA54. 3 INCH 6 mm NOTES :. OUTLINE CONFORMS TO EIA48. Data and specifications subject to change without notice. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (3) 25275 TAC Fax: (3) 2527903 Visit us at www.irf.com for sales contact information.2/04 www.irf.com
Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/