SSO Noise, Eye Margin, and Jitter Characterization for I/O Power Integrity

DESIGNCON 2009 SSO Noise, Eye Margin, and Jitter Characterization for I/O Power Integrity Vishram S. Pandit, Intel Corporation [vishram.s.pandit@intel.com, (916)356-2059] Ashish N. Pardiwala, Intel Corporation [ashish.n.pardiwala@intel.com, (916)356-8292] Hsiao-ching Chuang, Intel Corporation [hsiao-ching.chuang@intel.com, (408)-765-0334] Myoung J. Choi, Intel Corporation [myoung.j.choi@intel.com, (916) 933-8743] Md. Ruhul Quddus, Intel Corporation [md.r.quddus@intel.com@intel.com, (480) 554 4738]

Abstract In this paper, we describe the Power Integrity design and characterization for a single ended I/O interface through noise, EYE margin, and jitter measurements. The frequency domain techniques are used for designing the I/O PDN. For PDN characterization, onchip PDN elements are extracted through the VNA measurements. The peak to peak voltage noise is measured on-chip at the driver. The Eye margin reduction and jitter induced due to power noise are characterized versus frequency. The overall signature of the time domain noise, Eye margin reduction and jitter response is well correlated with simulated impedance response. Author s Biography Vishram S. Pandit: Vishram is Power Integrity Engineer at Intel Corporation. He works on developing power delivery designs for high speed interfaces. His focus areas include highspeed system power delivery, on-chip power delivery, and Signal/ Power Integrity codesign. Ashish N. Pardiwala: Ashish is Analog Design Engineer at Intel Corporation. He works on Signal Integrity Engineering characterization for high speed interfaces. His focus areas include System level Signal Integrity characterization, path-finding, and test vehicles for future technologies. Hsiao-ching Chuang: Hsiao-Ching is Analog Circuit Engineer at Intel Corporation. She works on custom logic circuits, timing analysis and specification definition for high-speed interfaces. Myoung Joon Choi: Myoung "Joon" Choi is a signal and power integrity engineer at Intel Corporation, working on signal integrity, system analysis and high speed channel optimization, and SI-PI co-integrity. His research interests are modeling, new simulation algorithms, and high speed signal-power integrity. He has received the M.S. and PhD degree from the electrical and computer engineering at the University of Illinois at Urbana- Champaign (UIUC) in 2001 and 2004 respectively and received the B.S. degree from Korea University, Seoul, Korea, in 1997. Md. Ruhul Quddus: Ruhul is Power Integrity (power delivery network) engineer at Intel Corporation. He is responsible for computer system products power delivery network design. His focus areas include developing statistical PD methodology and jitter-based target to design PDN.

1.0 Introduction The Power Delivery Network (PDN) for a single ended Input/ Output (I/O) interface is designed. Figure 1 shows a simplified diagram for a single ended I/O interface. It is a push-pull driver with Center Tap Termination (CTT) at the receiver end. VCC Driver A Receiver R2 R1 B D R1 Z0 R2 C VSS Figure 1 Simplified Diagram for an I/O Interface There are different nodes indicated in the diagram: A is the driver power node, C is the driver ground node, B is the driver side I/O node, and D is receiver side I/O node. These will be used in simulations and measurements in the following sections. Overall impedance response from the chip is simulated and optimized based on the design target. It is essential to characterize the effect of the PDN in terms of noise and timing impact. Based on the bus activity, different frequencies are activated in the PDN. By varying the data rates and patterns, frequency response of the noise and jitter is obtained. 2.0 I/O PDN Design 2.1 Power Delivery Network Figure 2 shows the PDN for the I/O interfaces.

I/O On- Chip PDN PKG PDN BRD PDN VRM Figure 2 Power Delivery Network for I/O Motherboard has a DC/ DC converter or a Voltage Regulator Module (VRM). There are some bulk capacitors which are effective in low frequencies. The motherboard stackup determines the power to ground planar capacitance. The silicon chip is typically designed with a mult-layer Grid Array (GA) package. It is mounted on the motherboard, and near the chip there are some edge capacitors. The package provides a very tight coupling between power and ground. There are some low Equivalent series inductance (ESL) package capacitors which provide smaller loop inductance. 2.2 PDN Design Target Typically, PDN is designed using Frequency Domain techniques. Self Impedance or Z11, is the primary design criterion. For the I/O PDN the design target for the PDN impedance is based on the Equation 1: Equation 1: V ( Δv) (1) Z = Imax Imin where V is the nominal voltage of the rail, v is the required tolerance, and Imax-Imin is the di/dt current. The I/O interface in consideration is a single ended system with Center Tap Termination (CTT). The currents in the PDN are determined as described in reference [2]. Using the di/dt currents and the required tolerance for the given range, the self impedance or Z11 target can be calculated. For the I/O interface, overall current in the PDN when the entire bus is switching, needs to be accounted for. The Z11 obtained with this technique is the self impedance for the PDN looking in the chip. For the given interface, the required Z11 comes out to be about 200 mohms. It is to be noted that, this Z11 is high compared to earlier published literature for the core PDN (3). The impedance target depends on the di/dt and the required tolerance. 2.2 PDN Analysis and Optimization First, the package and board PDN are modeled with planar 3D electromagnetic solver, without any capacitors. Only the capacitors related to voltage regulator module are mounted. The S parameters are computed over a broad frequency range up to 6GHz. The self impedance Z11 at the package bump is shown in Figure 3. It shows much higher impedance than the required impedance.

3E2 1E2 Mag[Z(1,1)] Ω mag(z(6,6)) 1E1 1 1E-1 1E-2 1E7 1E8 1E9 6E9 freq, Hz Figure 3 Z11 with Motherboard and Package without the capacitors Different capacitors are evaluated for the decoupling. Bulk capacitors are used for low frequency bypassing. Its effective range is up to a few MHz. The edge capacitors are placed near the driver, and its effective range is up to a few 10s of MHz. The package capacitors are reverse geometry capacitors and they have very low ESL. The effective frequency goes up to 100s of MHz. Above that frequency only the on-chip capacitor Cdie is effective (4). Once the effective frequency ranges for different capacitive elements is known, they are placed and the number of those are optimized. First some bulk capacitors are placed on the motherboard and overall self impedance Z11 looking from the BGA side is plotted as shown in Figure 4A. Then the edge capacitors are added near the driver and Z11 is analyzed as shown in Figure 4B. Mag[Z(1,1)] mag(z(7,7)) Ω A] B] 5E1 1E1 1 1E-1 1E-2 1E3 1E4 1E5 1E6 1E7 1E8 5E8 Mag[Z(1,1)] mag(z(8,8)) Ω 1E1 1 1E-1 1E-2 1E7 1E8 1E9 6E9 freq, Hz freq, H z Figure 4 Z11 with MB + PKG A] Bulk Caps, B] Bulk Caps + Edge Caps The number of bulk capacitors and edge capacitors are optimized based on the desired response. Compared to no motherboard capacitor response, bulk capacitors improve the lower frequency response, and edge capacitors improve the higher frequency response. However, the impedance value is still much higher than the target impedance. The motherboard components are designed in such a way that the target impedance is met

well over 50MHz or so. Above that frequency only the package decoupling and on-chip decoupling components are effective (4). The package capacitors are placed on the package and optimized to get the broadband Z11 response. The Z11 response is simulated at the package bump side as shown in Figure 5A. With the package capacitors, the target impedance is met up to a few hundreds of MHz frequency. Above that frequency only the on-chip capacitor will be effective. With the on-chip capacitor, the broadband response is obtained which complies with the impedance targets over wide frequency range. mag(z(9,9)) Mag[Z(1,1)] Ω A] B] 1E1 1 1E-1 1E-2 1E-3 1E7 1E8 freq, Hz 1E9 6E9 Mag[Z(1,1)] Ω mag(z(10,10)) 3E-1 1E-1 1E-2 1E7 1E8 freq, Hz 1E9 6E9 Figure 5 Z11 with A] MB Caps + PKG Caps, B]MB Caps + PKG Caps +Chip caps The on-chip model is a single node PDN model with Cchip and its parasitic Rchip. The bumps are connected to the on-chip capacitor through the power grid parasitics (Lgrid, Rgrid). Figure 5B shows the simulated Z11 response at the power and ground nodes at the chip. It has a resonant peak at about 235 MHz. At this frequency it exhibits highest impedance. Any switching pattern which has this prominent frequency will exhibit higher noise. 2.3 Primary FD Parameters for TD Performance 2.3.1 Self Impedance or Z11 In the earlier section the self impedance or Z11 of the PDN is analyzed and PDN is optimized to meet the given Z11 target. This Z11 is at the chip location. The self impedance Z11 is plotted again with the linear scale in Figure 6. With reference to Figure 1, the self impedance is between nodes A to C. When there is a current fluctuation in the PDN the noise is generated. Noise should follow a similar signature as that of Z11, when frequency of the noise is varied. The frequency of the noise can be varied by switching different patterns and data rates. In the following sections, the time domain noise at the chip location is compared against this Z11 and signature is verified.

0.20 Mag[Z(1,1)] mag(z(12,12)) Ω 0.15 0.10 0.05 0.00 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 freq, GHz Figure 6 Simulated Self Impedance at the Chip Location 2.3.1 Power to Signal Transfer Impedance Second important parameter in the PDN design is PD to Signal coupling at the chip. It is the transfer impedance from power net to signal net at the chip as shown in Figure 7. 0.14 0.12 Mag[Z(1,2)] Ω mag(z(2,12)) 0.10 0.08 0.06 0.04 0.02 0.00 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 freq, GHz Figure 7 Simulated Power to Signal Coupling at the Chip With reference to Figure 1 the transfer impedance is from nodes A to B. When the driver is switching there is an effective resistance Ron from power net to signal net. For this simulation, the Ron and far end On-Die Termination (ODT) are used. The transfer impedance indicates the power domain to signal coupling at the chip, when driver is switching. It shows a peak at about 220 MHz. It follows a similar curve as the self impedance. The coupled noise from power to signal at the chip, affects the timing of the signals. Therefore, the jitter on the signal nets due to Power noise at the chip will follow the similar signature as shown in Figure 7, when the frequency of the noise is varied. Later on in this paper, we vary the frequency of the noise, and measure the jitter impact which corresponds to the signature of the Power to Signal coupling.

2.3.1 SSO Impact in Frequency Domain Simultaneously Switching Output (SSO) occurs when a number of buffers are switching simultaneously, producing noise and consequently the timing impact. When a buffer A under consideration is switching, it produces noise in the power domain. When its neighboring buffers are also switching, the noise due to them, affect the buffer A. Overall power noise for buffer A increases due to other neighbors. The extent in which the neighbors are affecting the buffer A can be determined using frequency domain design techniques. In earlier section, for analyzing Z11 a simple single node chip PDN model has been used. For determining the SSO impact in frequency domain, distributed chip PDN model is used. Previously, a 2D TLM model has been used and validated for accuracy (5-7). A similar model is used for the SSO analysis, based on the chip layout. This distributed chip model is combined with the package model and the motherboard model for system level analysis. In the design under consideration, there are 8 DQ Modules DQ0 Module through DQ7 Module. It has distributed chip side power ports per module locations. The victim module for SSO is DQ4 Module or DQ4M. The impact of neighboring modules is examined by plotting transfer impedance from DQx power node to DQ4M power node, as shown in Figure 8. DQ4M power node is corresponding to 1 byte whereas power nodes of all other modules correspond to 2 bytes. This is similar to correlation setup as described in section 3.2.2. From DQ5M power node to DQ4M power node there is a significant coupling. Next, the plot shows coupling from DQ7M power node to DQ4M power node. This is lower than that for DQ5M. The third curve in the plot shows coupling from DQ3M power node to DQ4M power node. It is very low indicating that the noise on the power node of DQ3M will not impact much the DQ4M power node. Ω 2E0 1 Transfer Impedance from Neighboring Modules mag(dqm3to4) mag(dqm7to4) mag(z12) mag(dqm5to4) 1E-1 1E-2 1E-3 0.0 0.2 0.4 0.6 0.8 1.0 freq, GHz Z(DQM4, DQM5) Z(DQM4, DQM7) Z(DQM4, DQM3) Figure 8 Coupling from Power Nets of Other Modules to DQ4-Module

For analyzing SSO impact on DQ4M, from neighboring modules, the transfer impedances from neighboring modules need to be considered. This is an additive impact so the total power impedance for the DQ4M is a summation of the self impedance and transfer impedances from the other modules. As an example, the total power node impedance for DQ4M taking into account the DQ4M and DQ5M will be: Equation 2: Ztot: DQ4M (DQ4M-5M) = Z11 (DQ4M) + Z12 (DQ4M-DQ5M) The Equation 2 shows the Z for DQ4M considering SSO of DQ4M and DQ5M. Further, taking into account the DQ6M the total Z for DQ4M power node becomes Equation 3 : Ztot: DQ4M (DQ4M-6M) = Z11 (DQ4M) + Z12 (DQ4M-DQ5M) + Z12 (DQ4M-DQ6M) The Equation 3 above shows the Z for DQ4M considering SSO of DQ4M, DQ5M, and DQ6M The above procedure is repeated for all the modules. With this, the total SSO impact from the neighboring modules can be analyzed and plotted, as shown in Figure 9. The frequency of the Z11 and Z1x in the curve is 200MHz. After certain distance, the SSO impact gets saturated as shown in Figure 9. Total Z simulated at DQ Module 4 (DQM4) Total Z = Z11 + Sum (Z1x) Ohms 3 2.5 2 1.5 1 0.5 0 DQM4 DQM4 DQM5 DQM4 DQM6 DQM4 DQM7 DQM3 DQM7 DQM2 DQM7 DQM1 DQM7 DQM0 DQM7 DQ Module Switching Locations Figure 9 SSO Impact and Saturation

From the Figure 9, the total Z for DQ4M increases with two modules (DQ4M-5M), three modules (DQ4M-6M) and four modules (DQ4M-7M). However, DQ3M through DQ0M do not have much impact in terms of the SSO. This is dependent on the chip layout and the placement of on-chip PD elements. Therefore beyond DQ3M the SSO is getting saturated. Once the frequency domain SSO impact is obtained, changes can be made in the on-chip Power Delivery design in order to optimize the effect. This frequency domain characterization of the SSO is later on validated by turning on the corresponding neighboring modules and measuring the noise at DQ4M, with 200MHz switching pattern. 3.0 I/O PDN Characterization 3.1 Frequency Domain Characterization I/O PDN characterization is done in frequency domain and in time domain. Frequency domain PCB PDN VNA characterization details are described in [8]. Two port network VNA measurements are used for PDN measurements. It is usually fairly straightforward to characterize the PCB, and package PDN and corresponding components. However, it is very difficult to correlate with the on-chip Z11 response. The VNA probing points on the chip are not available. Therefore, VNA probing is done on the package BGA locations. The package capacitors are removed so as to get effect from the on-chip capacitors. Z11 is open circuit response as shown in Figure 10. 5E1 1E1 mag(z(3,3)) mag(zin_dut) 1 1E-1 1E5 1E6 1E7 1E8 5E8 Measurement freq, Hz Equivalent Model Figure 10 VNA Measurement for determining On-chip PD Elements The S parameters are fit into a lumped model. The extracted equivalent PDN model is in the RLGC format. From the measured data the power delivery components are extracted.

Figure 11 shows the equivalent model for the measurements. Cdie is the intentional chip capacitor with parasitic resistance Rdie. Rleak is the leakage resistor. Rs is a combination on equivalent package power domain resistance and equivalent power grid resistance. Ls is a combination of equivalent power grid inductance and package power inductance. This equivalent model can be used up to a few GHz, above which a more complex model will be required. Ls Buffer VCC Rs Bump Cdie Rleak Rdie VSS Figure 11 Equivalent Power Delivery Model for the Chip and Package 3.2 Time Domain Characterization The on-chip Z11 response is an open circuit response. It does not show a system level response looking from the chip. Time domain characterization enables to determine the noise and jitter. With varying the data rate and patterns, the frequency response of noise and jitter can be determined. 3.2.1 On-chip Noise Measurements at the Driver For probing the noise at the die of the drivers, special structure is designed to have a measuring probe connected to the lower metal layers of the silicon. The DQ bus activity then programmed with different data rates and different data patterns, with all DQ bits on the interface simultaneously toggling. The combination of data pattern and data rates setup will excite different frequencies of switching noise at the driver power supply. For example, at 1066MTs, 1010 data pattern will have dominant simultaneous switching noise (SSN) tone at 553MHz, 1100 data pattern will have dominant SSN noise tone at 266MHz. Figure 12 shows a pico-probing plot for on-chip noise measurement, when bus is operated at 1066Mbps with 1100 data pattern.

Figure 12 Screen Capture of Pico-probing Measurements The FFT response shows 266MHz peak pertaining to 1100 data rate. It also shows a 533MHz component pertaining to the strobe frequency. These measurements are repeated with different data rate and data pattern settings. The peak to peak SSN noise is measured and plotted against the SSN frequency as shown in Figure 13. The SSN noise is peaking at about 240 MHz and it shows a very similar signature to the frequency domain self impedance response as in Figure 6. Pico-probing result noise amplitude (p2p, mv) 200.00 150.00 100.00 50.00 0.00 0 100 200 300 400 500 600 SSN noise frequency (MHz) Figure 13 Measured On-Chip SSO Noise Amplitude vs. Frequency 3.2.2 Noise Measurements at the Receiver The power noise due to SSN at the driver can be measured by another way. When all the bits in an interface at the driver are switching, the on-chip SSN is coupled to the data bits through the Ron and terminations. This alternate method is implemented by selecting two nearby DQ bits as probes and hold one data bit low (DQL) while another data bit is high (DQH). The neighboring data bits to DQH, DQL programmed low to minimize crosstalk effect in the channel (the measurement is done at the receive end). All the other are switched simultaneously and generate SSN. The bit which is held high reflects the power fluctuations, and the one which is held low

reflects the ground fluctuations at the driver. Overall power to ground noise is obtained by subtracting the two. Referring back to Figure 1, we would like to measure noise at node D and determine the noise from nodes A to C. When DQ is held high, the noise at node A appears at D, and for DQ low situation, noise at node C appears at D. Since we are using two different bits, 1 for DQH and the other for DQL, we need to make sure that they have similar noise profiles on power and/ or ground. Figure 14 Calibration method Figure 14 shows the skew between DQH and DQL bits. By holding both DQH and DQL bits under test to drive 0 while other data bits toggling at SSN frequency, we observed the skew between the two ground noise waveform and we should phase align the two on the scope before starting DQH-DQL measurement. Figure 15 DQH-DQL Measured Noise with 1010 Data Pattern One example of DQH-DQL measured on-die noise is shown on Figure15 with SSN data pattern programmed to 1010 at 1066MTs, 533MHz AC noise is observed through DQH-DQL measurement. The power-ground noise amplitude at the driver is determined by calibrating the channel loss and resistor divider network (On Die

Terminations, Ron for driver, and series resistance on the data line) from the measured result, as shown in Figure 16. Referring back to Figure 1, the Ron, AC impedance of the transmission line, and the termination schemes are simulated to establish the transfer function from A to D. m1 freq= 120.5MHz mag(scaling_factor)=0.378 0.5 m2 freq= 526.0MHz mag(scaling_factor)=0.317 mag(scaling_factor) 0.4 0.3 m1 m2 0.2 50 250 450 600 freq, MHz Figure 16 Transfer Function for Determining On-chip Noise After the noise at point D is measured with DQH-DQL method, with applying the above transfer function, the noise at point A is projected. With this DQH-DQL approach, the noise is measured at different data rates and frequencies. Figure 17 shows graph similar to pico-probing noise. DQH-DQL result noise amplitude (p2p, mv) 250 200 150 100 50 0 0 100 200 300 400 500 600 SSN noise frequency (MHz) Figure 17 Projected On-chip Noise at Driver with DQH-DQL Approach As seen in Figure 17, the projected on-chip noise from the receiver side measurements show a very similar curve to Z11 as simulated in Figure 6.

Then, we examine the impact from the other switching bits. Each DQ module has 16 bits. For a particular case for DQM4, 8 bits are switching and remaining 8 bits are held 0. Out of those held 0 one is DQH and the other is DQL. This way it minimizes the crosstalk impact for the noise measurement. Then, the bits in the neighboring modules are switched at the same frequency/ data rate. Figure 18 shows the accumulated SSN noise amplitude at DQM4, at 200MHz switching pattern. Supply noise probed at DQ Module 4 (DQM4) (8 DQ bits switching effect from DQM4, 16 DQ bits switching effect from all the other modules ) noise amplitude (p2p,mv) 250 200 150 100 50 0 DQM4 DQM4 DQM5 DQM4 DQM5 DQM6 DQM4 DQM7 DQM3 DQM7 DQM2 DQM7 DQM1 DQM7 DQM0 DQM7 DQ bits switching location (SSN source) Figure 18 SSN Impact of the Neighboring Modules First data point is taken when only Module 4 is switching, then Modules 4-5 switching, then Modules 4, 5, 6 switching, and so on. The SSN noise amplitude saturates after enabling the first few neighboring DQ modules. Comparing to Figure 9, SSO impact in frequency domain, the curve above in Figure 18 shows a very similar saturation pattern, and also relative amplitude for Ztotal and SSO time domain noise are comparable. 3.2.2 Eye Diagram Measurements at the Receiver 3.2.2.1 Measurements Setup Fully function system including Driver, Motherboard, and Receiver components is used for Eye Diagram Measurements. A special software is used to enable particular data rate, and bit pattern. Agilent 12GHz bandwidth scope is used with 40GS/s sample rates. There are two types of measurements: one is DQS or strobe jitter due to SSO and the other is timing window reduction due to SSO. 3.2.2.1 DQS Jitter due to SSO

First, we determine the strobe line jitter due to SSO. Victim bit is toggling 1010 pattern and remaining 7 bits in that byte lane are quite. There is no crosstalk as neighboring bits are not toggling. The DQS strobe line jitter is measured with respect to the Clock. Then, the SSO is introduced by toggling remaining bits (except the very close-by bits that cause the crosstalk) in other DQ modules. Figure 19 shows the DQS7 jitter measurements without the SSO noise, victim DQ bit is toggling with 1010 pattern. Figure 19 DQS Jitter without the SSO Noise Figure 20 shows the DQS7 jitter measurements with the SSO noise, DQ59 toggle 1010 and remaining DQ modules toggle 1100 pattern.

Figure 20 DQS Jitter With the SSO Noise for 1100 pattern This experiment is repeated with different data patterns 1010, 1100, and 11110000 in order to get the frequency response. Then, the jitter with the SSO case is subtracted from that without the SSO case. This delta jitter is attributed to the SSO effects. Figure 21 shows the jitter induced due to power noise for the strobe lines. DQS Jitter due to SSO 80 70 60 Delta Jitter(ps) 50 40 30 20 10 0 0 100 200 300 400 500 600 Frequency (MHz) DQS Figure 21 Frequency Response of the DQS Jitter

3.2.2.1 Timing Window Reduction due to SSO With the same setup, the setup/ hold time at the receiver is measured. In this case, instead of holding the data bits high or low, the victim bit is toggling 1010 with maximum data rate. The neighboring bits to the victim bit are masked to eliminate crosstalk effects. All the other Modules on the interface are kept simultaneously switching. The setup/ hold times are measured on the victim bit with Eye Diagram measurements. Similar to the noise measurements, the pattern and data rates for the other toggling bits varied. Figure 22 shows the DQ-DQS Setup/Hold time measurements without the SSO noise, victim DQ bit only toggle 1010 pattern Figure 22 Setup/ Hold Time without the SSO Noise Figure 23 shows the DQ-DQS Setup/Hold time measurements with the SSO noise, Victim DQ bit toggle 1010 pattern and other DQ modules toggle 1100 pattern

Figure 23 Setup/ Hold Time with SSO Noise for 1100 Pattern The window margin difference for without SSO noise and with SSO noise is plotted as shown in Figure 24. Margin window (Withough SSO-With SSO) 70 60 50 Window Reduction (ps) 40 30 20 10 0-10 0 100 200 300 400 500 600 Window -20-30 Frequency (MHz) Figure 24 Timing Window Reduction due to SSO For this plot also, the data rate is varied from 1067Mbps to 800Mbps. Different patterns such as 1010, 1100, and 11110000 are used. Comparing Figure 7 with Figure 23-24, it is observed that the frequency response of Eye margin reduction and jitter

closely match with the transfer impedance (PD to signal coupling) response at the driver chip. 4.0 Conclusion PCB, package and on-chip PDN need to be analyzed for the I/O PDN design. Different decoupling elements are placed in the PDN to achieve the impedance design targets. The I/O PDN is designed in frequency domain and characterized in time domain. 1] Self impedance and Noise: On-chip pico-probing is performed and the time domain peak to peak noise is obtained. The time domain peak to peak noise value is plotted against the frequency based on the bus operation pattern. It shows similar signature to the simulated PDN Z11 response. Alternatively, the driver side chip level noise is measured at the receiver, with holding one bit high (DQH) and the other bit low (DQL). The projected chip level noise follows the Z11 signature at the chip. 2] SSO effects: The SSO impact and saturation is simulated in frequency domain by adding the transfer impedances from neighboring power nodes. Then, it is verified in time domain by switching individual neighboring modules and measuring SSO noise at the victim module with DQH-DQL method. 3] PD to signal coupling and Timing: Power to signal coupling is determined in frequency domain analysis. The Eye margin reduction due to SSO and jitter due to SSO is plotted against the frequency by varying the data rates and the patterns. The frequency response of SSO timing impact closely matches with the simulated transfer impedance (PD to signal coupling) profiles. 5.0 Future Work In this paper, we have characterized the on-chip power noise, and its impact on the system timing. The data patterns used are systematic in nature simultaneously switching at specific frequencies. The crosstalk effects are eliminated by switching off the neighboring bits. The channel resonance effects are not considered. This may be the worst case power integrity condition, however, other conditions such as channel resonance, worst case crosstalk and worst case ISI conditions need to be considered. Probability of these conditions occurring at the same time need to be determined, for overall system response. Acknowledgements: Authors would like to thank Joe Salmon, Woong Hwan Ryu, Julius Delino, and Erich Heinemann.

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