Varactor Loaded Transmission Lines for Linear Applications

Varactor Loaded Transmission Lines for Linear Applications Amit S. Nagra ECE Dept. University of California Santa Barbara

Acknowledgements Ph.D. Committee Professor Robert York Professor Nadir Dagli Professor Umesh Mishra ECE Dept. UCSB Dr. Michael VanBlaricum Toyon Research Corporation Goleta, CA Varactor loaded lines Professor Rodwell ECE Dept. UCSB

Varactor Loaded Transmission Lines for Linear Applications Used for several nonlinear applications like ultra fast pulse generation, pulse shaping, soliton generation, harmonic multipliers etc. Potential of this technology for linear applications not fully realized Motivation for linear applications Varactor loaded transmission lines have bias dependant properties Impedance, phase velocity, time of flight can be controlled Useful for applications such as phase shifters, true time delay units, travelling wave antenna arrays, tunable impedance matching networks Capable of low loss performance Consume small DC power Fast switching response Easily fabricated using monolithic fabrication techniques Compatible with existing GaAs MMIC technology

Equivalent Circuit for Varactor Loaded Transmission Lines Schematic for varactor loaded transmission line 1 Z i, v i 2... n Z i, v i Z i, v i C var C var C var L sect Equivalent circuit for varactor loaded transmission line L t C t C var (V) L t C t C var (V) L t C t C var (V) Transmission line represented by equivalent inductance and capacitance per section L t sect lv Z C lsect = i t = Z v i i i

Basic Principle of Synthetic Transmission lines Periodic structure-exhibits Bragg reflection phenomenon f Bragg 1 = π LtbCt + Cvarg Behaves like synthetic transmission line for frequencies << Bragg Frequency Z L (V), v phase (V) L tot = n L sect Properties of the synthetic transmission line Bias dependant impedance Bias dependant phase velocity Z v L = phase = b Ll C + C ( V) l l var sect b 1 L C + C ( V) / l l l var sect g g

Varactor Loaded Transmission Lines as Low Loss Analog Phase Shifters Current state of the art Demonstration of hybrid prototypes of analog phase shifters Relatively low frequency of operation (< 5 GHz) No efforts to optimize the insertion loss performance Focus of our effort Optimize design of analog phase shifters for lowest possible insertion loss Increase frequency of operation by adopting monolithic fabrication techniques Demonstrate optimized phase shifters operating at K-band

Design Equations for Varactor Loaded Transmission Line Phase Shifters Key design variable- loading factor x = C max var / l C l sect Impose constraint that impedance of the synthetic line be 50 Ω Zi = 50 1+ x Pick a minimum Bragg frequency f min Bragg = π c L C 1 + C max t t var h = π l sect vi 1+ x Determine spacing between loading capacitors from the minimum Bragg frequency l sect = vi min π f 1+ x Bragg Determine value of the variable capacitors C max var = 1 x min 50 f 1+ x Bragg a f

Design Equations for Varactor Loaded Transmission Line Phase Shifters Express phase shift per section at frequency (f) of interest in terms of the loading factor (x) and capacitance ratio (y) δφ = 2π f l sect 1+ x 1+ xy v i c min y = C / C var max var h Determine number of sections required for 360º of phase shift n sect = 2π δφ All the design parameters - Z i, L sect, C var, n sect - have been specified in terms of the loading factor, minimum Bragg frequency and tuning ratio Minimum Bragg frequency must be higher than frequency of interest Tuning ratio determined by the variable capacitor technology Loading factor only degree freedom available for optimizing loss Optimum loading factor for lowest loss depends on varactor and transmission line technology

Choice of Transmission Line and Variable Capacitor technology RF input CPW Center Conductor CPW Ground RF output Shunt Varactor Diodes CPW Ground CPW lines best for low parasitic connections of shunt components Two variable capacitors connected in parallel to preserve symmetry Ground to ground spacing limited to half of length of the section Lines fabricated on semi-insulating GaAs (ε s =13) Varactor technology Schottky diodes on GaAs 2 µm design rules for Schottky contact width and spacing from N-ohmics f c = 700 GHz, capacitance ratio (y) = 2.4

Components of Insertion Loss Varactor loss per section Due to series resistance of the diode Inversely proportional to cutoff frequency Increases as square of frequency b 1 Lvar = f Cvar rs ZL = 2 2 2 π π g f f 2 s C var Z L CPW loss per section Due to resistance of conductors Loss of loaded line is higher than corresponding line loss without loading Strong function of line impedance (Z i ) Depends on substrate dielectric constant, aspect ratio of lines, total line width, metal thickness and resistivity Increases as square root of frequency α Z i b g Attenuation per unit length for unloaded line of impedance Z i L l Z Z cpw sect i Z = αb g i L

Optimization of Insertion Loss Unloaded Line Impedance (Ohms) 50 61 71 79 87 94 100 106 112 100 0.25 Number of Sections 80 60 40 20 Number of sections Diode loss CPW loss 0.2 0.15 0.1 0.05 Loss per section (db) 0 0 0.5 1 1.5 2 2.5 3 3.5 4 Loading Factor (x) 0 Effect of loading factor on loss per section Diode loss per section increases slowly with increase in loading factor beyond x=1 CPW loss per section increases rapidly with increase in loading factor because higher loading factors require higher line impedance Z i

Optimization of Insertion Loss Total circuit loss c h b g 2 f L n L L n C Z n l Z Z tot = sect var + cpw = sectπ var L + sect sectα i f Z s i L Effect of loading factor on total circuit loss Unloaded Line Impedance (Ohms) 50 61 71 79 87 94 100 106 112 7 Total Insertion Loss (db) 6 5 4 3 2 Total Circuit Loss Total Diode Loss Total CPW Loss 1 0 0.5 1 1.5 2 2.5 3 3.5 4 Loading Factor (x)

Optimum Loading for Minimum Circuit Loss Effect of loading factor on total circuit loss Total circuit loss is the product of the loss per section and the number of sections Number of sections decreases with an increase in the loading factor (x) Total contribution of the diode loss decreases with increasing loading factor Total CPW loss goes through a minimum at x=1.2 For x<1.2 number of sections increases very rapidly while for x>1.2 CPW loss per section increases strongly Total circuit loss also shows minimum at x=1.2 Thus there is an optimal value of loading factor for minimum loss Optimal loading factor depends on technology

Monolithic Fabrication Process Process flow originally developed by Professor Rodwell s research group for NLTL work Starting epitaxial layer structure N- N+ 0.5 µm 0.9 µm Semi-insulating GaAs Self aligned ohmic contacts Ohmic contact Ohmic contact

Monolithic Fabrication Process Proton implants for isolation H+ Isolation Implant H+ Isolation Implant H+ Isolation Implant Deposition of Schottky contacts Schottky Contacts

Monolithic Fabrication Process CPW and Interconnect metal CPW Ground CPW Signal CPW Ground SEM pictures showing details of fabricated circuit Ground Signal Interconnect Schottky Ohmic Ohmic

Verification of Optimal Loading Phase shifters with different loading factors fabricated on same wafer All circuits produced 360º of differential phase shift at 20 GHz Insertion loss data measured at 20 GHz agrees well with predicted curve Optimum loading factor of 1.2 for lowest insertion loss 7 6.5 Insertion Loss (db) 6 5.5 5 4.5 Measured Theory 4 0 0.5 1 1.5 2 2.5 3 3.5 4 Loading Factor (x)

Measured Performance of Optimally Loaded Phase Shifter Circuit Differential Phase (Degrees) 500 400 300 200 100 0 Bias= -10 V Bias= -1.6 V Bias= -0.5 V Bias= 0 V 0 5 10 15 20 25 Frequency (GHz) Maximum differential phase shift at 20 GHz ----- 360 Differential phase shift linear with frequency till ~ 15 GHz Phase shift becomes non linear in the vicinity of the Bragg frequency

Measured Performance of Optimally Loaded Phase Shifter Circuit 0 0-1 Bias = -10 V -5 Insertion Loss (db) -2-3 -4-5 -6 Bias = 0 V Return Loss (db) -10-15 -20-25 -30 Bias = 0 V -7-8 0 5 10 15 20 25-35 Bias = -10 V -40 0 5 10 15 20 25 Frequency (GHz) Frequency (GHz) Maximum insertion loss at 20 GHz ----- 4.2 db Lowest insertion loss reported for an analog phase shifter in the K-band Return loss lower than -12 db over all bias states

Accurate Model for the Varactor Loaded Transmission Lines Synthetic transmission line model valid for frequencies well below Bragg frequency- does not predict nonlinear phase shift versus frequency More accurate model obtained by solving the propagation constant for the lumped element unit cell Takes into account the discrete nature of the loading Lumped element unit cell depicting node voltages and currents V n L V t n+1 I n I n+1 C t C var G var

Lumped Element Model Express node voltages and currents in terms of the complex propagation constant γ=α+jβ for a unit cell γ V = e V n+ 1 γ I = e I n+ 1 n n Express node voltages and currents in terms of the lumped elements Equate the real and imaginary parts of the previous equations Vn Vn +1 = j2πflt In I I = G + j2πfbc + C V n n+ 1 var t var n+ 1 Cosh( α)cos( β) = 1 ( 2π f ) Sinh( α)sin( β) = ( 2π f ) 2 L t G var 2 g L ( C + C ) t t var 2 Simplified propagation constant /unit cell for small attenuation Cos( β) = 1 ( 2π f ) α L = ( 2π f ) t G var 2 1 Cos( β) 2 L ( C + C ) t t var 2 2

Comparison of Modeled and Measured Results Differential Phase Shift (Degrees) 500 400 300 200 100 ++++ Measured Lumped element model... Transmission line model 0 0 5 10 15 20 25 Frequency (GHz) Insertion Loss (db) 8 7 6 5 4 3 2 1 ++++ Measured Lumped element model... Transmission line model 0 0 5 10 15 20 25 Frequency (GHz) At low frequencies, both the lumped element model and the synthetic line model are accurate Synthetic line model does not predict deviation from linear phase shift in the vicinity of the Bragg frequency Lumped element model successfully predicts rapid increase in phase shift and loss at frequencies approaching the Bragg frequency

Analysis of Loss Components Measured data provides no insight into origin of circuit loss Lumped element model used to predict relative contributions of CPW conductor loss and diode diode loss to total circuit loss Model indicates that at 20 GHz about 3dB loss is due to the varactor diodes Further improvements must concentrate on reducing diode losses 7 6 Insertion Loss (db) 5 4 3 2 Total Circuit Loss Diode Loss 1 CPW Skin Loss 0 0 5 10 15 20 25 Frequency (GHz)

Motivation Modified Phase Shifter with Multiple Frequency Operation Capability Phase shift and insertion loss scale with number of sections Phase shifter with appropriate number of sections is capable of 360º phase shift with less than 5 db loss at any frequency in the 7-22 GHz range Existing design can be easily modified to take advantage of this property 16 Loss (db) per 360 degreees of Phase Shift 14 12 10 8 6 4 Extrapolated from Measured Data... Predicted by lumped element Model 2 0 5 10 15 20 25 Frequency (GHz)

Modified Phase Shifter with Multiple Frequency Operation Capability Length of section calculated at highest frequency of interest (22 GHz here) Number of sections calculated at lowest frequency of interest (16 GHz here) Bias state with lowest loss used as reference for differential phase shift 0-360º phase shift possible at any frequency in the 16-22 GHz range Full bias range used at 16 GHz while smaller bias range used at 22 GHz Differential Phase Shift (Degrees) 100 0 Bias= -10 V -100-200 Bias= -2 V -300-400 Bias= -0.5 V -500-600 Bias= 0 V -700 16 17 18 19 20 21 22 Frequency (GHz)

Modified Phase Shifter with Multiple Frequency Operation Capability -2 0 Insertion Loss (db) -3-4 -5-6 -7 Bias= -10 V Bias= -2 V Bias= -0.5 V Bias= 0 V Return Loss (db) -10-20 -30-40 Bias= 0 V Bias= -10 V -8 16 17 18 19 20 21 22 Frequency (GHz) -50 16 17 18 19 20 21 22 Frequency (GHz) Maximum loss at 16 GHz is 4.2 db at a bias of 0 V Maximum loss at 22 GHz is 5 db at a bias of -0.5 V *** Note that 0 V bias state is not used at 22 GHz Return loss lower than -15 db over entire frequency range over all bias states of interest

Conclusions Varactor loaded transmission line phase shifter Developed design for varactor loaded line for phase shifting applications Optimized design for obtaining lowest possible insertion loss for given device and transmission line technology Demonstrated K-band analog phase shifter with lowest reported insertion loss