Fall 2013, Koç Uiversity ELEC 204 Digital Systems Desig Egi Erzi College of Egieerig Koç Uiversity,Istabul,Turkey eerzi@ku.edu.tr KU College of Egieerig Elec 204: Digital Systems Desig 1
Today: Datapaths Ø Datapath Example Ø Aritmetic Logic Uit (ALU) Ø Shifter Ø Datapath Represetatio Ø Cotrol Word Elec204 Fall 2013 Caledar (Tetative) M T W T F TA Sep 16, 13 Sep 17, 13 Sep 18, 13 Sep 19, 13 Sep 20, 13 Sep 23, 13 Sep 24, 13 Sep 25, 13 Sep 26, 13 Sep 27, 13 Sep 30, 13 Oct 1, 13 Oct 2, 13 Oct 3, 13 Oct 4, 13 Lab1 PS1 Mustafa- Narjis / Mustafa Oct 7, 13 Oct 8, 13 Oct 9, 13 Oct 10, 13 Oct 11, 13 Oct 14, 13 Oct 15, 13 Oct 16, 13 Oct 17, 13 Oct 18, 13 Oct 21, 13 Oct 22, 13 Oct 23, 13 Oct 24, 13 Oct 25, 13 Lab2 PS2 Tugba - Naveed / Tugba Oct 28, 13 Oct 29, 13 Oct 30, 13 Oct 31, 13 Nov 1, 13 Lab3 Rizwa- Shoaib Nov 4, 13 Nov 5, 13 Nov 6, 13 Nov 7, 13 Nov 8, 13 PS3 Shoaib Nov 11, 13 Nov 12, 13 Nov 13, 13 Nov 14, 13 Nov 15, 13 Lab4 PS4 Mustafa- Shoaib / Narjis Nov 18, 13 Nov 19, 13 Nov 20, 13 Nov 21, 13 Nov 22, 13 Midterm Nov 25, 13 Nov 26, 13 Nov 27, 13 Nov 28, 13 Nov 29, 13 Lab5 Narjis- Naveed Dec 2, 13 Dec 3, 13 Dec 4, 13 Dec 5, 13 Dec 6, 13 Project Prop PS5 Naveed Dec 9, 13 Dec 10, 13 Dec 11, 13 Dec 12, 13 Dec 13, 13 Lab Midterm Tugba- Rizwa Dec 16, 13 Dec 17, 13 Dec 18, 13 Dec 19, 13 Dec 20, 13 PS6 Rizwa Dec 23, 13 Dec 24, 13 Dec 25, 13 Dec 26, 13 Dec 27, 13 Project Report/Demo Lecture 15 KU College of Egieerig Elec 204: Digital Systems Desig 2
Itroductio Computer Specificatio Istructio Set Architecture (ISA) - the specificatio of a computer's appearace to a programmer at its lowest level Computer Architecture - a high-level descriptio of the hardware implemetig the computer derived from the ISA The architecture usually icludes additioal specificatios such as speed, cost, ad reliability. KU College of Egieerig Elec 204: Digital Systems Desig 3
Itroductio (cotiued) Simple computer architecture decomposed ito: Datapath for performig operatios Cotrol uit for cotrollig datapath operatios A datapath is specified by: A set of registers The microoperatios performed o the data stored i the registers A cotrol iterface KU College of Egieerig Elec 204: Digital Systems Desig 4
Datapaths Guidig priciples for basic datapaths: The set of registers Collectio of idividual registers A set of registers with commo access resources called a register file A combiatio of the above Microoperatio implemetatio Oe or more shared resources for implemetig microoperatios Buses - shared trasfer paths Arithmetic-Logic Uit (ALU) - shared resource for implemetig arithmetic ad logic microoperatios Shifter - shared resource for implemetig shift microoperatios KU College of Egieerig Elec 204: Digital Systems Desig 5
Four parallel-load registers Two mux-based register selectors Register destiatio decoder Mux B for exteral costat iput Buses A ad B with exteral address ad data outputs ALU ad Shifter with Mux F for output select Mux D for exteral data iput Logic for geeratig status bits V, C, N, Z Datapath Example Load eable Write D data 0 1 2 3 Decoder D address 2 Costat i Destiatio select MB select Bus A V C N Z Load Load Load Load G select 4 Zero Detect MF select R0 R1 R2 R3 MD select 0 1 MUX D Bus D 1 0 MUX B 0 1 MUX F F Bus B 2 2 A data A B A B H select 2 B S 2:0 C i Arithmetic/logic uit (ALU) G A address A select 0 1 MUX 2 3 Fuctio uit Register file S 0 I R Shifter I L 0 H B select B address 0 1 MUX 2 3 B data Address Out Data Out Data I KU College of Egieerig Elec 204: Digital Systems Desig 6
Datapath Example: Performig a Microoperatio Microoperatio: R0 R1 + R2 Apply 01 to A select to place cotets of R1 oto Bus A Apply 10 to B select to place cotets of R2 oto B data ad apply 0 to MB select to place B data o Bus B Apply 0010 to G select to perform additio G = Bus A + Bus B Apply 0 to MF select ad 0 to MD select to place the value of G oto BUS D Apply 00 to Destiatio select to eable the Load iput to R0 Apply 1 to Load Eable to force the Load iput to R0 to 1 so that R0 is loaded o the clock pulse (ot show) The overall microoperatio requires 1 clock cycle Write D data Load eable 0 1 2 3 Decoder D address 2 Costat i Destiatio select MB select Bus A KU College of Egieerig Elec 204: Digital Systems Desig V C N Z Load Load Load Load G select 4 Zero Detect MF select R0 R1 R2 R3 MD select 0 1 MUX D Bus D 1 0 MUX B 0 1 MUX F F Bus B 2 2 A data A B A B H select 2 B S 2:0 C i Arithmetic/logic uit (ALU) G A address A select 0 1 MUX 2 3 Fuctio uit Register file S 0 I R Shifter I L 0 H B select B address 0 1 MUX 2 3 B data Address Out Data Out Data I 7
Datapath Example: Key Cotrol Actios for Microoperatio Alteratives Write D data Load eable A address A select B select B address Perform a shift microoperatio apply 1 to MF select Use a costat i a micro- operatio usig Bus B apply 1 to MB select Provide a address ad data for a memory or output write microoperatio apply 0 to Load eable to prevet register loadig Provide a address ad obtai data for a memory or output read microoperatio apply 1 to MD select For some of the above, other cotrol sigals become do't cares 0 1 2 3 Decoder D address 2 Costat i Destiatio select MB select Bus A V C N Z Load Load Load Load G select 4 Zero Detect MF select R0 R1 R2 R3 MD select 0 1 MUX D Bus D 1 0 MUX B 0 1 MUX F F Bus B 2 2 A data A B A B H select 2 B S 2:0 C i Arithmetic/logic uit (ALU) G 0 1 MUX 2 3 Fuctio uit Register file S 0 I R Shifter I L 0 H 0 1 MUX 2 3 B data Address Out Data Out Data I KU College of Egieerig Elec 204: Digital Systems Desig 8
Arithmetic Logic Uit (ALU) I this ad the ext sectio, we deal with detailed desig of typical ALUs ad shifters Decompose the ALU ito: A arithmetic circuit A logic circuit A selector to pick betwee the two circuits Arithmetic circuit desig Decompose the arithmetic circuit ito: A -bit parallel adder A block of logic that selects four choices for the B iput to the adder See ext slide for diagram KU College of Egieerig Elec 204: Digital Systems Desig 9
Arithmetic Circuit Desig (cotiued) There are oly four fuctios of B to select as Y i G = A + Y: Y C i = 0 C i = 1 0 G = A G = A + 1 B G = A + B G = A + B + 1 B G = A + B G = A + B + 1 1 G = A 1 G = A What fuctios are implemeted with carry-i to the adder = 0? =1? C i A X B S 0 S 1 B iput logic Y -bit parallel adder G=X+Y+C i C out KU College of Egieerig Elec 204: Digital Systems Desig 10
Arithmetic Circuit Desig (cotiued) Addig selectio codes to the fuctios of B: The useful arithmetic fuctios are labeled i the table Note that all four fuctios of B produce at least oe useful fuctio KU College of Egieerig Elec 204: Digital Systems Desig 11
Logic Circuit The text gives a circuit implemeted usig a multiplexer plus gates implemetig: AND, OR, XOR ad NOT Here we custom desig a circuit for bit G i by begiig with a truth table orgaized as a K-map ad assigig (S1, S0) codes to AND, OR, etc. G i = S 0 A i B i + S 1 A i B i + S 0 A i B i + S 1 S 0 A i Gate iput cout for MUX solutio > 29 Gate iput cout for above circuit < 20 Custom desig better S 1 S 0 AND OR XOR NOT A i B i 0 0 0 1 1 1 1 0 0 0 0 0 0 1 0 1 0 1 1 1 1 1 1 1 0 0 1 0 0 1 1 0 KU College of Egieerig Elec 204: Digital Systems Desig 12
Arithmetic Logic Uit (ALU) The custom circuit has iterchaged the (S 1,S 0 ) codes for XOR ad NOT compared to the MUX circuit. To preserve compatibility with the text, we use the MUX solutio. Next, use the arithmetic circuit, the logic circuit, ad a 2-way multiplexer to form the ALU. See the ext slide for the bit slice diagram. The iput coectios to the arithmetic circuit ad logic circuit have bee bee assiged to prepare for seamless additio of the shifter, keepig the selectio codes for the combied ALU ad the shifter at 4 bits: Carry-i C i ad Carry-out C i+1 go betwee bits A i ad B i are coected to both uits A ew sigal S 2 performs the arithmetic/logic selectio The select sigal eterig the LSB of the arithmetic circuit, C i, is coected to the least sigificat selectio iput for the logic circuit, S 0. KU College of Egieerig Elec 204: Digital Systems Desig 13
Arithmetic Logic Uit (ALU) (cotiued) C i C i C i + 1 A i B i S 0 S 1 A i B i S 0 S 1 Oe stage of arithmetic circuit 0 2-to-1 MUX G i A i 1 S C i B i S 0 Oe stage of logic circuit S 1 S 2 The ext most sigificat select sigals, S0 for the arithmetic circuit ad S1 for the logic circuit, are wired together, completig the two select sigals for the logic circuit. The remaiig S1 completes the three select sigals for the arithmetic circuit. KU College of Egieerig Elec 204: Digital Systems Desig 14
Combiatioal Shifter Parameters Directio: Left, Right Number of positios with examples: Sigle bit: 1 positio 0 ad 1 positios Multiple bit: 1 to 1 positios 0 to 1 positios Fillig of vacat positios May optios depedig o istructio set Here, will provide iput lies or zero fill KU College of Egieerig Elec 204: Digital Systems Desig 15
Serial output L 4-Bit Basic Left/Right Shifter B 3 B 2 B 1 B 0 I R Serial output R I L S 0 1 2 M U X S 0 1 2 M U X S 0 1 2 M U X S 0 1 2 M U X S 2 H 3 H 2 Serial Iputs: I R for right shift I L for left shift Serial Outputs R for right shift (Same as MSB iput) L for left shift (Same as LSB iput) H 1 H 0 Shift Fuctios: (S 1, S 0 ) = 00 Pass B uchaged 01 Right shift 10 Left shift 11 Uused KU College of Egieerig Elec 204: Digital Systems Desig 16
Datapath Represetatio Have looked at detailed desig of ALU ad shifter i the datapath i slide 8 Here we move up oe level i the hierarchy from that datapath The registers, ad the multiplexer, decoder, ad eable hardware for accessig them become a register file The ALU, shifter, Mux F ad status hardware become a fuctio uit The remaiig muxes ad buses which hadle data trasfers are at the ew level of the hierarchy Costat i MB select FS V C N Z m m 4 D data Write D address 2 m x Register file A address A data A Bus A B address B data Fuctio uit F 1 0 MUX B Bus B B m Address out Data out Data i MD select 0 1 MUX D KU College of Egieerig Elec 204: Digital Systems Desig 17
Datapath Represetatio (cotiued) I the register file: Multiplexer select iputs become A address ad B address Decoder iput becomes D address Multiplexer outputs become A data ad B data Iput data to the registers becomes D data Load eable becomes write The register file ow appears like a memory based o clocked flip-flops (the clock is ot show) The fuctio uit labelig is quite straightforward except for FS Costat i MB select FS V C N Z m m 4 D data Write D address 2 m x Register file A address A data A Bus A B address B data Fuctio uit F 1 0 MUX B Bus B B m Address out Data out Data i MD select 0 1 MUX D KU College of Egieerig Elec 204: Digital Systems Desig 18
Defiitio of Fuctio Uit Select (FS) Codes FS(3:0) G Select, H Select, ad MF i T of FS Codes MF Select G Select(3:0) H Select(3:0) Micr ooperatio 0000 0 0000 XX 0001 0 0001 XX 0010 0 0010 XX 0011 0 0011 XX 0100 0 0100 XX 0101 0 0101 XX 0110 0 0110 XX 0111 0 0111 XX 1000 0 1 X 00 XX 1001 0 1 X 01 XX 1010 0 1 X 10 XX 1011 0 1 X 11 XX 1100 1 XXXX 00 1101 1 XXXX 01 1110 1 XXXX 10 F A F A + 1 F A + B F A + B + 1 F A + B F A + B + 1 F A - 1 F A F A B F A B F A B F A F B F sr B F sl B Boolea Equatios: MFS = F 3 F 2 GS i = F i HS i = F i KU College of Egieerig Elec 204: Digital Systems Desig 19
The Cotrol Word The datapath has may cotrol iputs The sigals drivig these iputs ca be defied ad orgaized ito a cotrol word To execute a microistructio, we apply cotrol word values for a clock cycle. For most microoperatios, the positive edge of the clock cycle is eeded to perform the register load The datapath cotrol word format ad the field defiitios are show o the ext slide KU College of Egieerig Elec 204: Digital Systems Desig 20
The Cotrol Word Fields 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D A AA BA M B FS M D R W Cotrol word Fields DA D Address AA A Address BA B Address MB Mux B FS Fuctio Select MD Mux D RW Register Write The coectios to datapath are show i the ext slide KU College of Egieerig Elec 204: Digital Systems Desig 21
Cotrol Word Block Diagram R W 0 Write D data D A 15 14 13 D address 8 x Register file AA 12 11 10 A address A data B address B data 9 8 7 BA Costat i MB 6 Bus A 1 0 MUX B Bus B Address out Data out A B V C N Z Fuctio uit 4 FS 5 3 2 Data i MD 1 0 1 MUX D Bus D KU College of Egieerig Elec 204: Digital Systems Desig 22
Ecodig of Cotrol W Cotrol Word Ecodig D A, AA, B A MB FS MD R W Fuctio Code Fuctio Code Fuctio Code Fuctio Code Fuctio Code R 0 000 Register 0 F A 0000 Fuctio 0 No write 0 R 1 001 Costat 1 F A + 1 0001 Data I 1 Write 1 R 2 010 F A + B 0010 R 3 011 F A + B + 1 0011 R 4 100 F A + B 0100 R 5 101 F A + B + 1 0101 R 6 110 F A - 1 0110 R 7 111 F A 0111 F A B 1000 F A B 1001 F A B 1010 F A 1011 F B 1100 F sr B 1101 F sl B 1110 KU College of Egieerig Elec 204: Digital Systems Desig 23
Microoperatios for the Datapath - Symbolic Represetatio Micro-operatio DA AA BA MB FS MD RW R1 R2 - R3 R4 sl R6 R7 R7 + 1 R1 R0 + 2 Data out R3 R4 Data i R5 0 R1 R2 R3 Register F = A + B + 1 Fuctio Write R4 R6 Register F = sl B Fuctio Write R7 R7 Register F = A + 1 Fuctio Write R1 R0 Costat F = A + B Fuctio Write R3 Register No Write R4 Data i Write R5 R0 R0 Register F = A B Fuctio Write KU College of Egieerig Elec 204: Digital Systems Desig 24
Microoperatios for the Datapath - Biary Represetatio m Microoperatios from a T Biary C o o Micro-operatio DA AA BA MB FS MD RW R1 R2 - R3 R4 sl R6 R7 R7 + 1 R1 R0 + 2 Data out R3 R4 Data i R5 0 001 010 011 0 100 XXX 110 0 111 111 XXX 0 001 000 XXX 1 XXX XXX 011 0 100 XXX XXX X 101 000 000 0 0101 0 1 1110 0 1 0001 0 1 0010 0 1 XXXX X 0 XXXX 1 1 1010 0 1 KU College of Egieerig Elec 204: Digital Systems Desig 25
KU College of Egieerig Elec 204: Digital Systems Desig 26
Pipelied Datapath Cocered about how fast ca we execute a sigle micro-op Maximum delay values eed to be cosidered Allowable clock rate will be a fuctio of maximal delay for a sigle micro-op Pipelied datapath: break the datapath ito smaller fuctioal blocks ad placed registers betwee each cosecutive blocks KU College of Egieerig Elec 204: Digital Systems Desig 27
Operad-fetch Execute Write-back KU College of Egieerig Elec 204: Digital Systems Desig 28
KU College of Egieerig Elec 204: Digital Systems Desig 29
Executio of pipelie micro-operatios KU College of Egieerig Elec 204: Digital Systems Desig 30