Single Phae Tranormerle Inverter and it Cloed Loop Control or Grid Connected PV Application 1 Pratik D. Rahate & Mini Rajeev 1, Dept. o Electrical Engineering, Fr. C. Rodrigue Intitute o Technology, Navi Mumbai, India Email : 1 Pratikrahate05@gmail.com, minirajeev1@yahoo.com Abtract Grid connected photovoltaic (PV) inverter eed power directly to the grid with the aid o power electronic converter. Recent tudie revealed that tranormer le inverter are preerred in ingle phae grid connected Photovoltaic (PV) application due to lower ize and weight, lower cot, improved eiciency etc. But there are iue with tranormer le grid connected ytem uch a leakage current, direct current injection and aety. Many inverter topologie are tudied in the literature to overcome thee iue [1-3]. Thi paper preent comparion o three commonly ued tranormer le H Bridge topologie, deign o LCL ilter and control trategy or grid ynchronization. Control trategy include Phae Locked Loop (PLL), generation o reerence current (I gre ), and cloed loop current controller to track the reerence current I gre. Simulation wa done in MATLAB- SIMULINK and reult obtained are compared and analyzed. Keyword - Tranormer le inverter, LCL ilter, H5, H6, HERIC, THD, Unipolar Pule Width Modulation, PLL and Current controller. I. INTRODUCTION The application o photovoltaic (PV) grid connected ytem ha been rapidly increaing in recent year or reidential and commercial purpoe. Earlier cot o the PV module wa a major component in uch ytem. But now a the PV module are cheaper, reduction in cot o ytem that include inverter and tranormer i eential. Hence tranormer le ytem i preerred due to reduction in weight, cot, ize and increae in eiciency [1]. Propoed olution in literature include ingle tage and double tage PV grid connected ytem. Single tage PV ytem include, ingle converter to track the maximum power point (MPP) and to interace PV ytem to grid. Thu ingle tage require a tep up tranormer or a high dc input voltage. The inverter control in ingle tage become more complicated to achieve objective uch a MPPT, Grid Synchronization and cloed loop current control. Double tage ytem include two converion tage, dc-dc converion or booting and tracking MPP, and dc-ac inverter or grid interace a hown in Fig.1 [3].Tranormer le PV inverter are pecially deigned or ingle phae low power (<5kW) ytem. The PV ytem connected to the grid hould ollow tandard like IEEE 1547, IEEE 519 and IEC6177 to meet the aety requirement [1]. Fig. 1 : Double-tage grid connected PV ytem. There are ome iue uch a leakage current, DC current injection and aety iue which need to be dealt with tranormer le ytem. Leakage current may low through paraitic capacitance o the PV array due to common mode voltage variation. Leakage current give rie to increaed loe, ditortion in grid current [1]. Thereore leakage current hould be limited below 300mA a peciied by the tandard DIN V VDE V 016-1-1 [5]. Alo DC current i injected in to the grid i tranormer removed, which caue aturation o tranormer preent along the ditribution network. Both the aety requirement or leakage current and DC current injection can be achieved by proper election o inverter topology and control trategie. Thi paper compare three commonly ued tranormer le inverter topologie in term o magnitude o leakage current, total harmonic ditortion (THD), number o component etc. Thee topologie are H5 topology patented by SMA, HERIC topology patented by Sunway and H6 topologie [1, 10].Simulation o thee three topologie are done in MATLAB-SIMULINK or eeding 1kW power to the grid. Reult are preented and analyzed. Reult o Cloed loop control are alo dicued. II. H-BRIDGE TOPOLOGIES In thi ection the baic contruction and the working detail o the mot commonly ued three H-Bridge topologie are dicued. The three topologie are H5, H6 and HERIC topology. All the topologie tudied in thi paper are being tudied or ingle phae ytem. 33
A. H5 Topology It ha an extra witch on dc ide o inverter. Thereore at zero voltage level o inverter output, the PV array i diconnected rom grid. In poitive or negative active mode the current alway low through three witche, while in reewheeling mode the current low through only two witche. H5 topology ha le power device a compared to other two topologie dicued. But the conduction loe are higher a compared to HERIC topology. The circuit diagram o H5 topology i a hown in Fig.. B. HERIC Topology Fig. : H5 Topology The HERIC topology called a Highly Eicient and Reliable Inverter Concept which i deigned by Sunway, which i actually derived rom ull bridge inverter. HERIC topology ha two extra witche on the ac ide. Thee two extra witche bypa the PV array rom the grid and thu contribute to minimization o leakage current. The circuit diagram o HERIC topology i a hown in Fig. 3. C. H6 Topology Fig. 3 : HERIC Topology An H6 topology i derived when an extra witch i placed at the dc ide o the H5 topology, to orm a new current low and thu to reduce conduction lo. Thereore during poitive hal o grid voltage, current low through three witche. While in negative hal o grid voltage the current low through two witche. Thereore PV array can be diconnected rom grid when output o inverter voltage i at zero voltage and thu leakage current can be minimized. Circuit diagram o H6 Topology i a hown in Fig. 4. Fig. 4 : H6 Topology III. CONTROL STRATEGY FOR TRANSFORMERLESS INVERTER In cae o H-Bridge two level inverter, traditional method i to apply the ull-bridge inverter with bipolar or unipolar pule width modulation (PWM). In bipolar PWM one reerence wave i compared with one carrier wave and pule are obtained. In Unipolar PWM, two reerence wave with 180 degree phae hit are been compared with carrier wave and pule are obtained. Bipolar PWM reult in excellent characteritic o leakage current but the current ripple acro inductor and witching loe are large. Unipolar PWM, reult in maller inductor current ripple and higher eiciency but it lead to high leakage current which are not deirable [1]. The olution to above i to diconnect the dc and ac ide o ull bridge inverter in the reewheeling mode o inverter. Unipolar PWM i elected or all topologie where requency o carrier wave i choen a 0 khz. IV. LCL FILTER DESIGN Filter i connected at the output o inverter to improve the quality o output voltage waveorm. LCL ilter provide a better decoupling between ilter and grid impedance and a lower ripple current tre acro the grid inductor. LCL ilter alo provide better attenuation a compared to other ilter with the ame ize with an inductive output[5]. Cut-o requency i an important parameter while deigning the ilter. The cut-o requency o ilter mut be minimally one hal o the witching requency o the converter, becaue the ilter mut have enough attenuation in the range o converter witching requency. Alo Cut-o requency mut have a uicient ditance rom the grid requency. A reitor i added in erie with capacitor to attenuate part o ripple on witching requency in order to avoid reonance [6]. L ac ( V dc V )* DT g (1) I L max Lg rl ac () C 0.05* (3) R C b 1 3* * C (4) re Value o L ac, L g, C and R obtained i given in Table-I. 34
V. CLOSED LOOP CONTROL Control trategy o grid connected inverter conit o PLL, Current control loop and generation o I gre which are dicued in ubequent ection. A. PLL Structure The PLL i ued to ynchronize the inverter output current with grid voltage. PLL imply ene the grid voltage and generate the peak grid voltage and phae angle. The tructure i baed on Single order generalized integrator (SOGI) which i propoed in [8]. A een in Fig. 5, V α i iltered grid ignal and V β a imaginary orthogonal ignal. Uing αβ to dq tranormation and PR regulator a a compenator, etimated angular requency ω e and phae angle θ are obtained. Fig.1 PLL Structure Band pa ilter i ued to ilter any harmonic in grid voltage. To eliminate low order harmonic, limited bandwidth i deired. Thereore Bandwidth i choen to be 40Hz. Q i calculated a 1.5 according to deired bandwidth o 40Hz. B. Reerence Current Generation Inverter output current hould be able track the Grid reerence current (I gre ) according to the variation in power (P re ) and input voltage o inverter (V dc ). Thi grid reerence current i given a in equation 5, where the active power reerence i P re and reactive power i Q re. A only active power i injected to grid, thereore Q re = 0. I gre Pre Qre co( ) (5) V C. Cloed loop current control m Cloed loop current controller a hown in Fig. 6, i deigned uing PR regulator which i introduced in [8]. Reerence grid current i compared with actual grid current. The error e c i then paed through C() which i a PR regulator, u c i the output o PR regulator and m c obtained i the inuoidal ignal which i then compared with carrier ignal in PWM technique. Fig. 6 : Cloed loop current controller The traner unction o PR current controller () a [8]: All the three topologie with LCL Filter at output o inverter and cloed loop current control i imulated and reult are hown in Fig. 7-16. 35 G c G c ( ) K p Ki (6) And traner unction o harmonic compenator to compenate elective harmonic 3 rd, 5th and 7 th a they are dominant harmonic in load current pectrum [9]: Traner unction o Harmonic compenator () G h compenate the elected harmonic 3 rd, 5th and 7 th i a G ( ) h ( h) Kih o VI. SIMULATION DETAILS The imulation model o ingle phae grid connected tranormerle inverter i developed in Mat lab/simulink.the ytem i deigned or eeding 1kW o power to the grid. For thi, PV panel o Open circuit voltage greater than peak value o ingle phae grid voltage i choen. H5, Heric and H6 topologie are imulated and reult are preented. Table I : Comparion o three topologie. (7) Parameter H5 HERIC H6 No. o Level 3 3 3 Total No. Switche 5 6 6 Number o Switche conduct 3 3 Number o Diode 1 with Freewheeling THD (At the output o 76.71 76.71 76.74 Inverter) LOH in Voltage 3 rd 3 rd 5 th Current THD 8.78% 8.78% 8.78 % LOH in Current 3 rd 3rd 5 th No. o controllable 5 6 6 Device Required Leakage Current 3.97m A 4.337m A 3.968 ma i to
A. Simulation reult o H5 Topology Fig.7 and Fig. 8 how the voltage waveorm o the H5 Topology preented in ection-ii. Fig. 11: -Level output voltage HERIC Topology. Fig. 7 : -Level output voltage o H5 Topology. Fig. 1: Output o HERIC Topology with LCL Filter. Fig. 8 : Output voltage o H5 Topology with LCL Filter. B. Simulation reult o H6 Topology Fig.9 and Fig. 10 how the voltage waveorm o the H6 Topology preented in ection-ii. Fig. 9 : -Level output voltage o H6 Topology. Fig. 10 : Ouput o H6 Topology with LCL Filter. C. Simulation reult o HERIC Topology Fig.11 and Fig. 1 how the voltage waveorm o the HERIC Topology preented in ection-ii Parameter DC-Link voltage TABLE II - SYSTEM PARAMETERS. Output Voltage (peak) Output Frequency Inverter Switching requency Output Power o Inverter Linv Lg R C Value 400V 35V 50Hz 0Khz 1KW 8.15mH 6.015mH 15.96 Ω 1.50679μF VII. RESULTS FOR CLOSED LOOP CONTROL OF TRANSFORMERLESS INVERTER Baed on the comparion given in Table II, HERIC topology i elected or the cloed loop control in grid connected ytem. A the cloed-loop current controller cloely track the generated reerence current, the teady tate error i almot zero. A hown in Fig. 14 voltage luctuation occur at 0.04 rom 35 V peak to 300 V peak and back to 35V peak at 0.14, which reult in change o I gre, which i tracked by grid current(i g ) through cloed loop current controller within hal cycle. Cloed loop current control alo achieve the Grid ynchronization a een in Fig. 15. It how the injected grid current ha ame requency and in phae with grid voltage. 36
Fig. 13 : Model o Cloed loop control Fig. 14 : Eect o change in V grid on I g Fig. 15 : Simulation reult o Grid Synchronization VIII. CONCLUSION In thi paper, a comparion i done between tranormerle inverter topologie uch a H5, H6 and HERIC topology. HERIC topology ha lower power loe and higher eiciency a compared to other topologie, hence HERIC topology wa ued or the detailed analyi. Simulation o cloed loop control o HERIC topology i carried out. Cloed loop current controller ha been deigned uing PR controller and Harmonic Compenator, which will track inuoidal reerence and provide good rejection or dominant harmonic. It can be een that the PR controller i able to reduce the teady tate error to zero. The eectivene o the current controller i veriied by changing the amplitude o grid voltage, the reult o which are preented in the paper. IX. REFERENCES [1] Li Zhang, Kai Sun, Yan Xing and Mu Xing, H6 Tranormerle Full-Bridge PV Grid-Tied Inverter, IEEE Tran. Power Electronic, vol. 9, pp. 3, Mar. 014. [] W. Cui, B. Yang, Y. Zhao, W. Li, and X. He, A novel Single-Phae tranormerle gridconnected inverter, in Proc. IEEE IECON, 011, pp. 1067-1071. Science, 1989. [3] Brain K. Perera, Sridhar R. Pulikanti, Philip Ciuo and Sarth Perera, Simulation Model o a Grid- Connected Single-phae Photovoltaic Sytem in PSCAD/EMTDC, in Proc. IEEE POWERCON, 01, pp. 1-6, Nov. 01. [4] W. Yu, J. Lai, H. Qain, and C. Hutchen, Higheiciency MOSFET inverter with H6-type coniguration or photovoltaic noniolated acmodule application, IEEE Tran.Power Electron., vol.6, no.4, pp.153-160, Apr.011. [5] Samuel Araujo and Fernando Antune LCL Filter deign or grid-connected NPC inverter in ohore wind turbine,proc in The 7th International Conerence on Power Electronic, Oct. 007. [6] M. Lierre, F.Blaabjerg, and S.Hanen, Deign and control o an LCL-ilter-baed three-phae active rectiier, IEEE Tran. Ind. Appl., vol. 41, no. 5, pp. 181-191, Sep.-Oct. 005. [7] M. Ciobotaru, R. Teodorecu, and F. Blaabjerg, A new ingle-phae PLL tructure baed on econd order generalized integrator, in Proc. 37 th Annu. IEEE Power Electronic Specialit Con. PESC 06, Jun.006, pp. 1-6. [8] Mihai Ciobotaru, Remu Teodorecu and Frede Blaabjerg, Control o ingle-tage ingle-phae PV inverter, Proc in Power Electronic and Application, 005 European Conerence. [9] Teodorecu R, Blaabjerg F, Lierre M,Loh P.C, Proportional-reonant controller and ilter or grid-connected voltage-ource converter, in Proc. IEE Electric Power Application Vol.153, Iue:5. 37