Design and Control of a Grid-Connected Three- Phase 3-Level NPC Inverter for Building Integrated Photovoltaic Systems

Transcription

1 Deign and Control o a Grid-Connected Three- Phae 3-Level NPC Inverter or Building Integrated Photovoltaic Sytem Youngroc Kim, Hanju Cha, Member, IEEE, Byeong-Mun Song, Senior Member, IEEE, and Kwang Y. Lee, Fellow, IEEE Abtract-- Thi paper preent the deign and control o a grid-connected three-phae 3-level Neutral Point Clamped (NPC) inverter or Building Integrated Photovoltaic (BIPV) ytem. The ytem conit o a PV array, boot DC/DC converter, 3- level NPC inverter, LC ilter and the grid. The 3-level NPC inverter i deigned without a galvanic iolation tranormer and it current controller i developed to minimize leakage current though common-mode voltage loop in the PV ytem. A prototype 3kW NPC inverter with a LC ilter wa abricated and teted, reulting in a low total harmonic ditortion (THD) o le than 3% THD and 97.5% eiciency at the peak load. The detail imulation and tet reult are dicued. Index Term A tranormerle 3-level NPC inverter, PV inverter, current control, LC ilter, BIPV. R I. INTRODUCTION ecently, variou photovoltaic (PV) ytem have been developed and widely intalled or renewable energy generation. Small-ale PV ytem o up to 5kW are emerging in the market o building integrated photovoltaic (BIPV) ytem []. Thee ytem typically require a galvanic iolated three-phae inverter that convert DC voltage rom PV array into AC voltage and eed it into utility grid. The inverter with galvanic iolation can provide olution or aety concern and voltage and current calability, but they can be quite heavy and very expenive. Furthermore, line tranormer and high requency tranormer caue additional loe in the power converion circuit which caue the PV inverter to have poor overall eiciency []. A tranormerle inverter topology i an alternative olution to overcome the aorementioned limitation. However, there are compatibility problem that have been ound in common-mode voltage and leakage current reulting in aety and electromagnetic intererence (EMI) iue. Although thee problem are generic to the ingle-phae inverter with highpeed witching, their eect are magniied by high witching requencie [3]. In act, high-peed witching induced dv/dt and di/dt cauing many o the compatibility problem. The ame problem are een in the three-phae inverter ytem. Thu, the deign hould have two goal. One, to lower R. Y. Kim and H. Cha are with the Department o Electrical Engineering, Chungnam National Univerity, Daejeon, Korea ( rykim@hex.co.kr, hjcha@cnu.ac.kr). B. M. Song and K. Y. Lee are with the Department o Electrical and Computer Engineering, Baylor Univerity, Waco, TX USA ( Ben_Song@baylor.edu; Kwang_Y_Lee@baylor.edu). dv/dt and di/dt to protect the PV array and extend the lie cycle o dc link capacitor and another, to decreae the leakage current through the common-mode path between the PV array and the grid. The deign hould alo reduce EMI. Two main quetion to ak are () how to lower the dv/dt and di/dt and () how to optimize the PWM witching trategie o the inverter and the boot DC/DC converter. A multilevel inverter topology oer a olution to reduce dv/dt voltage tre acro each device by increaing the number o level. It i alo poible to have lower voltage rating in DC link capacitor, reulting in a greater number o choice or low cot capacitor [4]. Furthermore, with advanced witching modulation trategie the PV ytem can eliminate the leakage current though common-mode voltage loop [5]. In thi paper, a three-phae 3-level diode clamped baed neutral point clamped (NPC) inverter with LC ilter i propoed or BIPV ytem. The inverter i newly deigned and controlled by the propoed current controller or the eective active and reactive power control. The new current controller o the inverter with LC ilter i alo deigned to reduce the total harmonic ditortion (THD) to be le than 5%. Variou imulation are perormed with PSIM imulation otware and MATLAB to characterize the common-mode voltage and the leakage current and to deign the current controller and the LC ilter. For validation, a prototype 3kW three-phae 3-level NPC inverter i abricated and teted. II. PHOTOVOLTAIC THREE-PHASE 3-LEVEL INVERTER SYSTEM A. Overall Sytem Coniguration Fig. how the overall coniguration o a tranormerle three-phae 3-level NPC inverter ytem. The ytem conit o a PV array, boot DC/DC converter, 3-level NPC inverter, LC ilter and the grid. The output voltage o the PV array i widely varying rom 350V to 850VDC. For the utility grid, the output o the inverter ytem i deined a a 3kW, 380V, 60Hz. To achieve high ytem eiciency, low witching requencie are choen. The witching requency o the DC/DC converter i elected to be 0 khz and the witching requency o the inverter i elected to be 5 khz. The 3-level NPC inverter can produce ive voltage level on the utility grid; V dc, V dc /, 0, V dc /, and V dc depending on the witching requency. A LC ilter i employed to reduce the voltage ripple, reulting in the low THD //$ IEEE

2 Fig.. Overall coniguration o a tranormerle three-phae 3-level NPC inverter ytem. B. PWM Strategy Since the PV array ha an exiting galvanic connection between the ground o the grid and the PV array, the commonmode voltage loop can orm a reonant circuit with the tray capacitance and leakage inductance during zero-equence witching tate [5-6]. Such a direct tie or low impedance tie rom the PV array and the grid will allow zero-equence current low and caue triple harmonic current into the inverter through the PV module, the ground, and the DC and AC ilter element. Furthermore, when a varying commonmode voltage that i the voltage common to both input PV array and output grid terminal can timulate the reonant circuit, it may generate high common-mode current on the inverter. Thu, thi hould be avoided becaue the ytem may become untable. Three alternative PWM trategie are available or the three-phae NPC inverter; ) Alternative phae oppoition dipoition (APOD), ) Phae oppoition dipoition (POD), and 3) Phae dipoition (PD). Fig. how the PD PWM witching pattern o the one-leg in the 3-level NPC inverter uing phae dipoition method. The elected PD trategy can achieve the lowet harmonic ditortion or the line-to-line voltage o the inverter [6]. Conidering the ytem eiciency, the witching requency o the DC/DC converter i elected or 0 khz to reduce the input current ripple, and 5 khz or the inverter witching requency. The third harmonic injection PWM with two carrier-baed witching i programmed by uing DSP TMS30F8. S S S 3 S 4 V carrier-a V carrier-b Fig.. PD PWM witching pattern o one 3- level inverter phae-leg. V re II. CONTROL AND DESIGN OF THREE-PHASE 3-LEVEL NPC INVERTER WITH LC FILTER A. Control Sytem A control ytem o a grid connected three-phae 3-level NPC inverter ytem a hown in Fig. 3 conit o two main controller; the DC-ide controller or the boot DC/DC converter, and AC-ide controller or the inverter. Thee controller are incorporated with the overall ytem controller in the inverter circuit that i regulated with the DC link voltage, the line-voltage at the point o common coupling (PCC), the inverter current and the grid current. The DC/DC converter i controlled to maintain the ixed DC link voltage enough high to make the inverter operate. To achieve the maximum power rom the PV array, a perturbation and obervation (P&O) method i applied or the maximum power point tracking (MPPT) controller [7]. The output o MPPT generate current reerence o the boot inductor current. Both voltage controller or MPPT and inductor current controller ue controller in thi ytem. The control o the 3-level NPC inverter i to regulate DC voltage and upply power generated by PV array to the grid with low harmonic current. The current controller i implemented in the d-q ynchronou rame and it manipulated variable are generated in the d-q coordinate ytem. Due to the act that phae quantitie are required in the PWM witching pattern, controller reult are tranormed back to the αβ coordinate ytem and then back into phae quantitie [8]. VPV IPV V PV Cin VPV IPV LB MPPT IPV Boot Conv. Gate Driver IPVre VPVre VPV DB - * Phae peak voltage Multilevel Inv. idoe ia* Gate Driver abc dq iqoe ido iqo ian*, ibn*, icn* i derr i qerr ω L L iinv (r,,t) abc C ia i dq Fig. 3. Control block diagram o a 3- level NPC inverter ytem. i? id iq vout (vr, v, vt)? iq* PLL? Look-Up Table in(? t)/ co (? t) B. Current Control The current controller i deigned with two control loop or active and reactive power control [9]. The current controller i ued to regulate the output power o the PV ytem. Each current loop with a proportional-integral () controller regulate the output current to ollow it reerence value. To control the active power, the inverter output power i meaured and compared to the power reerence. The power error eed a controller having a current reerence, i q *, a id* 0 Grid *

3 3 output. To have the d-axi current reerence, i d *, the inverter output voltage alo i meaured and compared to the voltage reerence. In the ame way, the error eed to a current controller and i regulated or reactive power by the gridconnected inverter. The controller output power i controlled by the meaured output power o the inverter and the reerence active power. All controller gain are determined by the input error between the meaured and the reerence voltage. On the other hand, the current reerence deigned with a ynchronou reerence d-q axi rame i oriented to the d-axi rotating at the grid requency. The meaured three phae voltage are tranormed to the ynchronou rotating reerence at the grid requency. And the output o thi controller i ued to generate the current command or the inverter witching. The d-q current command component, i d * and i q * are tranerred to the a-b-c current command component, i an*, i bn* and i cn*, repectively. All gate ignal are produced by thee reerence vector yntheized by pace vector modulation (SVM) algorithm. The current controller G () in the d-q reerence rame i deined a: G Ki ( ) KP () where, K p i the proportional gain, and K i i the integral contant. Since the controller i decompoed into a parallel tructure and the K p, i time invariant, the gain parameter are ineective on the direct and invere equence component o the current error [0]. Thu, the K P hould be interpreted a the um o the proportional gain o the current equence controller. For thi, the controller require a grid voltage eed-orward loop or the dynamic repone. However, thi approach may reult in poor THD o the load current. B. LC Filter A imple L-ilter i widely ued or the inverter to reduce the current harmonic. The L ilter hould be deigned with line requency, o that it require high inductance value, reulting in cot riing in the order o everal kilowatt []. In addition, the dynamic repone may become poor. Thu, LC or LCL ilter coniting o quite mall value o inductor and capacitor can replace the low pa ilter. The LCL ilter need more pace and cot becaue o two inductor. The eiciency, cot, loe, weight and ize are dierent, depending o the ilter type. In thi work, an LC ilter i deigned. In order to deign the LC ilter [-3], irtly the maximum ac current ripple hould be deined. In thi deign, the inverter ide inductance i elected with 5% o the phae current at rated power. Baed on thi guideline, the undamental component o grid current i aumed to be zero. Then, the undamental component o the ilter inductor voltage i to be alo zero. Thu the voltage acro the inductor i deined a: V L V V () inv g where V L i the inductor voltage, V inv i the inverter output voltage and V g i the grid voltage. On the other hand, the phae voltage o the 3-level inverter ha ive level to the mid-point: V dc, V dc /, 0, -V dc /, and V dc. The phae voltage depend on the witching requency that i higher than the grid requency N. Thu, the time average value o the inverter output voltage V av can be deined a contant during the witching time T. In thi cae, the peakto-peak value o the ilter inductor current when uing PD PWM witching method i alo obtained a: Vav d Δ I pp I rpm () L where, I pp and I rpm are the peak-to-peak value and maximum value o ilter inductor current ripple, repectively. L i the ilter inductance value, d i the duty cycle. During the interval o 0 < ωt <π, Vav ( ω t) d( ωt) (3) d ( ω t) ma in( ω ) (4) t where, m a i modulation index. Hence, the maximum inductor current ripple I rpm can be expreed a ollow: I rpm 4L 4L [ d ( ωt) ] [ m in( ωt) ] m in( ωt) a d ( ωt) Auming m a, the maximum value o I rpm i /4 at π/6, 5 π /6. L ΔI (6) 6 ph(max) Thu, baed on witching requency, the value o the inverter- ide inductor wa elected. For the election o the ilter capacitance, it i conidered that the maximum power actor variation een by the grid hould be et to 5%. From the capacitance variation, the overall ytem impedance bae value, Z B, i calculated a: a (5) vg Z B (7) P / 3 C C Av (8) B ωn ZB π N ZB max C B (9) where, v G i the line-to-line rm voltage, P Av i the rated active power, and ω N i the grid requency. In (9), while uing value higher than thi 5%, the power actor o the ytem will be le than the power actor expected. That i, i too large capacitor are elected, the inductor current ripple will be increaed. On the other hand, ince the tranormerle inverter ha the common-mode voltage loop during PWM witching, the reonance circuit i ormed and it reonant requency will be

4 4 calculated under the boundary condition between the witching requency and the control bandwidth [4]: v S_inv S 0 N re (0) where, re i the reonance requency and i deined a: re () π L C Phae voltage [V] v S_grid It i clear that the election o the witching requency hould be ar above the reonant requency o the LC ilter. III. SIMULATION AND VERIFICATION C. Digital Simulation Setup For eective ytem evaluation, the propoed inverter i imulated uing PSIM. Table how Sytem parameter or imulation. Fig. 4(a) how a PSIM baed chematic diagram and Fig. 4(b) how the 3-level inverter output voltage and line-to-line grid voltage waveorm. It can be een that the inverter output voltage o the 3-level inverter ha ive voltage level, V dc, V dc /, 0, -V dc /, and V dc, depending on the witching requency. Fig. 4(c) how the injected rated current to the grid. The imulation reult how that the injected current are inuoidal and THD o current achieve about.5%. Fig. 5 how the Bode plot o the LC ilter which can be een that at low requency when the damped LCL ilter behave like an L ilter o the ame value. The igure alo how the dierence among our dierent type o ilter: L, LC and LCL with no damping reitor, and LCL with damping reitor. A hown, the -40dB attenuation i obtained rom the LC ilter. Thu, the grid-ide current ripple i highly attenuated under the grid impedance variation. TABLE I SIMULATION PARAMETERS Key parameter Value PV Array voltage V dc Grid 60Hz, 3Ф, 380 V (LL) Nominal Power 3kW PWM carrier requency - Inverter - DC-DC converter 5 khz 0 khz LC Filter 4.5mH/ 0µF Gain(dB) Phae(deg) Grid current [A] (b) Grid voltage and 3-level PWM output voltage. (c) i R i S Injected current to the grid (Ir, I, It). Fig. 4. PSIM baed chematic diagram and imulation output i T Frequency repone o ilter L LC no damp LCL no damp LCL damp Frequency (Hz) Fig. 5. Bode plot o the LC ilter. (a) PSIM imulation chematic diagram. Fig. 6 how the current and voltage waveorm between PV terminal and the ground. Equivalent paraitic capacitor, 90.04nF, are connected to the, - terminal o the 3kW PV array. The leakage current to the ground i below 3mA, low enough to not be an electric hock hazard even though there the lo balancing control i not good. The capacitor voltage only have low requency ripple.

5 5 From the reult o imulation, it i clear that the 3-level NPC inverter i a good choice or the tranormerle PV inverter. Even though the NPC inverter ha a low witching requency and a LC ilter, the THD and power quality meet the requirement o IEEE Standard. And aety i alo achieved without tranormer. propoed inverter alo achieved the equal perormance in power quality even though it ha lower witching requency. DC capacitor voltage [V] V Cdc V Cdc DC capacitor current [A] i Cdc & i Cdc Fig. 7. Photo o a prototype 3kW NPC inverter. Fig. 6. Voltage (top) and current (bottom) o the paraitic capacitor between PV terminal and the ground. v R v S v T IV. EXPERIMENTAL RESULTS The overall ytem o grid-connected NPC 3kW inverter, a hown in Fig. 7, i implemented ully in otware adopting a 3-bit ixed-point DSP TMS30F8. The inverter controller i implemented in otware, and the PWM pule are generated through the internal pule generator o the DSP. Voltage and current ignal are meaured by uing the -bit reolution o internal analog-to-digital (A/D) converter in the DSP. Alo a our-channel 8-bit digital-to-analog (D/A) converter ha been ued or debugging. In addition, experimental comparion with the conventional ull-bridge inverter with tranormer have been carried out. Both ytem have ued DSP TMS30F8 control board and the ame control algorithm. But, two dierent gain are elected to optimize the deired repone. However, the conventional ull-bridge inverter ha 0 khz witching requency but the NPC inverter ha 5 khz. The power device are Vincotech IGBT 600V-65A or the NPV inverter. Fig. 8 how the experimental three-level PWM inverter output voltage waveorm on the three phae voltage, v R,v S, and v T. Fig. 9 how the experimental grid waveorm on the rated inverter output current, i R, i S, and i T. A preented, the propoed inverter ytem with LC ilter operate well with the current controller. Fig. 0 (a) and (b) how ytem eiciency and current THD meaured by the WT600 digital meter. It i clear that both inverter achieve a lower THD to meet the requirement to interace the grid network. The tranormerle NPC multilevel inverter ha better eiciency than the conventional inverter, becaue o the lower witching lo and the lack o tranormer lo. It i clear that the propoed 3-level NPC inverter achieved 97.5 % eiciency over a wide range o load and it improved 4% higher than the conventional two-level inverter with tranormer. In the THD comparion, the Fig. 8. Experimental three-level NPC inverter output voltage waveorm (v R,v S, and v T ) v LL i R i S i T Fig. 9. Experimental waveorm o grid voltage V LL and current i R, i S, i T at rated output. Fig. how the emiion noie o AC output that i meaured rom 50kHz to 30MHz. Thi reult meet the requirement o IEC that the intererence voltage require a 79 db (µv) at 50kZ, average 60 db (µv) at 30MHz and how 57.6dB at50khz, lat low at the entire requencie. A can een in Fig., the leakage current through common-mode voltage loop in the PV ytem during zero-tate equence i almot eliminated by uing PD PWM witching method.

6 6 Eiciency 00% 98% 96% 94% 9% 90% 88% 86% (a) Comparion o eiciencie. 3-Level -Level Power deigned and ully implemented in otware or active and reactive power control. Variou imulation were perormed with PSIM imulation otware and MATLAB to characterize the leakage current through common-mode voltage loop in the PV ytem. A phae dipoition (PD) pule-width-modulation (PWM) witching trategy wa applied to the inverter o that the leakage current through the common-mode voltage loop wa reduced, reulting in the reduction o emiion noie. A prototype 3kW NPC inverter with LC ilter demontrated a low total harmonic ditortion (THD) o le than 3% THD and 97.5% eiciency at the peak load. A a reult, it concluded that the propoed tranormerle 3-level NPC inverter with LC ilter can be utilized to eliminate common-mode voltage and the leakage current. The reult i a cot eective olution or mall-cale PV ytem o up to 5kW or building integrated photovoltaic (BIPV) ytem. (b) Comparion o THD o injected current to the grid. Fig. 0. Comparion o eiciencie and THD between tranormerle 3- level NPC inverter and -level inverter with tranormer. IEC Fig.. Conducted noie meaurement o the propoed inverter ytem. V. CONCLUSIONS Thi paper preented the deign and control o a tranormerle grid-connected three-phae 3-level NPC inverter or BIPV ytem. The propoed inverter wa alo characterized and analyzed or the eective grid interace. In addition, a new current controller uing control wa REFERENCES [] T. Kereke, R. Teodorecu, and U. Borup, Tranormerle Photovoltaic Inverter Connected to the Grid, IEEE 007 Applied Power Electronic Conerence, (APEC), 007, pp [] P. Zacharia and B. Burger, Overview o Recent Inverter Development or Grid-Connected PV Sytem, in t European Photovoltaic Solar Conerence, 006, Dreden, Germany. [3] T. Kereke, R. Teodorecu, and M. Lierre, Common mode Voltage in cae o Tranormerle PV inverter connected to the Grid, IEEE 008 International Sympoium on Indutrial Electronic (ISIE), 008, pp [4] B. M. Song and J. S. Lai, A multilevel ot-witching inverter with inductor coupling, IEEE Tran. Ind. Appli., vol. 37, pp , Mar./Apr. 00. [5] B. P. McGrath and D. G. Holme, A comparion o multicarrier PWM trategie or cacaded and neutral point clamped multilevel inverter, IEEE 3 t Annual Power Electronic Specialit Conerence (PESC 00), June 000, pp [6] G. Carrara, S. Gardella, M. Marcheoni, R. Salutari, and G. Sciutto, A New Multilevel PWM Method: A Theoretical Analyi, in IEEE Tranaction on Power Electronic, vol. 7, no. 3, pp , July 99. [7] B. M. Song, Y. Kim, H. Cha, and H. Ree, Current Harmonic Minimization o a Grid-Connected Photovoltaic 500kW Three-Phae Inverter uing PR Control, IEEE 0 Energy Converion Conerence and Expoition (ECCE 0), Phoenix, AZ, Sept. 0. [8] F. Blaabjerg, R. Teodrecu, M. Lierre, and A. V. Timbu, Overview o Control and Grid Synchronization or Ditributed Power Generation Sytem, in IEEE Tran. on Indutrial Elect., vol. 53, no.5, pp , Oct [9] H. R. Seo, M. Park, I. K. Yu, and B. M. Song, Perormance Analyi and Evaluation o a Multiunctional Grid-Connected PV Sytem uing Power Hardware-in-the-Loop Simulation, IEEE 0 Applied Power Electronic Conerence (APEC 0), March 0, pp [0] E. Cengelci, S. U. Sulitijo, B. O. Woom, P. Enjeti, R. Teodorecu, and F. Blaabjerg, A New Medium Voltage PWM Inverter Topology or Adjutable Speed Drive, in Con. Rec. IEEE-IAS Annu. Meeting, St. Loui, MO, Oct. 998, pp [] M. Lierre, F. Blaabjerg, and S. Hanen, Deign and Control o an LCL ilter baed Three-Phae Active Rectiier, in IEEE Tranaction on Indutry Application, vol. 4, no.5, pp. 8 9, ep./oct [] E. Twining and D. G. Holme, Grid Current Regulation o a Three Phae Voltage Source Inverter with an LCL Input Filter, in IEEE Tranaction on Power Electronic, vol. 8, no. 3, pp , May 003. [3] K. H. Ahmed, S. J. Finney, and B. W. William, Paive Filter Deign or Three-Phae Inverter Interacing in Ditribution Generation, Journal o Compatibility in Power Electronic (CPE 07), vol., no., pp. -9, May/June 007. [4] H. Kim and K. H. Kim, Filter deign or grid connected PV inverter, IEEE International Conerence on Sutainable Energy Technologie (ICSET 08), pp , 008.

7 7 VI. BIOGRAPHIES Youngroc Kim received hi B.S. and M.S. degree in Electrical Engineering rom Chungnam National Univerity, Daejeon, Korea, in 990 and 99, repectively, and i currently puruing hi Ph.D. degree at Chungnam National Univerity. From 99 to 999, he wa with LG Indutrial Sytem (LGIS) Anyang, Korea, where he wa engaged in the development o power electronic and UPS. In 000, he co-ounded the HexPower Inc. in Seoul, Korea, and erve a the CTO. Hi interet are in PV ytem deign and development or renewable power electronic ytem. Hanju Cha received the B.S degree in Electrical Engineering rom Seoul National Univerity, Korea, the M.S degree rom Pohang Intitute o Science and Technology, Korea and the Ph.D degree rom Texa A&M Univerity, College Station, TX in 988, 990 and 004, all in electrical engineering. From 990 to 00, he wa with LG Indutrial Sytem, Anyang, Korea, where he wa engaged in the development o power electronic and adjutable peed drive. In 005, he joined the Department o Electrical Engineering, Chungnam National Univerity, Daejeon, Korea. Hi reearch interet are high power converter, ac/dc, dc/ac and ac/ac converter topologie, power quality and utility interace iue or ditributed energy ytem and microgrid. Byeong-Mun Song (M 90, SM 0) received hi B.S. and M.S. degree in Electrical Engineering rom Chungnam National Univerity, Korea, in 986 and 988, repectively, and hi Ph.D. degree in Electrical Engineering rom Virginia Polytechnic Intitute and State Univerity, Blackburg in 00. He wa with Korea Electrotechnology Reearch Intitute and General Atomic. In 004, he etablihed hi ActPower Technologie, San Diego, CA and erved a the CEO/Preident and CTO. In Augut 009, Dr. Song joined the Department o Electrical and Computer Engineering, Baylor Univerity, Waco, Texa. Hi interet are in the deign, control, and implementation o high perormance power converter, motor drive, and power electronic ytem. Dr. Song i a Senior Member o IEEE. Kwang Y. Lee (F 0) received hi B.S. degree in Electrical Engineering rom Seoul National Univerity, Korea, in 964, M.S. degree in Electrical Engineering rom North Dakota State Univerity, Fargo, in 968, and Ph.D. degree in Sytem Science rom Michigan State Univerity, Eat Laning, in 97. He ha been with Michigan State, Oregon State, Univ. o Houton, the Pennylvania State Univerity, and Baylor Univerity, where he i now Proeor and Chairman o the Department o Electrical and Computer Engineering. Hi interet include power ytem control, operation, planning, and intelligent ytem application to power ytem. Dr. Lee i alo a Fellow o IEEE and Editor o IEEE Tranaction on Energy Converion.