Tradeoffs and Optimization in Analog CMOS Design David M. Binkley University of North Carolina at Charlotte, USA A John Wiley & Sons, Ltd., Publication
Contents Foreword Preface Acknowledgmerits List of Symbols and Abbreviations xvii xxi xxiii xxv 1 Introduction 1 1.1 Importance of Tradeoffs and Optimization in Analog CMOS Design 1 1.2 Industry Designers and University Students as Readers 2 1.3 Organization and Overview of Book 3 1.4 Füll or Selective Reading of Book 5 1.5 Example Technologies and Technology Extensions 6 1.6 Limitations of the Methods 6 1.7 Disclaimer 7 PART I MOS Device Performance, Tradeoffs and Optimization for Analog CMOS Design 9 2 MOS Design from Weak through Strong Inversion 11 2.1 Introduction 11 2.2 MOS Design Complexity Compared to Bipolar Design 12 2.3 Bipolar Transistor Collector Current and Transconductance 12 2.4 MOS Drain Current and Transconductance 13 2.4.1 In Weak Inversion 13 2.4.2 In Strong Inversion without Velocity Saturation Effects 14 2.4.3 In Strong Inversion with Velocity Saturation Effects 16 2.4.4 In Moderate Inversion and All Regions of Operation 18 2.5 MOS Drain-Source Conductance 23 2.6 Analog CMOS Electronic Design Automation Tools and Design Methods 25 2.6.1 Electronic Design Automation Tools 25 2.6.2 Design Methods 28 2.6.3 Previous Application of Design Methods Presented in this Book 29 References 30 3 MOS Performance versus Drain Current, Inversion Coefficient, and Channel Length 33 3.1 Introduction 33 3.2 Advantages of Selecting Drain Current, Inversion Coefficient, and Channel Length in Analog CMOS Design 34
viii CONTENTS 3.2.1 Optimizing Drain Current, Inversion Coefficient, and Channel Length Separately 35 3.2.2 Design in Moderate Inversion 35 3.2.3 Design Inclusive of Velocity Saturation Effects 36 3.2.4 Design with Technology Independence 36 3.2.5 Simple Predictions of Performance and Trends 36 3.2.6 Minimizing Iterative Computer Simulations - "PreSPICE" Guidance 37 3.2.7 Observing Performance Tradeoffs - The MOSFET Operating Plane 37 3.2.8 Cross-Checking with Computer Simulation MOS Models 39 3.3 Process Parameters for Example Processes 40 3.3.1 Calculation of Composite Process Parameters 40 3.3.2 DC, Small-Signal, and Intrinsic Gate Capacitance Parameters 42 3.3.3 Flicker Noise and Local-Area DC Mismatch Parameters 44 3.3.4 Gate-Overlap and Drain-Body Capacitance Parameters 45 3.3.5 Temperature Parameters 46 3.4 Substrate Factor and Inversion Coefficient 46 3.4.1 Substrate Factor 47 3.4.2 Inversion Coefficient 50 3.4.2.1 Traditional inversion coefficient 50 3.4.2.2 Fixed-normalized inversion coefficient 51 3.4.2.3 Using the fixed-normalized inversion coefficient in design 52 3.4.2.4 Regions and subregions of inversion 53 3.5 Temperature Effects 55 3.5.1 Bandgap Energy, Thermal Voltage, and Substrate Factor 55 3.5.2 Mobility, Transconductance Factor, and Technology Current 57 3.5.3 Inversion Coefficient 59 3.5.4 Threshold Voltage 60 3.5.5 Design Considerations 60 3.6 Sizing Relationships 61 3.6.1 Shape Factor 62 3.6.2 Channel Width 64 3.6.3 Gate Area and Silicon Cost 65 3.7 Drain Current and Bias Voltages 67 3.7.1 Drain Current 67 3.7.1.1 Without small-geometry effects 68 3.7.1.2 With velocity Saturation effects 70 3.7.1.3 With VFMR effects 72 3.7.1.4 With velocity Saturation and VFMR effects 72 3.7.1.5 The equivalent velocity Saturation voltage 75 3.7.1.6 Predicted and measured values 76 3.7.1.7 The extrapolated threshold voltage 79 3.7.2 Effective Gate-Source Voltage 80 3.7.2.1 Without small-geometry effects 80 3.7.2.2 With velocity Saturation and VFMR effects\ 82 3.7.2.3 Predicted and measured values 86 3.7.2.4 Summary of trends 88 3.7.3 Drain-Source Saturation Voltage 89 3.7.3.1 Physical versus circuit defmition 89 3.7.3.2 Without small-geometry effects 90 3.7.3.3 With velocity Saturation effects 92
CONTENTS ix 3.7.3.4 Predicted and measured values 96 3.7.3.5 Summary of trends 97 3.8 Small-Signal Parameters and Intrinsic Voltage Gain 98 3.8.1 Small-Signal Model and its Application 98 3.8.2 Transconductance 103 3.8.2.1 Without small-geometry effects 103 3.8.2.2 With velocity Saturation and VFMR effects 106 3.8.2.3 Predicted and measured values 111 3.8.2.4 Summary of trends 113 3.8.2.5 Universal g m /I D characteristic in CMOS technologies 115 3.8.2.6 Distortion 115 3.8.3 Body-Effect Transconductance and Relationship to Substrate Factor 121 3.8.3.1 Substrate factor 122 3.8.3.2 Body-effect transconductance 125 3.8.3.3 Predicted and measured values 126 3.8.3.4 Summary of trends 129 3.8.4 Drain Conductance 130 ^3.8.4.1 Due to Channel length modulation 131 3.8.4.2 DuetoDIBL 141 3.8.4.3 Due to hot-electron effects 146 3.8.4.4 Impact of increase near V DSsal 150 3.8.4.5 Measured values 152 3.8.4.6 Summary of trends 161 3.8.5 Intrinsic Voltage Gain 163 3.9 Capacitances and Bandwidth 169 3.9.1 Gate-Oxide Capacitance 169 3.9.2 Intrinsic Gate Capacitances 170 3.9.3 Extrinsic Gate-Overlap Capacitances 173 3.9.4 Drain-Body and Source-Body Junction Capacitances 176 3.9.5 Intrinsic Drain-Body and Source-Body Capacitances 179 3.9.6 Intrinsic Bandwidth 179 3.9.7 Extrinsic and Diode-Connected Bandwidths 185 3.10 Noise 188 3.10.1 Thermal Noise in the Ohmic Region 189 3.10.2 Thermal Noise in the Saturation Region 190 3.10.2.1 Without small-geometry effects 190 3.10.2.2 With small-geometry effects 193 3.10.2.3 Summary of drain-referred and gate-referred thermal noise 194 3.10.3 Flicker Noise 200 3.10.3.1 Carrier density fluctuation model 201 3.10.3.2 Carrier mobility fluctuation model 203 3.10.3.3 Unified, carrier density, correlated mobility fluctuation model 204 3.10.3.4 Flicker-noise prediction from flicker-noise factors 207 3.10.3.5 Reported flicker-noise factors and trends 209 3.10.3.6 Measured and predicted flicker noise 212 3.10.3.7 Summary of gate-referred and drain-referred flicker noise 217 3.10.3.8 Flicker-noise corner frequency 224 3.10.4 Gate, Substrate, and Source Resistance Thermal Noise 227 3.10.5 Channel Avalanche Noise 229 3.10.6 Induced Gate Noise Current 229 3.10.7 Gate Leakage Noise Current 231
CONTENTS 3.11 Mismatch 233 3.11.1 Local-Area DC Mismatch 233 3.11.1.1 Modeling 233 3.11.1.2 Reported mismatch factors and trends 237 3.11.1.3 Edge effects and other model limitations 239 3.11.1.4 Calculating gate-source voltage and drain current mismatch 241 3.11.1.5 Threshold-voltage mismatch increase for non-zero V SB 244 3.11.1.6 Threshold-voltage dominance of mismatch 246 3.11.1.7 Summary of gate-source voltage and drain current mismatch 247 3.11.2 Distance DC Mismatch 254 3.11.2.1 Modeling 254 3.11.2.2 Reported mismatch factors and trends 255 3.11.2.3 Gate-source voltage and drain current mismatch 256 3.11.2.4 Threshold-voltage dominance of mismatch 258 3.11.2.5 Critical spacing for comparable distance and local-area mismatch 258 3.11.3 DC Mismatch Effects on Circuit Performance 259 3.11.3.1 Bandwidth, power, and accuracy tradeoffs in current-mode circuits 259 3.11.3.2 Bandwidth, power, and accuracy tradeoffs in voltage-mode circuits 262 3.11.3.3 Tirning skew in digital circuits 264 3.11.4 Small-Signal Parameter and Capacitance Mismatch 265 3.11.4.1 Transconductance mismatch 265 3.11.4.2 Drain-source conductance mismatch 267 3.11.4.3 Mismatch effects on circuit Performance 268 3.12 Leakage Current 268 3.12.1 Gate Leakage Current and Conductance 268 3.12.1.1 Gate current 269 3.12.1.2 Gate conductance - 273 3.12.2 Gate Leakage Current Effects on Circuit Performance 274 3.12.2.1 Minimum frequency of Operation 274 3.12.2.2 Intrinsic current gain 275 3.12.2.3 Discharge of capacitances 276 3.12.2.4 Noise 277 3.12.2.5 Mismatch 277 3.12.2.6 Summary of tradeoffs 278 3.12.3 Drain-Body and Source-Body Leakage Current 279 3.12.4 Subthreshold Drain Leakage Current 282 References 283 Tradeoffs in MOS Performance, and Design of Differential Pairs and Current Mirrors 295 4.1 Introduction 295 4.2 Performance Trends 296 4.2.1 Exploring Drain Current, Inversion Coefficient, and Channel Length Separately 296 4.2.2 Trends as Inversion Coefficient Increases 297 4.2.3 Trends as Channel Length Increases 300 4.2.4 Trends as Drain Current Increases 302 4.3 Performance Tradeoffs 303 4.3.1 Overview - The MOSFET Operating Plane 303 4.3.2 Region and Level of Inversion - The Inversion Coefficient as a Number Line 304
CONTENTS xi 4.3.3 Tradeoffs Common to All Devices 306 4.3.3.1 Channel width and gate area 309 4.3.3.2 Intrinsic gate capacitance and drain-body capacitance 310 4.3.3.3 Effective gate-source voltage and drain-source Saturation voltage 312 4.3.3.4 Transconductance efficiency and Early voltage 314 4.3.3.5 Intrinsic voltage gain and bandwidth 317 4.3.4 Tradeoffs Specific to Differential-Pair Devices 320 4.3.4.1 Transconductance distortion 320 4.3.4.2 Intrinsic gate capacitance and gate-referred thermal-noise voltage 323 4.3.4.3 Gate-referred flicker-noise voltage and gate-source mismatch voltage 325 4.3.5 Tradeoffs Specific to Current-Mirror Devices 328 4.3.5.1 Intrinsic bandwidth and drain-referred thermal-noise current 329 4.3.5.2 Drain-referred flicker-noise current and drain mismatch current 333 4.3.6 Tradeoffs in Figures of Merit 336 4.3.6.1 Transconductance efficiency and Early voltage 338 4.3.6.2 Intrinsic voltage gain, bandwidth, and gain-bandwidth 338 4.3.6.3 Transconductance efficiency and intrinsic bandwidth 339 4.3.6.4 Thermal-noise efficiency and flicker-noise area efficiency 340 4.3.6.5 Bandwidth, power, and accuracy with DC offset 340 4.3.6.6 Bandwidth, power, and accuracy with thermal noise 342 4.3.6.7 Comparison of bandwidth, power, and accuracy for DC offset and thermal noise 345 4.3.6.8 Extensions 345 4.4 Design of Differential Pairs and Current Minors Using the Analog CMOS Design, Tradeoffs and Optimization Spreadsheet 346 4.4.1 Selecting Inversion Coefficient 348 4.4.2 Selecting Channel Length 353 4.4.3 Selecting Drain Cunent 359 4.4.4 Optimizing for DC, Balanced, and AC Performance 363 4.4.4.1 DC optimization 364 4.4.4.2 AC optimization 366 4.4.4.3 Balanced optimization 366 4.4.4.4 Optimizations at millipower Operation 367 4.4.4.5 Optimizations at micropower Operation 369 4.4.4.6 Summary of micropower Performance considerations 372 4.4.5 Summary Procedure for Device Optimization 372 References 373 PART II Circuit Design Examples Illustrating Optimization for Analog CMOS Design 375 5 Design of CMOS Operational Transconductance Amplifiers Optimized for DC, Balanced, and AC Performance 377 5.1 Introduction 377 5.2 Circuit Description 379 5.2.1 Simple OTAs 379 5.2.2 Cascoded OTAs 380 5.3 Circuit Analysis and Performance Optimization 382 5.3.1 Transconductance 383 5.3.1.1 Simple OTAs 383 5.3.1.2 Cascoded OTAs 384
xü CONTENTS 5.3.1.3 Optimization 384 5.3.2 Output Resistance 385 5.3.2.1 Simple OTAs 385 5.3.2.2 CascodedOTAs 385 5.3.2.3 Optimization 387 5.3.3 Voltage Gain 387 5.3.3.1 Simple OTAs 387 5.3.3.2 Cascoded OTAs 388 5.3.3.3 Optimization 388 5.3.4 Frequency Response 389 5.3.4.1 Simple OTAs 389 5.3.4.2 CascodedOTAs 391 5.3.4.3 Optimization 392 5.3.5 Thermal Noise 393 5.3.5.1 Simple OTAs 393 5.3.5.2 Cascoded OTAs 394 5.3.5.3 Optimization 396 5.3.6 Flicker Noise 397 5.3.6.1 Simple OTAs 397 5.3.6.2 CascodedOTAs 399 5.3.6.3 Optimization 400 5.3.7 Offset Voltage due to Local-Area Mismatch 403 5.3.7.1 Simple OTAs 403 5.3.7.2 Cascoded OTAs 407 5.3.7.3 Optimization 409 5.3.8 Systematic Offset Voltage for Simple OTAs 412 5.3.9 Input and Output Capacitances 413 5.3.9.1 Simple OTAs 413 5.3.9.2 CascodedOTAs 415 5.3.9.3 Optimization 416 5.3.10 Slew Rate 417 5.3.10.1 Simple OTAs 417 5.3.10.2 Cascoded OTAs 417 5.3.10.3 Optimization 417 5.3.11 Input and Output Voltage Ranges 417 5.3.11.1 Simple OTAs 417 5.3.11.2 CascodedOTAs 419 5.3.11.3 Optimization 421 5.3.12 Input, 1 db Compression Voltage 423 5.3.12.1 Simple OTAs 423 5.3.12.2 CascodedOTAs 423 5.3.12.3 Optimization 424 5.3.13 Management of Small-Geometry Effects 424 5.4 Design Optimization and Resulting Performance for the Simple OTAs 425 5.4.1 Selection of MOSFET Inversion Coefficients and Channel Lengths 425 5.4.1.1 DC optimization 429 5.4.1.2 AC optimization 430 5.4.1.3 Balanced optimization 431 5.4.2 Predicted and Measured Performance 431 5.4.2.1 Transconductance, Output resistance, and voltage gain 435 5.4.2.2 Frequency response 439
CONTENTS xiii 5.4.2.3 Thermal noise 439 5.4.2.4 Flicker noise 440 5.4.2.5 Offset voltage due to local-area mismatch 441 5.4.2.6 Systematic offset voltage 442 5.4.2.7 Input and Output capacitances 442 5.4.2.8 Slewrate 442 5.4.2.9 Input and Output voltage ranges 443 5.4.2.10 Input, ldb compression voltage 443 5.4.2.11 Layout area 444 5.4.2.12 Tradeoffs in DC accuracy, low-frequency AC accuracy, voltage gain, and transconductance bandwidth 446 5.4.3 Other Optimizations: Ensuring Input Devices Dominate Thermal Noise 447 5.5 Design Optimization and Resulting Performance for the Cascoded OTAs 448 5.5.1 Selection of MOSFET Inversion Coefficients and Channel Lengths 448 5.5.1.1 DC optimization 451 5.5.1.2 AC optimization 452 5.5.1.3 B alanced optimization 453 5.5.2 Predicted and Measured Performance 453 5.5.2.1 Transconductance, Output resistance, and voltage gain 458 5.5.2.2 Frequency response 461 5.5.2.3 Thermal noise 462 5.5.2.4 Flicker noise 463 5.5.2.5 Offset voltage due to local-area mismatch 464 5.5.2.6 Input and Output capacitances 466 5.5.2.7 Slew rate 467 5.5.2.8 Input and Output voltage ranges 467 5.5.2.9 Input, 1 db compression voltage 468 5.5.2.10 Layout area 468 5.5.2.11 Tradeoffs in DC accuracy, low-frequency AC accuracy, voltage gain, and transconductance bandwidth 470 5.5.2.12 Comparison of Performance tradeoffs with those of simple OTAs 472 5.5.3 Other Optimizations: Ensuring Input Devices Dominate Flicker Noise and Local-Area Mismatch 472 5.5.4 Other Optimizations: Complementing the Design 473 5.6 Prediction Accuracy for Design Guidance and Optimization 474 References 476 Design of Micropower CMOS Preamplifiers Optimized for Low Thermal and Flicker Noise 477 6.1 Introduction 477 6.2 Using the Lateral Bipolar Transistor for Low-Flicker-Noise Applications 478 6.3 Measures of Preamplifier Noise Performance 479 6.3.1 Thermal-Noise Efficiency Factor 479 6.3.2 Flicker-Noise Area Efficiency Factor 482 6.4 Reported Micropower, Low-Noise CMOS Preamplifiers 483 6.5 MOS Noise versus the Bias Compliance Voltage 486 6.5.1 Transconductance in Saturation 486 6.5.2 Drain-Source Resistance and Transconductance in the Deep Ohmic Region 489 6.5.3 Gate Noise Voltage 491 6.5.3.1 Thermal noise 491 6.5.3.2 Flicker noise 493
xiv CONTENTS 6.5.4 Drain Noise Current 494 6.5.4.1 Thermal noise 494 6.5.4.2 Flicker noise 494 6.5.5 Drain Noise Current with Resistive Source Degeneration 496 6.5.5.1 Bias compliance voltage 496 6.5.5.2 Thermal noise 497 6.5.5.3 Flicker noise 500 6.6 Extraction of MOS Flicker-Noise Parameters 504 6.6.1 Preamplifier Input Devices 504 6.6.2 Preamplifier Non-Input Devices 506 6.6.3 Comparisons of Ricker Noise 507 6.7 Differential Input Preamplifier 507 6.7.1 Description 507 6.7.2 Circuit Analysis, Performance Optimization, and Predicted Performance 509 6.7.2.1 Voltage gain 510 6.7.2.2 Frequency response 511 6.7.2.3 Thermal noise 511 6.7.2.4 Thermal noise expressed from DC bias conditions 512 6.7.2.5 Flicker noise 516 6.7.2.6 Flicker noise expressed from DC bias conditions 517 6.7.3 Summary of Predicted and Measured Performance 520 6.7.3.1 MOSFET design selections 521 6.7.3.2 Resulting preamplifier Performance 525 6.7.4 Design Improvements 529 6.8 Single-Ended Input Preamplifier 531 6.8.1 Description 531 6.8.2 Circuit Analysis, Performance Optimization, and Predicted Performance 532 6.8.2.1 Voltage gain 533 6.8.2.2 Frequency response 534 6.8.2.3 Thermal noise 535 6.8.2.4 Thermal noise expressed from DC bias conditions 536 6.8.2.5 Flicker noise 538 6.8.2.6 Flicker noise expressed from DC bias conditions 539 6.8.3 Summary of Predicted and Measured Performance 541 6.8.3.1 MOSFET design selections 541 6.8.3.2 Resulting preamplifier Performance 543 6.8.4 Design Improvements 547 6.9 Prediction Accuracy for Design Guidance and Optimization 549 6.10 Summary of Low-Noise Design Methods and Resulting Challenges in Low-Voltage Processes 550 References 552 Extending Optimization Methods to Smaller-Geometry CMOS Processes and Future Technologies 555 7.1 Introduction 555 7.2 Using the Inversion Coefficient for CMOS Process Independence and for Extension to Smaller-Geometry Processes 556 7.2.1 Universal g m /I D, V EFF, and V DSsal Characteristics Across CMOS Processes 556
CONTENTS 7.2.2 Other Nearly Universal Performance Characteristics Across CMOS Processes 556 7.2.3 Porting Designs Across CMOS Processes 557 7.2.4 Extending Design Methods to Smaller-Geometry Processes 560 7.3 Enhancing Optimization Methods by Including Gate Leakage Current Effects 560 7.4 Using an Inversion Coefficient Measure for Non-CMOS Technologies 561 References 562 Appendix: The Analog CMOS Design, Tradeoffs and Optimization Spreadsheet 565 Index 583