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Table of Contents Table of Contents 1 Overview 1.1 Layout Analysis Floor Plan 1.2 List of Figures 1.3 List of Tables 2 Device Overview 2.1 Introduction 2.2 Device Summary 3 Device Identification 3.1 Package 3.2 Die 4 Functional Layout Analysis 4.1 Overview 4.2 Functional Block Measurements 5 Statement of Measurement Uncertainty and Scope Variation About Chipworks
Overview 1-1 1 Overview 1.1 Layout Analysis Floor Plan This report delivers an overview of an IC s die size, block sizes, and floor plan. A lower level metal die photo is annotated showing the functional blocks on the die at a high level. Clients use this information to compare their own designs and block efficiency and to determine where additional R&D investment is required to leapfrog the competition. Package photographs Package X-ray Depot (bare die) die photograph Die size measurements Annotated metal 1 or poly die photograph showing the major physical blocks on the die Major layout blocks annotated Layout block measurements Table summarizing the L, W, Area, and the percentage die area of each block
Overview 1-2 1.2 List of Figures 3 Device Identification 3.1.1 Package Top 3.1.2 Package Bottom 3.1.3 Package X-Ray 3.2.1 Die Photograph 3.2.2 Die Markings 4 Functional Layout Analysis 4.1.1 Annotated Die Photograph Functional Blocks 1.3 List of Tables 2 Device Overview 2.1.1 Device Identification 2.2.1 Device Summary 4 Functional Layout Analysis 4.2.1 Functional Block Measurements
Device Overview 2-1 2 Device Overview 2.1 Introduction Manufacturer and device profile with key findings summarized. This report contains the following detailed information: Package photographs, package X-ray, die markings, die photograph, and die photographs with annotated functional blocks and memories Measurements of horizontal dimensions of major microstructural features Identification of major functional blocks All of the analyses for this report were performed on two parts, with the following markings: Table 2.1.1 Device Identification Device Package markings Die markings Date code 2.1.1 Device Identification Table 2.1.1 Device Identification
Device Overview 2-2 2.2 Device Summary Table 2.2.1 Device Summary Manufacturer Foundry Part number Type Date code Package markings Package type Package dimensions Die markings Die size (die edge seal) 2.2.1 Device Summary Table 2.2.1 Device Summary
Device Identification 3-1 3 Device Identification 3.1 Package Top and bottom photographs of the package are shown in Figure 3.1.1 and Figure 3.1.2, respectively. The 36 pin exposed pad thin plastic quad flatpack (EP-LQFP) package is 5 mm x 5 mm x 0.6 mm thick. The package bottom image shows the exposed pad, which is 3.6 mm long x 3.6 mm wide. The package markings for this device include: Figure 3.1.1Package Top Figure 3.1.1 Package Top Figure 3.1.1 Package Top
Device Identification 3-2 Figure 3.1.2Package Bottom Figure 3.1.2 Package Bottom pin 1 Figure 3.1.2 Package Bottom
Device Identification 3-3 A plan-view X-ray photograph of the package is shown in Figure 3.1.3, with the location of the exposed pad annotated. Bond wires connect the die to the lead frame. Figure 3.1.3Package X-Ray Figure 3.1.3 Package X-Ray pin 1 exposed pad Figure 3.1.3 Package X-Ray
Device Identification 3-4 3.2 Die Figure 3.2.1 shows a photograph of the die. The die is 3.15 mm x 3.15 mm as measured from the die seals, or 3.18 mm x 3.18 mm for the whole die. This yields a die area of 9.92 mm 2 within the die seals. Bond pads are arranged around the periphery of the die; there are approximately 58 total bond pads with 38 of the pads bonded. Figure 3.2.1Die Photograph Figure 3.2.1 Die Photograph Figure 3.2.1 Die Photograph
Device Identification 3-5 The die markings are shown in Figure 3.2.2, they include: Figure 3.2.2Die Markings Figure 3.2.2 Die Markings Figure 3.2.2 Die Markings
Functional Layout Analysis 4-1 4 Functional Layout Analysis 4.1 Overview Figure 4.1.1 shows the major functional blocks annotated on a photograph of the die. The blocks were divided based on the physical layout features visible on the polysilicon die photograph. The functions of the blocks were estimated based on the pinout information gathered from the product line. This is due to the similarity in the layout features of both devices, as well as the common functions shared by both chips. Other sources of information include product summaries, functional block diagram in the product line, microscopic observation, and previous knowledge and experience. No circuit extraction was carried out to confirm these assumptions. (Basic analysis) Figure 4.1.1Annotated Die Photograph Functional Blocks Figure 4.1.1 Annotated Die Photograph Functional Blocks I/O 1 general analog comparator analog system analog reference 4 kbyte SRAM 16 kbyte flash module I/O 2 CPU core amplifier/ comparator MEM 3 sense cap control IDAC Figure 4.1.1 Annotated Die Photograph Functional Blocks
Functional Layout Analysis 4-2 4.2 Functional Block Measurements Table 4.2.1 shows the physical measurements (length and width) of the major functional blocks analyzed in Figure 4.1.1, as well as the percentage of the total die area they occupy. The die size (die edge seal) measures 3.15 mm x 3.15 mm, for an area of 9.92 mm 2. Some length and width fields are left blank due to irregular block shapes. Table 4.2.1 Functional Block Measurements Functional Block Amplifier/ comparator Analog reference Comparator analog system Type 4.2.1 Functional Block Measurements Length (mm) Width (mm) Total Area (mm 2 ) % of Die Analog 0.53 0.49 0.26 2.6 Analog 0.39 0.64 0.25 2.5 Analog 0.53 1.04 0.55 5.5 General analog Analog 1.47 0.36 0.53 5.3 IDAC Analog 0.78 0.51 0.40 4.0 Sense cap Analog 0.60 0.64 0.38 3.8 control TruTouch Analog 0.83 1.76 1.46 14.7 module 4 kbyte SRAM Logic/memory 0.22 0.64 0.14 1.4 16 kbyte Flash Logic/memory 0.52 1.25 0.65 6.5 MEM3 Logic/memory 0.08 0.09 0.01 0.1 CPU Core Logic Irregular 2.12 21.4 I/O 1 I/O buffers Irregular 1.17 11.7 I/O 2 I/O buffers Irregular 0.71 7.1 Table 4.2.1 Functional Block Measurements
Statement of Measurement Uncertainty and Scope Variation 5-1 5 Statement of Measurement Uncertainty and Scope Variation Measurement Uncertainty Chipworks calibrates length measurements on its scanning electron microscopes (SEM), transmission electron microscope (TEM), and optical microscopes, using measurement standards that are traceable to the International System of Units (SI). Our SEM/TEM cross-calibration standard was calibrated at the National Physical Laboratory (NPL) in the UK (Report Reference LR0304/E06050342/SEM4/190). This standard has a 146 ± 2 nm (± 1.4%) pitch, as certified by NPL. Chipworks regularly verifies that its SEM and TEM are calibrated to within ± 2% of this standard, over the full magnification ranges used. Fluctuations in the tool performance, coupled with variability in sample preparation, and random errors introduced during analyses of the micrographs, yield an expanded uncertainty of approximately ± 5%. The materials analysis reported in Chipworks reports is normally limited to approximate elemental composition, rather than stoichiometry, since calibration of our SEM and TEM-based methods is not feasible. Chipworks will typically abbreviate, using only the elemental symbols, rather than full chemical formulae, usually starting with silicon or the metallic element, then in approximate order of decreasing atomic % (when known). Elemental labels on energy dispersive X-ray spectra (EDS) will be colored red for spurious peaks (elements not originally in sample). Elemental labels in blue correspond to interference from adjacent layers. Secondary ion mass spectrometry (SIMS) data may be calibrated for certain dopant elements, provided suitable standards were available. A stage micrometer, calibrated at the National Research Council of Canada (CNRC) (Report Reference LS-2005-0010), is used to calibrate Chipworks optical microscopes. This standard has an expanded uncertainty of 0.3 µm for the stage micrometer s 100 µm pitch lines. Random errors, during analyses of optical micrographs, yield an expanded uncertainty of approximately ± 5% to the measurements. Scope Variation Due to the nature of reverse engineering, there is a possibility of minor content variation in Chipworks standard reports. Chipworks has a defined table of contents for each standard reports type. At a minimum, the defined content will be included in the report. However, depending on the nature of the analysis, additional information may be provided in a report, as value-added material for our customers.
About Chipworks About Chipworks Chipworks is the recognized leader in reverse engineering and patent infringement analysis of semiconductors and electronic systems. The company s ability to analyze the circuitry and physical composition of these systems makes them a key partner in the success of the world s largest semiconductor and microelectronics companies. Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation earning hundreds of millions of dollars in patent licenses, and saving as much in royalty payments. Research & Development and Product Management rely on Chipworks for success in new product design and launch, saving hundreds of millions of dollars in design, and earning even more through superior product design and faster launches. Contact Chipworks To find out more information on this report, or any other reports in our library, please contact Chipworks at: Chipworks 3685 Richmond Rd. Suite 500 Ottawa, Ontario K2H 5B7 Canada T: 1.613.829.0414 F: 1.613.829.0515 Web site: www.chipworks.com Email: info@chipworks.com Please send any feedback to feedback@chipworks.com