Desauraion Faul Deecion Opocoupler Gae Drive Producs wih Feaure: PLJ, PL0J, PLJ, PL1J and HCPLJ Applicaion Noe 1. Inroducion A desauraion faul deecion circui provides proecion for power semiconducor swiches (IGBT or MOSFETs) agains shorcircui curren evens which may lead o desrucion of hese power swiches. This desauraion of he inverers can also occur due o an insufficien gae drive signal caused by inverer gae driver misperformance or by driver supply volage issues. Oher failure modes ha can poenially cause excessive currens and excessive power dissipaion in he inverers can be due o phase and/or rail supply shor circuis due o incorrec user connecions or bad wiring, conrol signal failures due o noise or compuaional errors, over load condiions induced by he load, and componen failures in he gae drive circuiry. The drasically increased power dissipaion very quickly overheas he power inverer and desroys i. To preven caasrophic damage o he drive, desauraion faul deecion and proecion mus be implemened o reduce or urnoff he overcurrens during he faul condiion. This applicaion noe covers he design of he desauraion faul deecion feaure in Avago inelligen gae drivers. How does he desauraion faul deecion feaure work in Avago drivers? i. Faul Deecion The IGBT collecoremier volage, VCESAT, is moniored by he pin of he gae drive opocoupler (Pin of Figure 1a and 1b). When here is shor circui in an applicaion and a very high curren flow hrough he IGBT, i will go ino he desauraion mode; hence is VCESAT volage will rise. A faul is deeced by he opocoupler gae driver (while he IGBT is on) once his VCESAT volage goes above he inernal desauraion faul deecion hreshold volage, which is ypically.0 V. This faul deecion riggers wo evens: a. Vou of he opocoupler gae driver is slowly brough low in order o sofly urn off he IGBT and preven large di/d induced volage spikes. b. An inernal feedback channel is acivaed which brings he Faul oupu low for he purpose of noifying he microconroller of he faul condiion. A his poin, he microconroller mus ake he appropriae acion o shudown or rese he moor drive. ii. Sof Turnoff This feaure exiss in Avago gae opocouplers, (e.g. PL J, PL0J, PLJ, PL1J and HCPLJ). When a faul is deeced by he feaure, a weak pulldown device in he oupu drive sage will urn on o sofly urn off he IGBT and prevens large di/d induced volages. This device slowly discharges he IGBT gae o preven fas changes in collecor curren ha could cause damaging volage spikes due o sray inducances. During he slow urn off, he large oupu pulldown device remains off unil he oupu volage falls below V, a which ime he large pulldown device clamps he IGBT gae o. iii. Off Sae and Rese During he IGBT off sae, he driver faul deecion circuiry is disabled o preven false faul signals. The faul oupu, Pin of Figure 1a, is pulled down and oupu Pin goes low for he duraion of he faul. In he PLJ and PL0J, he faul is selfrese afer a fixed mue ime of ypically s. In he PLJ and PL1J, he faul is rese a he nex posiive inpu signal o he driver afer a fixed mue ime. The HCPLJ has o be rese exernally hrough he Rese pin (Pin of Figure 1b). For boh case, he rese will only be cleared when deecion has gone o low (shorcircui is cleared). iv. Undervolage Lockou (UVLO) wih Hyseresis The oupu of he opocoupler gae driver and he saus are conrolled by a combinaion of V IN, UVLO, and he deeced IGBT condiion. During power up, he UVLO feaure prevens he applicaion of insufficien gae volage o he IGBT, by forcing he oupu of he opocoupler gae driver low. Once he power supply of he opocoupler gae driver is above he posiive UVLO hresholds, he deecion feaure is he primary source of IGBT proecion. The oupu of he opocoupler is safely brough low once he power supply of he opocoupler falls below he negaive UVLO hreshold level. Hyseresis in he posiive UVLO and negaive UVLO hreshold levels provides an appropriae noise margin for he UVLO deecion and oupu shudown feaures.
1 V S V LED 1 C BLANK R F R D C F C V S C 1 CATHODE 1 ANODE ANODE LAMP CATHODE Figure 1a. Desauraion deecion circui for he PLJ, PL0J, PLJ and PL1J. 1 V IN V IN V LED 1 C BLANK, (0pF) Fas Recovery 0 Ω D C 1 V LED1 V LED1 1 Q HVDC PHASE HVDC Figure 1b. Desauraion deecion circui for he HCPLJ V LED 1 C BLANK R D Zener V (New Threshold ) V F V Z Figure. Zener diode and diode connecion o adjus he hreshold volage
. Basic deecor circui componen selecion For ypical applicaions, he hree exernal componens required o build he circui are he diode, D, resisor, R, and blank capacior, C BLANK. Blanking Time The faul deecion circuiry should remain disabled for a shor ime period following he urnon of he IGBT o allow he collecor volage o fall below he hreshold. The ime period, called he blanking ime, ensures ha here is no nuisance ripping during IGBT urnon. This ime also represens he ime i akes for he driver o deec a faul condiion. The blanking ime is conrolled by he inernal charge curren, I CHG, of 0 A (yp), he volage hreshold, V, and he exernal blank capacior, C BLANK. During operaion, blank capacior is discharged when he driver oupu is low (IGBT off). Tha is, he deecion feaures becomes acive only when he oupu of he gae driver opocoupler is in he high sae, driving he IGBT ino sauraion. When he IGBT is urned on, he capacior sars charging and proecion becomes effecive only if he hreshold is exceeded afer he blanking ime. Blanking Time Capacior Sizing C = BLANK BLANK * V I CHG Blanking ime is deermined using formula (1): The recommended value is 0 pf which gives a blank ime of. μs (Condiion: I CHG = 0 A and V =. V; Page of he HCPLJ daashee AV0EN). HV Blocking Diode and Threshold The diode funcion is o conduc forward curren, allowing sensing of he IGBT s SAT. In a high power applicaion, he pin may be pulled low due o reverse recovery spikes of he freewheeling diode. This reverse recovery spike end o forward bias he subsrae diode (1) of he HCPLJ, which may respond by generaing a false deecion signal. In order o minimize his charging curren and avoid false riggering, i is bes o use very fas reverse recovery ime diodes wih very small reverse parasiic capaciance. Lised in he able below are fasrecovery diodes ha are suiable for use as he diode, D. The deecion hreshold volage of V (ypical) can be reduced by placing a sring of diodes in series or by placing a a low volage zener diode in series wih he diode. For he sring of diodes mehod, V =.0 n * V ( New Threshold ) F For he diode wih Zener Diode mehod, V =.0 V V () ( New Threshold ) F Z where n is he number of diodes, Vz is he zener volage value and V f is he forward volage of diode. This allow he designer o choose he appropriae hreshold volage. Refer o Figure for a diode and zener diode connecion diagram. Resisor The aniparallel diode of he IGBT can have a large insananeous forward volage ransien which exceeds he nominal forward volage of he diode. This may resul in a large negaive volage spike on he pin which will draw a subsanial amoun of curren ou of he driver. To limi he curren level drawn from he gae driver, a resisor can be added (0 recommended) in series wih he diode. The added resisor will no appreciably aler he hreshold or he blanking ime. Oupu Pin The pin (Pin of he PLJ/1J and Pin of he HCPLJ) is an open collecor oupu and requires a pullup resisor, RF (.1 k for PLJ and 1J,. k for HCPLJ), o provide a high level signal. In order o preven he pin from being riggered by high CMR noise, a filer capacior, C F, is included beween he pin and ground (Figure 1a). () Par Number Manufacurer Trr (ns) Max. Reverse Volage Raing, VRRM (Vols) Package Type ERA Fuji Semiconducor 1 00 Axial Leaded MUR10E Moorola 00 0 (axial leaded) UF00 General Semiconducor 00 DO0AL (axial leaded) BYME Philips 00 SOD (axial leaded) BYVE Philips 00 SOD (axial leaded) BYV Philips 00 SOD (surface moun) MURS0T Moorola 00 Case 0A (surface moun)
. Advanced desauraion deecion opic Inernal Charging Curren Source, ICHG, Wide Variaion The blanking capacior charge curren parameer in he daa shee (page of he HCPLJ daashee), is lised as: Blanking Capacior Min Typ Max Unis Charging Curren, I CHG 0 0 A Based on a V desauraion volage hreshold and he above charging curren, we will ge hree differen blanking ime values; minimum, ypical and maximum value. I CHG = C * V () Using he above formula, he hree I CHG values, C BLANK = 0 pf (Figure 1) and V= V, we will have he following blanking imes, 0 pf * V Δ (max) = =. μs μa 0 pf * V Δ (yp) = =. μs 0 μa 0 pf * V Δ (min) = =.1 μs 0 μa For some applicaion, his variaion may no be a problem. However, o minimize he above variaion, several exernal blanking circuis are suggesed in his Applicaion Noe. These are shown in figures, and.. Preven false faul deecion due o negaive volage spikes during power semiconducor swiching operaion One of he siuaions ha may cause he driver o generae a false faul signal is if he subsrae diode of he driver becomes forward biased. This can happen if he reverse recovery spikes coming from he IGBT free wheeling diodes bring he pin below ground. Hence he pin volage will be brough above he hreshold volage. This negaive going volage spikes is ypically generaed by inducive loads or reverse recovery spikes of he IGBT/MOSFETs freewheeling diodes. In order o preven a false faul signal, i is highly recommended o connec a zener diode and schoky diode across he pin and VE pin (e.g. for HCPLJ, beween pin and ). This circui soluion is shown in Figure. The schoky diode will preven he subsrae diode of he gae driver opocoupler from being forward biased while he zener diode (value around. o V) is used o preven any posiive high ransien volage o affec he pin.. Oher mehods of weaking deecion blanking ime Besides he recommended circuis o adjus blanking ime in Figures 1 and, wo oher mehods are inroduced in his applicaion noe. The firs mehod, shown in Figures and, uses addiional capaciors, a resisor and a FET. The second simpler mehod, shown in Figure, requires only one addiional resisor plus scaling of he blanking capacior, CBLANK. The figures show how his can be conneced using a HCPLJ. This circuiry is applicable wih oher similar drivers like he PL J. Each of hese circuiries mus always come wih a schoky diode conneced o pin (cahode) and pin (anode) o preven he device s subsrae diode from being forward biased. In Figures and, he blanking ime is conrolled by wih he ime consan adjused by a capacior value of 0 pf and resisor of 1 k. Designers may choose o adjus his value according o heir desired blanking ime. The *RC ime consan wih 0 pf and 1 k gives a blanking ime of. s. Figure shows anoher concep for an exernal blanking circui. This mehod uses one addiional exernal resisor, R B, conneced from he oupu o he pin. This allows an addiional blanking capacior charging curren componen from he oupu of he gae driver opocoupler hrough R B and adds o he inernal curren source of he gae drive opocoupler. This higher blanking capacior charging curren allows a designer greaer flexibiliy in choosing boh an appropriae value of he blanking capacior and an appropriae curren hrough a choice of he exernal resisor R B. By adjusing he capaciance of he blanking capacior and he addiional curren hrough R B a designer can se a specific, precise blanking ime, and an example calculaion of he blanking ime is shown below: V C RC ( ) = V V (1 e ) i f possible condiions can happen during he On period: A) Desa pin volage is fully discharged by he inernal DMOS during previous Off period During he Off period, he inernal DMOS across Desa pin and pin is urned on o discharge he exernal blanking capacior s volage o prepare for he On period. Assuming ha = V = 0 V C = 1 V R B = 00 C BLANK = 00
Therefore, a = 0, V i = = 0 V A =, V c ( ) = V i V = C = 1 V V c () = V i V (1 e RC ) = C (1 e RC ) V c () = 1(1 e RC ), where = BLANK and V c () = V c ( BLANK ) V c ( BLANK ) = V = 1(1 e BLANK e RC = 1 = 0. 1 BLANK = In(0.) RC BLANK RC ) Wih R B = 00, C BLANK = 00 pf BLANK =. s B) Schoky Diode is forward biased by he freewheeling effec of he IGBT load Due o he freewheeling effec of he IGBT load (moor inducance) before IGBT can urnon, he schoky diode conneced across Desa pin and pin is being forward biased. (Noe: wihou he schoky diode s proecion, he device s subsrae will be forward biased insead and his will cause Desa proecion o be misriggered). Assuming ha = V = 0 V C = 1 V R B = 00 C BLANK = 00 and V F(schoky) = 0. V Therefore, a = 0, V i =0. V A =, V c ( ) = V i V = C = 1 V So, V = C 0. V V c () = V i V (1 e RC ) = 0. (C 0.)(1 e Where = BLANK and V c () = V c ( BLANK ) V c ( BLANK ) = V = 0. (1 0.)(1 e BLANK. e RC = 1 = 0. 1. BLANK = In(0.) RC Wih R B = 00, C BLANK = 00 pf BLANK =. s BLANK RC ) RC ) 1 V IN V IN V LED 1 0pF 0 Ω Fas Recovery D C 1 V LED1 V LED1 1 0pF C 0.1uF TMOS N00LT1 Q HVDC PHASE HVDC V Zener 1NA MBR00 Schoky Diode 0pF C1 R1 1kΩ Exernal Blanking Circui Proecion on Pin Figure. Exernal blanking circui wih a. s nominal blanking delay using he HCPLJ
1 V IN V IN V LED 1 0pF 0 Ω Fas Recovery D C 1 V LED1 V LED1 V Zener 1NA Proecion on Pin 1 MBR00 Schoky Diode 0pF C 0pF C1 R1 1kΩ. Ω 0.1uF TMOS N00LT1 Exernal Blanking Circui nf. Ω Q HVDC PHASE HVDC Figure. Exernal blanking circui wih exernal buffer for high curren drive using he HCPLJ Blanking Circui 1 V IN V IN V LED 1 00pF 0 Fas Recovery D V Zener 1NA Proecion on Pin MBR00 Schoky Diode V LED1 V LED1 C 1 1 0.1uF R B = 1k Q A schoky diode mus be conneced o pin (cahode) and pin (anode) o preven he device's subsrae diode from being forward biased. HVDC PHASE HVDC Figure. Second exernal blanking circui mehod using he HCPLJ
. Experimenal resuls Figure shows experimenal waveforms for he desauraion and sofshudown condiions. Operaing Condiions (Refer o Figure 1a): Swiching Frequency = khz C = 1 V C L = nf (simulae an IGBT load ) = (gae resisance) C BLANK = 0 pf Figure. Channel 1 (Yellow) Inpu LED, Channel (Green) Oupu Volage, Channel (Blue) For produc informaion and a complee lis of disribuors, please go o our web sie: www.avagoech.com Avago, Avago Technologies, and he A logo are rademarks of Avago Technologies in he Unied Saes and oher counries. Daa subjec o change. Copyrigh 0001 Avago Technologies. All righs reserved. AV00EN January, 01