Measurement and modelling of specific behaviors in 28nm FD SOI UTBB MOSFETs of importance for analog / RF amplifiers Denis Flandre, Valeriya Kilchytska, Cecilia Gimeno, David Bol, Babak Kazemi Esfeh, Jean-Pierre Raskin ICTEAM Institute, Université catholique de Louvain Louvain-la-Neuve, Belgium
Context FD-SOI: Unique Analog design opportunity UTBB FD-SOI Total dielectric isolation No channel doping No pocket implant Body Bias: 85mV/V VTh adjust in FD-SOI New design opportunity by controlling analog device characteristics through back gate biasing techniques q V T adjustment Courtesy Ph. Flatresse, ST M, confidential q Improved SCE control (suppression of SUB depletion) Also better other analog performances? And are they correctly modeled? 2
Outline ü Context ü Analog / RF Figures of Merit : from device assessment to circuit design at low frequency ü UTBB specificities & challenges Back gate biasing & FoM variation with frequency ü Wideband RF amplifier Non-linear performance ü Conclusions 3
Analog / RF figures of merit Key-factors @ MOSFET-level Ø f T = g m /(2 π C gg ) Ø f max α f T, R g Ø A v0 = g m /g d = (g m /I d ) V EA const ( f ) @ IC (amplifier)-level Ø GBW = g m /(2 π C L ) = = (g m /I d ) (I d /(2 π C L )) ð depends on q Transconductance g m q Drive current, I d q Output conductance, g d q Early voltage, V EA (V EA =I d /g d ) q g m /I d ratio q Gate capacitance, C gg q Parasitics (C, R) 4
Methodology : device assessment & circuit design g m / I d vs I d,norm G m /I d, V -1 30 20 Baseband applications (High gain, High precision) WI: ~1/S q independent on V T q independent on L (except SCE) q independent on V sub L=30nm V sub = - 2 2 V (2µC ox /ni dnorm ) SI: µ,, n High Frequency applications (High drive current) 10 R sd v sat V. Kilchytska et al. SSE 2012 0 10-12 10-10 10-8 10-6 10-4 Normalized drain current, I d /(W/L), A g m /W g m - A v Analog Metric SCE, R sd V d =1 V V g =V Th +0.6 V Short-L Long-L Intrinsic gain, A v0 q analogue of I on I off digital metric q very visual q independent of V T Allow fair comparison of different devices & at different conditions 5
Comparison of UTBB vs bulk g m / I d g d x 1.1 in SOI (n/µ) / 1.2 g m /I d ~ 10 20 % and g d ~ 2 10 x better in UTTB than bulk depending on length, bias, temperature and frequency conditions 6
Circuit validation at low frequency and power A Fully-Differential OTA in 28 nm UTBB FDSOI CMOS Harikumar et al, ECCTD 2015 10-5 SPICE simulations Total bias current (A) 10-6 Harikumar Bulk FD SOI 40 50 60 70 80 90 DC open-loop gain (db) 7
UTBB Specificities (1) : Effect of V sub g m /W (ms/µm) V sub : S, DIBL, but V T ð I on V sub + : µ ð G m max & I on 1.6 1.2 0.8 0.4 V bg =+1 V V bg + V bg - V bg =-1 V V bg I d, g m V EA g m /I d A v0 + - V bg =0 V 0 20 24 28 32 36 A V0 (db) Trade-off for analog FoM??? V. Kilchytska et al. SSE 2012 q V sub + ð I d norm of 5-10% (sign of µ ) q V sub ð V EA (as a result of DIBL improvement) ð G m /I d (at low V g =V d ) (result of V T shift) ð one can win ~ 5 db (in max A v range) Choice of V sub + or - depends on targeted applications (either I d or A v ) 8
UTBB Specificities (2) : Effect of frequency f S parameters VNA 40 khz 4 GHz S ij Y ij conversion de-embedding g d = Re(Y dd ) L f Frequency-dependent effects: Floating body, self-heating, substrate coupling, g d (f) & g m (f) Gain (f) Performance prediction from DC data is insufficient Quest for wide-f characterization g m A v analogue metric is strongly f-dependent: g m, g d, A v with f S. Makovejev et al. ULSI 2014 9
UTBB Specificities (3) : Effect of self-heating (SH) S G D n p n nogp p-substrate BOX GP SUB with GP S. Makovejev et al. ULSI 2014 GP allows to suppress SUB-related g d (f) variation SH is the main reason of g d (f) variation g d (f) = g intr + Δg d_fb (f) + Δg d_sh (f) + Δg d_sub (f) 10
SH and its effect on Analog FoM in 28 FDSOI vs bulk SH extraction using RF (S-param) method FDSOI Δgd _ SH Rth = I + g V di dt ( d d _ LF d ) d a S. Makovejev et al. EuroSOI-ULIS 2015 g m - A v analogue metric ΔT = R th I d V d bulk S. Makovejev et al. ULIS 2014 R th in bulk lower than in FDSOI C th higher in bulk than in FDSOI due to larger Si volume available for generated heat Temperature rise due to self-heating up to ~32 K in bulk and ~87 K in FDSOI 0 0.25 0.5 Power, mw/µm In spite of stronger SH effect, FDSOI outperform bulk in terms of Analog FoM in entire frequency range While thermal effects are stronger in FDSOI, their influence on device parameters is limited 11
Outline ü Context ü Analog / RF Figures of Merit : from device assessment to circuit design at low frequency ü UTBB specificities & challenges Back gate biasing & FoM variation with frequency ü Wideband RF amplifier Non-linear performance ü Conclusions 12
Wideband LNA Crucial for efficient low-power multi-standard applications such as - UWB (Ultra-Wide Band) - SDR (Software-Defined Radio) High gain up to 6-10 GHz + impedance matching noise figure linearity low area (inductorless) 13
Wideband inductor-less LNA! Noise-cancelling Inductor-less architecture With high linearity For 6-10 GHz Software-Defined Radios In 28nm CMOS G. De Streel et al. IEEE S3S Conf. 2015 UTBB FD-SOI versus Bulk C. Gimeno et al. IMS Conf. 2017 14
Non-linearity figures of merit Considering a memoryless circuit excited by a sinusoidal signal with AC amplitude A with P out OIP3 P out, 1dB 1 db Considering Y = g 1 X + g 2 X 2 + g 3 X 3 Noise floor Dynamic range (DR) IIP3 of an amplifier in open loop is proportional to while in feedback (g 1 / g 3 ) 1/2 P in, 1dB IIP3 P in g 3 2g 2 2 / g 1 15
Transconductance : Bulk vs UTBB SOI Normalized Transconductance, g m1 /(W/L) (µs) 50 40 30 20 10 FDSOI V d = 50 mv 1 V 0 0 10 20 30 Normalized Drain Current, I d /(W/L) (µa) L=30 nm; W= 48.6 µm Bulk V d = V. Kilchytska et al. EUROSOI-ULIS 2017 q Advantage of FDSOI is very clear in below around V Th q V g >V Th +0.2 V Bulk curves stretch out w.r.t FDSOI to higher I d and higher g m1 q Contrarily FDSOI curves quasi-saturate with V d R sd effect??? q RF measurements give : R sd_fdsoi <R sd_bulk q I d -V d curves do not indicate higher R sd in FDSOI Not related to R sd 16
Second-derivative g m2 : Experiments vs SPICE Measurements Spice simulations q Difference in the V d behavior of FDSOI and Bulk devices is not well reproduced by Spice simulations q At low V d : Spice curves agree well for both Bulk and FDSOI devices q With V d : discrepancy is rather strong in FDSOI device q Stretching of bulk curves is well reproduced, but not saturation of FDSOI ones, which in Spice simulations behave in the same way as bulk 17
Silvaco ATLAS simulations : with SH or not Norm. Transconductance, g m1 /(W/L) (µs) 50 40 30 20 SH solid lines nosh dashed lines nosh V d = 10 SH V d = 50 mv 1 V 0 0 10 20 Normalized Drain Current, I d /(W/L) (µa) Normalized 2 nd I d derivative, g m2 /(W/L) 1 10-4 5 10-5 0-5 10-5 SH solid lines nosh dashed lines V d = 50 mv 1 V nosh SH V d = 0 10 20 Normalized Drain Current, I d /(W/L) (µa) strongly suggests that the experimental difference in FDSOI vs Bulk is (at least partially) due to SH Preliminary RF experiments show similar trend V. Kilchytska et al. EUROSOI-ULIS 2017 18
Impact of back-gate bias on non-linearities DC : B. Kazemi et al. ESSDERC 2017 RF : 19
Wideband LNA SPICE simulations Back-bias improvement also obtained in simulations over large process and temperature variations C. Gimeno et al., IEEE S3S Conf. 2017 20
Conclusions ü Analog / RF FoM are excellent in FDSOI to design highperformance amplifiers (gain, bandwidth, power consumption) but specificities require cautious modeling (back bias, frequency, self-heating) ü Non-linearities in FDSOI and Bulk MOSFETs compared by measurements and simulations : Minimization at lower biases in FDSOI w.r.t bulk, which is beneficial for LP applications Application of a positive back-gate (or body) bias in FDSOI allows for further non-linearity reduction ü Next : noise? (see L. Van Brandt s presentation in this workshop) 21
ACKNOWLEDGEMENTS Research projects & Major partners : STM, LETI, IMEC WELCOME Characterization Platform (ELEN/ICTEAM/UCL): https://sites.uclouvain.be/welcome/index.php 22