C M P C h a r a c t e r I z a t I o n S o l u t I o n s 200mm and 300mm Test Patterned Wafers for Bonding Process Applications SKW ASSOCIATES, INC. 2920 Scott Blvd., Santa Clara, CA 95054 Tel: 408-919-0094, Fax: 408-919-0097 SKW Associates, Inc.
SKW Associates, Inc, 2920 Scott Blvd. Santa Clara, CA 95054 Phone (408) 919-0094 Fax (408) 919-0097 Email: skw@testwafer.com http//www.testwafer.com SKWB-200-Ti-ND Wafer Specifications DATE: September 16, 2010 Ti 500A Silicon Ti 500A Cross Sectional View SKWB-200-Ti-ND Mask Floor Plan Patterning Center Die X Location Center Die Y Location Die Size: X Die Size: Y Die Stepping (X /Y) PARAMETER NOMINAL -4.500 mm -4.500 mm 1 / 1 mm TOLERANCE +/- 100 µm +/- 100 µm +/- 10 µm +/- 10 µm +/- 10% Wafers must be patterned all the way to the edges of the wafer, i.e. no area anywhere on the wafer unpatterned. (Under certain stepper operating conditions, 2 mm edge edge exclusion is allowed.)
PARAMETER Line CD Variation (measured on 10 µm structure) Within-Die (measured on 9 trenches) PVD Ti film thickness Within-Die NOMINAL 10 µm 500 Å TOLERANCE Si substrate: p-type (100), resistivity 1-100 ohm-cm, double-side polished
SKW Associates, Inc, 2920 Scott Blvd. Santa Clara, CA 95054 Phone (408) 919-0094 Fax (408) 919-0097 Email: skw@testwafer.com http//www.testwafer.com SKWB-200-Ti Wafer Specifications (for defect characterization) DATE: September 16, 2010 500 µm 4 mm 500 µm 500 µm 4 mm 2 mm 10L/10S 10L/10S 2 mm 2 mm 20L/20S 40L/40S 20L/20S 40L/40S Ti 500A 1000A SiO2 Silicon Ti 500A 2 mm 20/20C 20/20C Cross Sectional View 500 µm SKWB3 logo SKWB-200-Ti Mask Floor Plan Patterning Center Die X Location Center Die Y Location Die Size: X Die Size: Y Die Stepping (X /Y) PARAMETER NOMINAL -4.500 mm -4.500 mm 1 / 1 mm TOLERANCE +/- 100 µm +/- 100 µm +/- 10 µm +/- 10 µm +/- 10% Wafers must be patterned all the way to the edges of the wafer, i.e. no area anywhere on the wafer unpatterned. (Under certain stepper operating conditions, 2 mm edge edge exclusion is allowed.)
PARAMETER Line CD Variation (measured on 10 µm structure) Within-Die (measured on 9 trenches) Pad Oxide thickness Within-Die PVD Ti film thickness Within-Die NOMINAL 10 µm 1000 Å 500 Å TOLERANCE +/- 3 % +/- 3 % Si substrate: p-type (100), resistivity 1-100 ohm-cm, double-side polished
SKW Associates, Inc, 2920 Scott Blvd. Santa Clara, CA 95054 Phone (408) 919-0094 Fax (408) 919-0097 Email: skw@testwafer.com http//www.testwafer.com SKWBS-200 Wafer Specifications DATE: September 16, 2010 Cu Seed 1000A Ti 250A Oxide 500A 1 µm ECP Cu + Anneal Cu Seed 1000A Ti 250A Oxide 500A Silicon Cross Sectional View SKWBS-200 Mask Floor Plan (Additional planarization process (such as Cu CMP, etc.) will be performed upon customer s request) Patterning Center Die X Location Center Die Y Location Die Size: X Die Size: Y Die Stepping (X /Y) PARAMETER NOMINAL -4.500 mm -4.500 mm 1 / 1 mm TOLERANCE +/- 100 µm +/- 100 µm +/- 10 µm +/- 10 µm +/- 10% Wafers must be patterned all the way to the edges of the wafer, i.e. no area anywhere on the wafer unpatterned. (Under certain stepper operating conditions, 2 mm edge edge exclusion is allowed.)
PARAMETER Line CD Variation (measured on 10 µm structure) Within-Die (measured on 9 trenches) TEOS Oxide film thickness Within-Die PVD Ti film thickness Within-Die PVD Cu film thickness Within-Die ECD Cu film thickness Within-Die NOMINAL 10 µm 500 Å 250 Å 1000 Å 1 µm TOLERANCE +/- 3 % +/- 3 % Si substrate: p-type (100), resistivity 1-100 ohm-cm, double-side polished
SKW Associates, Inc, 2920 Scott Blvd. Santa Clara, CA 95054 Phone (408) 919-0094 Fax (408) 919-0097 Email: skw@testwafer.com http//www.testwafer.com SKWB-200 Wafer Specifications (for defect characterization) DATE: September 16, 2010 500 µm 4 mm 500 µm 500 µm 4 mm 2 mm 2 mm 2 mm 10L/10S 20L/20S 40L/40S 10L/10S 20L/20S 40L/40S Cu Seed 1000A Ti 250A Oxide 500A 1 µm ECP Cu + Anneal Cu Seed 1000A Ti 250A Oxide 500A 500A SiN 1000A Oxide Silicon 2 mm 500 µm SKWB3 logo 20/20C 20/20C SKWB-200 Mask Floor Plan Cross Sectional View Additional planarization process (such as Cu CMP, etc.) will be performed upon customer s request) Patterning Center Die X Location Center Die Y Location Die Size: X Die Size: Y Die Stepping (X /Y) PARAMETER NOMINAL -4.500 mm -4.500 mm 1 / 1 mm TOLERANCE +/- 100 µm +/- 100 µm +/- 10 µm +/- 10 µm +/- 10% Wafers must be patterned all the way to the edges of the wafer, i.e. no area anywhere on the wafer unpatterned. (Under certain stepper operating conditions, 2 mm edge edge exclusion is allowed.)
PARAMETER Line CD Variation (measured on 10 µm structure) Within-Die (measured on 9 trenches) Pad Oxide thickness Within-Die SiN film thickness Within-Die TEOS Oxide film thickness Within-Die PVD Ti film thickness Within-Die NOMINAL 10 µm 1000 Å 500 Å 500 Å 250 Å TOLERANCE +/- 3 % +/- 3 % +/- 3 % +/- 3 %
PARAMETER NOMINAL PVD Cu film thickness 1000 Å Within-Die ECD Cu film thickness 1 µm Within-Die Si substrate: p-type (100), resistivity 1-100 ohm-cm, double-side polished TOLERANCE
SKW Associates, Inc, 2920 Scott Blvd. Santa Clara, CA 95054 Phone (408) 919-0094 Fax (408) 919-0097 Email: skw@testwafer.com http//www.testwafer.com SKWB-300-Ti-ND Wafer Specifications DATE: September 16, 2010 Ti 500A Silicon Ti 500A Cross Sectional View SKWB-300-Ti-ND Mask Floor Plan Patterning Center Die X Location Center Die Y Location Die Size: X Die Size: Y Die Stepping (X /Y) PARAMETER NOMINAL -4.500 mm -4.500 mm 1 / 1 mm TOLERANCE +/- 100 µm +/- 100 µm +/- 10 µm +/- 10 µm +/- 10% Wafers must be patterned all the way to the edges of the wafer, i.e. no area anywhere on the wafer unpatterned. (Under certain stepper operating conditions, 4 mm edge edge exclusion is allowed.)
PARAMETER Line CD Variation (measured on 10 µm structure) Within-Die (measured on 9 trenches) PVD Ti film thickness Within-Die NOMINAL 10 µm 500 Å TOLERANCE Si substrate: p-type (100), resistivity 1-100 ohm-cm, double-side polished
SKW Associates, Inc, 2920 Scott Blvd. Santa Clara, CA 95054 Phone (408) 919-0094 Fax (408) 919-0097 Email: skw@testwafer.com http//www.testwafer.com SKWB-300-Ti Wafer Specifications (for defect characterization) DATE: September 16, 2010 500 µm 4 mm 500 µm 500 µm 4 mm 2 mm 10L/10S 10L/10S 2 mm 2 mm 20L/20S 40L/40S 20L/20S 40L/40S Ti 500A 1000A SiO2 Silicon Ti 500A 2 mm 20/20C 20/20C Cross Sectional View 500 µm SKWB3 logo SKWB-300-Ti Mask Floor Plan Patterning Center Die X Location Center Die Y Location Die Size: X Die Size: Y Die Stepping (X /Y) PARAMETER NOMINAL -4.500 mm -4.500 mm 1 / 1 mm TOLERANCE +/- 100 µm +/- 100 µm +/- 10 µm +/- 10 µm +/- 10% Wafers must be patterned all the way to the edges of the wafer, i.e. no area anywhere on the wafer unpatterned. (Under certain stepper operating conditions, 4 mm edge edge exclusion is allowed.)
PARAMETER Line CD Variation (measured on 10 µm structure) Within-Die (measured on 9 trenches) Pad Oxide thickness Within-Die PVD Ti film thickness Within-Die NOMINAL 10 µm 1000 Å 500 Å TOLERANCE +/- 3 % +/- 3 % Si substrate: p-type (100), resistivity 1-100 ohm-cm, double-side polished
SKW Associates, Inc, 2920 Scott Blvd. Santa Clara, CA 95054 Phone (408) 919-0094 Fax (408) 919-0097 Email: skw@testwafer.com http//www.testwafer.com SKWBS-300 Wafer Specifications DATE: September 16, 2010 Cu Seed 1000A Ti 250A Oxide 500A 1 µm ECP Cu + Anneal Cu Seed 1000A Ti 250A Oxide 500A Silicon Cross Sectional View SKWBS-300 Mask Floor Plan (Additional planarization process (such as Cu CMP, etc.) will be performed upon customer s request) Patterning Center Die X Location Center Die Y Location Die Size: X Die Size: Y Die Stepping (X /Y) PARAMETER NOMINAL -4.500 mm -4.500 mm 1 / 1 mm TOLERANCE +/- 100 µm +/- 100 µm +/- 10 µm +/- 10 µm +/- 10% Wafers must be patterned all the way to the edges of the wafer, i.e. no area anywhere on the wafer unpatterned. (Under certain stepper operating conditions, 4 mm edge edge exclusion is allowed.)
PARAMETER Line CD Variation (measured on 10 µm structure) Within-Die (measured on 9 trenches) TEOS Oxide film thickness Within-Die PVD Ti film thickness Within-Die PVD Cu film thickness Within-Die ECD Cu film thickness Within-Die NOMINAL 10 µm 500 Å 250 Å 1000 Å 1 µm TOLERANCE +/- 3 % +/- 3 % Si substrate: p-type (100), resistivity 1-100 ohm-cm, double-side polished
SKW Associates, Inc, 2920 Scott Blvd. Santa Clara, CA 95054 Phone (408) 919-0094 Fax (408) 919-0097 Email: skw@testwafer.com http//www.testwafer.com SKWB-300 Wafer Specifications (for defect characterization) DATE: September 16, 2010 500 µm 4 mm 500 µm 500 µm 4 mm 2 mm 2 mm 2 mm 10L/10S 20L/20S 40L/40S 10L/10S 20L/20S 40L/40S Cu Seed 1000A Ti 250A Oxide 500A 1 µm ECP Cu + Anneal Cu Seed 1000A Ti 250A Oxide 500A 500A SiN 1000A Oxide Silicon 2 mm 500 µm SKWB3 logo 20/20C 20/20C SKWB-300 Mask Floor Plan Cross Sectional View Additional planarization process (such as Cu CMP, etc.) will be performed upon customer s request) Patterning Center Die X Location Center Die Y Location Die Size: X Die Size: Y Die Stepping (X /Y) PARAMETER NOMINAL -4.500 mm -4.500 mm 1 / 1 mm TOLERANCE +/- 100 µm +/- 100 µm +/- 10 µm +/- 10 µm +/- 10% Wafers must be patterned all the way to the edges of the wafer, i.e. no area anywhere on the wafer unpatterned. (Under certain stepper operating conditions, 4 mm edge edge exclusion is allowed.)
PARAMETER Line CD Variation (measured on 10 µm structure) Within-Die (measured on 9 trenches) Pad Oxide thickness Within-Die SiN film thickness Within-Die TEOS Oxide film thickness Within-Die PVD Ti film thickness Within-Die NOMINAL 10 µm 1000 Å 500 Å 500 Å 250 Å TOLERANCE +/- 3 % +/- 3 % +/- 3 % +/- 3 %
PARAMETER NOMINAL PVD Cu film thickness 1000 Å Within-Die ECD Cu film thickness 1 µm Within-Die Si substrate: p-type (100), resistivity 1-100 ohm-cm, double-side polished TOLERANCE
SEMATECH Workshop on 3D Interconnect Metrology Standardized Test Wafers for 3D-IC Wafer Bonding Applications James Hermanowski
Overview Key Performance Metrics for 3D-IC Wafer Level Bonding SUSS Standardized Test Wafer Integration into 300mm Cluster Hardware and Software for Tool Self Diagnostics and Performance Metrology Metrology for Lights Out Manufacturing Test Data and Results Metrology Challenges Present and Future Summary
Key Performance Metrics GOAL to quickly measure and quantify interfaces created by 3D processing for process and equipment qualification Alignment drive minimum via size, electrical resistance Post bond alignment In-situ or in process metrology Measurement wafer face to wafer face, wafer face to wafer back Bond Quality voiding and micro-voiding die yield Bond Strength die yield, die lifetime Shear strength to resist damage during wafer thinning after bond Pull strength to resist mechanical, thermal or packaging stresses Hermiticity die lifetime Penetration of moisture or various undesired molecules Ability to resist degradation or deterioration Protective or seal rings around a die to prevent attack during later processing Electrical Performance yield and resistance
SUSS Standardized Test Wafer Design Key Features of Test Wafers Produced on various wafer types with various materials Si with Cu, Si with oxide, Si with Ti, glass with metal 300mm, 200mm, 150mm and smaller wafer sizes Mirrored design across die and wafer folds onto itself to accommodate wafer bonding 25 different machine readable targets for automated alignment testing Crosses, boxes, grids, dots, Cognex Positive and negative tone Face to Face targets, IR targets, Back to Front targets Human readable targets/verniers Quick check capability Not all companies have quick access to automation for metrology Hermeticity testing features Seven different seal rings with widths 10 microns and higher Via patterns for bond strength testing, capable of electrical testing
Cell Layout SUSS logo Mirrored line 0.5mm Streets 25 individual target designs Seal rings Large solid bonded area Area bonded by vias
Wafer Layout Cu on Si Mirrored line IR Image of Cu patterned test wafer
Combined Machine and Human Readable Targets Combined Target and Vernier, 0.5um
Vernier Examples Center Verniers: ±10micron with 1micron resolution; ±5micron with 0.25micron resolution; ±1micron with 0.1micron resolution Line length: 10, 50, 100, 200, 500, 800 (from left to right) Line length: 10, 50, 100, 200, 500, 800 (from right to left)
Typical Registration Verniers, 0.1 μm First Level Second Level
Reading Verniers In the sample shown below the long bar in the center is the zero point. The point where the red lines overlap exactly with those of the first level, black, defines the measurement. In this case the registration is found at the long central bar which happens to be zero, ie., perfect. If there was mis-registration of +0.4 μm then the forth set of bars to the right of the longer central bar would be perfectly aligned.
Verniers, 0.5 μm steps First Level Second Level
Machine Readable Marks ID Mask Model Wafer Model 4 5 6 7 8 9 10
Metrology by Linewidth Measurement Typically a box within a box type image. First Level Second Level After Alignment A x B x Registration (X-axis) = (A x B x ) /2 Resolution of features are limited by diffraction, especially when using IR
Metrology by Pattern Localization Dimensions In-Plane image after bonding Pattern recognition system locates origin of target #1 and target #2 Registration = Δ Origin (1, 2)
Example of Non-Overlapping Targets 9 μ 33.2 μ 35 μ 33.2 μ 117 μ 10 µ 10 µ Wafer #1 Wafer #2
Cognex Recommended Mark
IR Alignment Considerations Backside polished wafers: Good contrast and easy alignment Backside unpolished Difficult Metrology Heavily doped wafer Very low IR Transmission Very Difficult Metrology
Integration into 300mm Production Cluster Test wafers are integrated into SUSS 300mm tooling Global Calibration Device GCD use is integrated into software for tool self characterization, calibration, or test purposes.
Ceramic Tooling / Fixture (Patent Pending) Supports Industry Leading Submicron Post Bond Alignment Accuracy Transports aligned pair from BA300 to CB300 Delivers reproducible submicron alignment capabilities Maintains wafer to wafer alignment throughout all process and transfer steps No exclusion zone required for clamping No cutouts in chuck for maximum yield Maintains alignment accuracy through temperature ramp Chuck CTE matches Si CTE Increases throughput by reduction of thermal mass
Built-in Global Calibration Global calibration runs a complete bond align cycle Measures the entire process, not just sub-systems Uses the same optics/image processing to calibrate and align Results are fed back to the system for compensation Three different alignment cycle calibration data are stored: Fixture, Fusion, RPP Global Calibration Procedure uses fixture and GCS Wafers Load calibration device/wafers Run alignment cycle Join wafers (Fixture, Fusion, RPP) Re-measure wafer alignment of joined wafers Feedback data to control system Reference = global calibration standard for XYZθ Encompasses correction for all tool movements in XYZ and theta
BA300UHP Bond Aligner Module High Density TSV Manufacturing Path to ±350nm post bond alignment accuracy Allows smaller via diameters and higher via densities Alignment accuracy exceeds TSV Roadmap Global calibration system accounts for all errors and motions in the system Closed loop, real time feedback Microscope tracking and correction Stage axis tracking and correction Face to Face alignments Real time with live images, not historical images Allows tooling with zero cutouts for clamps or optical paths RPP - Radial Pressure Propagation system allows engineering control over bond front during direct bonding
BA300 Components
BA300 Components
Fusion Aligned Wafer Results BA300 LEFT SIDE RIGHT SIDE Left - X Right - X Right - Y Left - Y Post Anneal Alignment Accuracy Wfr Pr1 Wfr Pr2 Lx (um) 0.350 0.250 Ly (um) 0.100 0.150 Rx (um) 0.100 0.150 Ry (um) 0.100 0.100
BA300 Alignment Plot w/ Auto-Metrology
Cu-Cu Test Sequence Submicron Post Bond Alignment SUSS 300mm Cu Patterned Wafers 100KN Bond Force 425C Bond Temperature
Metrology for Lights Out Manufacturing IR images collected from pre-bond and post bond metrology Lights Out operation A tool monitors its own results and takes corrective action to maximize yield Pre-Bond metrology measures the alignment on wafer pairs BEFORE transfer to permanent bonding Recipe defined alignment spec and actions PASS move wafers to bonder FAIL separate and realign FAIL manual intervention FAIL reject wafers Post Bond measures the final result Recipe defined alignment spec and actions PASS tool continues operation FAIL alarm triggers user intervention to prevent more wafers from bonding Available optionally depending upon wafer and equipment configuration
Metrology Gage Study Micron 6 5 4 3 2 1 0-1 -2-3 -4-5 -6-7 -8 Metrology Repeatability Left X Left Y Right X Right Y 0 1 2 3 4 5 6 7 8 9 Run # Worst case example of metrology Bonded wafer pairs measured repeatedly, one reading each day Mixed target style used Wafer 1 visible target Wafer 2 IR target Stage motion required to focus on each target Illumination type changed for each target Ideal case is when both targets are: In the same plane Visible using the same illumination No need to move stages or refocus
Hermiticity Evaluation High resolution SAM image taken after wafer bonding Blue areas show good bond results Green areas at wafer edge show water penetration into die
Hermiticity Evaluation High resolution SAM image taken after additional 48 hours of water soaking Blue areas show good bond results Green areas at wafer edge show water penetration into die Water penetrates deeper into compromised die at wafer edge
Water Penetration of Edge Die High resolution SAM with zoom into edge die region Six die with seal rings Smallest seal ring width penetrated by water
Water Penetration of Edge Die 48 hour exposure to water High resolution SAM with zoom into edge die region Six die with seal rings Two seal rings penetrated by water No other rings penetrated
Metrology Challenges Present and Future Measurement standards for 3D alignments Wafer face aligned to wafer back via last approach and via after bonding Wafer back aligned to wafer back Interface measurements through non-transparent wafers Bond quality and alignments IR absorbing layers, metal layers and heavily doped Silicon Targets are on two different planes 3D spatially. May require visible & IR illumination How to measure when traditional forms of radiation (visible or IR) will not penetrate the wafer stack? Acoustic waves? Electrical?
Summary An approach to quickly measure and quantify interfaces created by 3D processing has been established for process and equipment qualification The approach uses standardized test wafers which contain features to simply and easily quantify processes and equipment used in the manufacture of 3D-IC Alignment drive minimum via size, electrical resistance Bond Quality voiding and micro-voiding die yield Bond Strength die yield, die lifetime Hermiticity die lifetime Technology has been integrated into SUSS XBC300 wafer bond production platform for automated tool calibration/control Challenges remain for simplified metrology of non-transparent wafers and features which cannot be localized in two dimensions