LIN Transceiver TLE7257SJ TLE7257LE Daa Shee Rev. 1.1, 2015-08-20 Auomoive Power
Table of Conens 1 Overview....................................................................... 3 2 Block Diagram................................................................... 4 3 Pin Configuraion................................................................ 5 3.1 Pin Assignmen................................................................... 5 3.2 Pin Definiions and Funcions........................................................ 5 4 Funcional Descripion............................................................ 6 4.1 Operaing Modes................................................................. 7 4.2 Normal Operaion Mode............................................................ 8 4.3 Sandby Mode.................................................................... 9 4.4 Sleep Mode..................................................................... 10 4.5 Bus Wake-up Even.............................................................. 12 4.6 Mode Transiion via inpu....................................................... 13 4.7 Over-Temperaure Proecion....................................................... 14 4.8 Undervolage Deecion........................................................... 15 4.9 Time-ou................................................................... 16 4.10 3.3 V and 5 V Logic Capabiliy...................................................... 16 4.11 Shor Circui.................................................................... 16 5 General Produc Characerisics................................................... 17 5.1 Absolue Maximum Raings........................................................ 17 5.2 Funcional Range................................................................ 18 5.3 Thermal Characerisics........................................................... 18 6 Elecrical Characerisics......................................................... 19 6.1 Funcional Device Characerisics................................................... 19 6.2 Diagrams...................................................................... 23 7 Applicaion Informaion.......................................................... 24 7.1 Applicaion Example.............................................................. 24 7.2 ESD Suscepibiliy according o IEC61000-4-2......................................... 25 7.3 Transien Robusness according o ISO 7637-2......................................... 25 7.4 LIN Physical Layer Compaibiliy.................................................... 25 7.5 Fail-Safe Inpu............................................................... 25 7.6 Pull-up Resisor............................................................. 26 7.7 Compaibiliy wih oher Infineon LIN Transceivers....................................... 27 8 Package Oulines............................................................... 29 9 Revision Hisory................................................................ 30 Daa Shee 2 Rev. 1.1, 2015-08-20
LIN Transceiver TLE7257 TLE7257SJ TLE7257LE 1 Overview Feaures Single-wire LIN ransceiver for ransmission raes up o 20 kbps Complian o ISO 17987-4, LIN Specificaion 2.2A and SAE J2602 Very low curren consumpion in Sleep mode wih wake-up capabiliy Very low leakage curren on he pin Digial I/O levels compaible wih 3.3 V and 5 V microconrollers proeced wih dominan ime-ou funcion and sae check afer mode change o Normal Operaion mode shor o V BAT proecion and shor o handling Over emperaure proecion and supply undervolage deecion Very high ESD robusness, ± 10 kv according o IEC61000-4-2 Opimized for high elecromagneic compaibiliy (EMC); Very low emission and high immuniy o inerference Available in sandard PG-DSO-8 and leadless PG-TSON-8 packages PG-TSON-8 package suppors Auomaed Opical Inspecion (AOI) Green Produc (RoHS complian) AEC Qualified PG-DSO-8 Descripion PG-TSON-8 The TLE7257 is a ransceiver for he Local Inerconnec Nework (LIN) wih inegraed wake-up and proecion feaures. I is designed for invehicle neworks using daa ransmission raes up o 20 kbps. The TLE7257 operae as a bus driver beween he proocol conroller and he physical bus of he LIN nework. Complian o all LIN sandards and wih a wide operaional supply range he TLE7257 can be used in all auomoive applicaions. The usage of differen operaion modes and he oupu allows he TLE7257 o conrol exernal componens like e.g. volage regulaors. In Sleep mode he TLE7257 draws ypically less han 10 μa of quiescen curren while sill being able o wake-up when deecing LIN bus raffic. The very low leakage curren on he pin makes he TLE7257 especially suiable for parially supplied neworks. Based on he Infineon BiCMOS echnology he TLE7257 provides excellen ESD robusness ogeher wih a very high elecromagneic compaibiliy (EMC). The TLE7257 reaches a very low level of elecromagneic emission (EME) wihin a broad frequency range and independen from he baery volage. The TLE7257 is AEC qualified and ailored o wihsand he harsh condiions of he auomoive environmen. Type Package Marking TLE7257SJ PG-DSO-8 7257 TLE7257LE PG-TSON-8 7257 Daa Shee 3 Rev. 1.1, 2015-08-20
Block Diagram 2 Block Diagram 7 8 Inernal Supply V REF 2 R slave R Wake Receiver Mode Conrol V REF Over-emperaure and Over-curren Proecion 6 Transmier Driver Time-ou 4 5 Receiver /2 RF- Filer 1 TLE7257_BLOCK_DIAGRAM Figure 1 Block diagram Daa Shee 4 Rev. 1.1, 2015-08-20
Pin Configuraion 3 Pin Configuraion 3.1 Pin Assignmen 1 8 1 8 N.C. 2 3 7 6 N.C. 2 7 3 6 4 5 4 5 PG-TSON-8 PG-DSO-8 (Top side X-Ray view) TLE7257_PINNING Figure 2 Pin configuraion 3.2 Pin Definiions and Funcions Pin Symbol Funcion 1 Receive daa oupu; Exernal pull-up necessary Moniors he LIN bus signal in Normal Operaion mode Indicaes a wake-up even in Sandby mode 2 Enable inpu; Inegraed pull-down resisor Logical high o selec Normal Operaion mode 3 N.C. No Conneced 4 Transmi daa inpu; Inegraed pull-up curren source Logical low o drive a dominan signal on he LIN bus 5 Ground 6 Bus inpu / oupu; Inegraed LIN slave erminaion 7 V s Baery supply inpu; 100 nf decoupling capacior required 8 Inhibi oupu; Baery supply relaed oupu Acive in Normal Operaion mode and Sandby mode PAD 1) Connec o PCB hea sink area. Do no connec o oher volage poenial han 1)Only for PG-TSON-8 package version (TLE7257LE) Daa Shee 5 Rev. 1.1, 2015-08-20
Funcional Descripion 4 Funcional Descripion The LIN inerface is a single wire, bi-direcional bus, used for in-vehicle neworks. The TLE7257 LIN ransceiver is he inerface beween he microconroller and he physical LIN Bus (see Figure 16). Daa from he microconroller is driven o he LIN bus via he inpu of he TLE7257. The ransmi daa sream on he inpu is convered o a LIN bus signal wih opimized slew raes in order o minimize he elecromagneic emission level of he LIN nework. The oupu reads back he informaion from he LIN bus o he microconroller. The receiver has an inegraed filer nework o suppress noise from he LIN bus and o increase he elecromagneic immuniy level of he ransceiver. The LIN specificaion defines wo valid bus saes (see Figure 3): Dominan sae wih he LIN bus volage level near. Recessive sae wih he LIN bus volage pulled up o he supply volage hrough he bus erminaion. By seing he inpu of he TLE7257 o a logical low signal, he ransceiver generaes a dominan level on he inerface pin. The receiver reads back he signal on he LIN bus and indicaes he dominan LIN bus signal wih a logical low level on he oupu o he microconroller. By seing he inpu o logical high, he ransceiver ses he LIN inerface pin o he recessive level. A he same ime he recessive level on he LIN bus is indicaed by a logical high level on he oupu. Every LIN nework consiss of a maser node and one or more slave nodes. To configure he TLE7257 for maser node applicaions, a erminaion resisor of 1 kω and a diode mus be conneced beween he LIN bus and he power supply (see Figure 16). V CC Recessive Recessive V h_rec V h_dom Dominan V CC Figure 3 LIN bus signals TLE7257_LIN_COMMUNICATION Daa Shee 6 Rev. 1.1, 2015-08-20
TLE7257 Funcional Descripion 4.1 Operaing Modes The TLE7257 has 3 major operaion modes (see Figure 4): Normal Operaion mode Sandby mode Sleep mode Table 1 Operaing modes Mode LIN Bus Terminaion Commens Sleep Low Floaing Disable 1) High 2) 30 kω (ypical) No wake-up reques deeced Sandby Low High High 3) Low 30 kω (ypical) Normal Operaion High High Low High Low High 30 kω (ypical) reflecs he signal on he bus driven by he microconroller 1) The inpu is disabled in Sleep mode and he inernal pull-up curren source is swiched off (see Figure 1). 2) A pull-up resisor o he exernal microconroller supply is required. 3) In case he inpu is open he sae is inernally se o logical high hrough he inernal pull-up curren source. Sleep Mode Power-up 1 : Floaing : Low : Disabled 1) : High 2) 5 2 Wake-up 3 Normal Operaion Mode : High : High 4 Sandby Mode : High : Low : High : Low 1) : The inpu is disabled and he pull-up curren source is swiched off 2) : The oupu is high because of he exernal pull-up resisor TLE7257_MODE_DIAGRAM Figure 4 Operaion mode sae diagram Daa Shee 7 Rev. 1.1, 2015-08-20
Funcional Descripion Table 2 Operaion mode ransiions Number Reason for ransiion Commen 1 Power-on deecion The supply volage rise above he,uv,pon power-on rese level 2 Mode change wih inpu Triggered by logical high level 3 Mode change wih inpu Triggered by logical low level 4 Mode change wih inpu Triggered by logical high level 5 Bus wake-up deecion se low for signalling he bus wake-up even o he microconroller 4.2 Normal Operaion Mode While operaing in Normal Operaion mode he LIN bus receiver and ransmier are acive and suppor daa ransmission raes up o 20 kbps. Daa from he microconroller is ransmied o he LIN bus via he inpu. Simulaneously he receiver deecs he daa sream on he LIN bus and forwards i o he oupu. Normal Operaion mode can be enered from eiher Sleep mode (see Figure 9) or from Sandby mode (see Figure 5), by seing he inpu o logical high. From Normal Operaion mode he TLE7257 can only ener Sleep mode, i is no possible o ener Sandby mode direcly (see Figure 4). The ransiion ime for mode change o Normal Operaion mode MODE specifies he delay beween he hreshold, where he pin deecs a high inpu signal, and he acual mode change of TLE7257 o Normal Operaion mode. V,ON V,OFF Hyseresis MODE MODE : high or low Daa ransmission o,rec : high because of inernal pull-up Daa ransmission : high impedance : high impedance Sandby mode Normal Operaion mode Sleep mode Sandby mode: Sleep mode: Figure 5 The inernal pull-up curren source ses he inpu o logical high in case he inpu is open. The inernal pull-up curren source is swiched off and he inpu is disabled. The inpu is floaing in case he inpu is open. TLE7257_NORMAL_MODE Enering Normal Operaion mode from Sandby mode Daa Shee 8 Rev. 1.1, 2015-08-20
Funcional Descripion While he TLE7257 is in Normal Operaion mode he following funcions are available: The ransmier is urned on; daa on he inpu are driven on he LIN bus. The receiver is urned on; daa on he LIN bus are moniored and signaled on he oupu. The pin is erminaed o via he inernal erminaion resisor R (see Figure 1). The inpu is pulled up via a curren source o he inernal power supply of he TLE7257. The oupu is swiched on. The bus wake-up comparaor is urned off. The wo-level undervolage deecion is acive. In case drops below he undervolage deecion level he TLE7257 blocks he ransmier and receiver. In case drops below he power-on rese level,uv,pon he TLE7257 changes he operaion mode o Sandby mode afer recovery (see Undervolage Deecion on Page 15). The inpu is acive. A low signal on he inpu riggers a ransiion o Sleep. Afer a mode change o Normal Operaion he TLE7257 requires a logical high signal for he ime o,rec on he inpu before releasing he daa communicaion (see Figure 5). The ransmier remains deacivaed as long as he signal on he inpu remains logical low, prevening possible bus communicaion disurbance. 4.3 Sandby Mode The Sandby mode is enered auomaically afer bus wake-up even. In Sandby mode no communicaion o he LIN bus is possible. The ransmier and he receiver are disabled. While he TLE7257 is in Sandby mode he following funcions are available: The ransmier is urned off, he inpu is inacive and he bus oupu is permanen recessive. The receiver is urned off. The oupu indicaes a wake-up even (see Figure 4 and Table 1). The pin is erminaed o via he inernal erminaion resisor R (see Figure 1). The inpu is pulled up wih a curren source o he inernal power supply of he TLE7257. The oupu is swiched on. In Sandby mode only he power-on rese level of he undervolage deecion is acive (see Undervolage Deecion on Page 15). The inpu is acive. A high signal on he inpu riggers a ransiion o Normal Operaion mode (see Figure 5). Daa Shee 9 Rev. 1.1, 2015-08-20
Funcional Descripion 4.4 Sleep Mode Sleep mode is a low power mode wih quiescen curren consumpion reduced o a minimum while he device is sill able o wake-up by a message on he LIN bus. Afer a power-up even he TLE7257 eners Sleep mode by defaul. The pin has an inernal pull-down resisor and he TLE7257 remains in Sleep mode unil he exernal microconroller applies a logical high signal a he inpu. To swich he TLE7257 from Normal Operaion mode o Sleep mode, he inpu has o be se o low. Conversely a logical high signal on he inpu ses he device direcly back o Normal Operaion mode (see Figure 4). The TLE7257 can only ener Sleep mode from Normal Operaion mode. : high or low depending on he signals on he LIN bus : high because of exernal pull-up resisor o he microconroller supply volage Daa ransmission : high impedance Mode : high impedance Normal Operaion mode Sleep mode TLE7257_SLEEP_MODE Figure 6 Enering Sleep mode from Normal Operaion mode While he TLE7257 is in Sleep mode he following funcions are available: The ransmier is urned off. The receiver is urned off. The oupu is erminaed o via he inernal erminaion resisor R (see Figure 1). The oupu is high if a pull-up resisor is conneced o he exernal microconroller supply. The inpu is disabled and he inernal pull-up curren source is swiched off. The oupu is swiched off and is floaing. The bus wake-up comparaor is acive and will cause ransiion o Sandby mode in case of a wake-up even. In Sleep mode only he power-on rese level of he undervolage deecion is acive (see Undervolage Deecion on Page 15). The inpu remains acive. A high signal on he inpu riggers a ransiion o Normal Operaion mode. Daa Shee 10 Rev. 1.1, 2015-08-20
Funcional Descripion,UV,PON Exernal microconroller supply: Off Exernal microconroller supply: On The device remains in Sleep Mode as long he inpu remains low Un-powered Sleep mode TLE7257_POWER_ON Figure 7 Enering Sleep mode afer Power-up Daa Shee 11 Rev. 1.1, 2015-08-20
Funcional Descripion 4.5 Bus Wake-up Even LIN bus signal V V,wk V,wk WK,bus Sleep mode Sandby mode : high impedance 1) : high impedance 1) : high because of inernal pull-up curren source : high because of he exernal pull-up o he microconroller supply volage 1) In case he inpu is open : low indicaes bus wake-up even TLE7257 WAKE Figure 8 Bus wake-up behavior A bus wake-up even, also called remoe wake-up, changes he operaion mode from Sleep mode o Sandby mode. A falling edge on he LIN bus, followed by a dominan bus signal for he ime WK,bus resuls in a bus wakeup even. The mode change o Sandby mode becomes acive wih he following rising edge on he LIN bus. The TLE7257 remains in Sleep mode unil i deecs a sae change on he LIN bus from dominan o recessive (see Figure 8). In Sandby mode a logical low signal on he oupu indicaes a bus wake-up even. Daa Shee 12 Rev. 1.1, 2015-08-20
Funcional Descripion 4.6 Mode Transiion via inpu V,ON V,OFF Hyseresis MODE MODE Daa ransmission o,rec 1) Daa ransmission : high impedance : high impedance Sleep mode Normal Operaion mode Sleep mode 1) The signal is driven from he exernal microconroller TLE7257_ABLE Figure 9 Enering Normal Operaion mode from Sleep mode The inpu is used for operaion mode conrol of he TLE7257. By seing he inpu logical high for he ime MODE while being Sleep or Sandby mode, a ransiion o Normal Operaion mode will be riggered (see Figure 9). The inpu has an inegraed pull-down resisor o ensure he device remains in Sleep or Sandby mode even if he pin is lef open. The inpu has an inegraed hyseresis. A signal ransiion from logical high o low on he inpu changes he operaion mode from Normal Operaion mode o Sleep mode (see Figure 5). The TLE7257 changes he operaion modes regardless of he signal on he pin. In he case of a shor circui beween he LIN bus and, resuling in a permanen dominan signal, he TLE7257 can be se o Sleep mode by seing he inpu o logical low. Afer a mode change o Normal Operaion mode, a logical high signal for he ime o,rec on he inpu is required o release he daa communicaion. Daa Shee 13 Rev. 1.1, 2015-08-20
Funcional Descripion 4.7 Over-Temperaure Proecion The TLE7257 has an inegraed over-emperaure sensor o proec he device agains hermal oversress on he ransmier. In case of an over-emperaure even, he ransmier will be disabled (see Figure 10). An overemperaure even will no cause any mode change and will no be direcly indicaed on he oupu or he inpu. When he juncion emperaure falls below he hermal shu down level T J < T JSD, he ransmier will be reacivaed. Afer an over-emperaure recovery he inpu requires a logical high signal before resaring daa ransmission. A 10 C hyseresis avoids oggling during he emperaure shu down. T JSD (shudown emp.) ΔT (shudown hyseresis) T J Swich-on Overemperaure even Cool down Figure 10 Over-emperaure shu down TLE7257_OVER_TEMPERATURE Daa Shee 14 Rev. 1.1, 2015-08-20
Funcional Descripion 4.8 Undervolage Deecion Supply volage VS Undervolage deecion level,uv,off Undervolage hyseresis,uv,hys Undervolage release level,uv,on Power-on rese level,uv,pon Blanking ime blank,uv Normal Operaion mode Communicaion blocked Normal Operaion mode TLE7257_UNDERVOLTAGE_EARLY Figure 11 Early undervolage deecion The TLE7257 has undervolage deecion on he supply pin wih wo differen hresholds: In Normal Operaion mode he TLE7257 blocks he communicaion beween he LIN bus and he microconroller when deecing undervolage evens. However, no mode change will occur. Afer rises above he undervolage release level,uv,rel, he bus communicaion inerface will be released when he signal on he inpu goes high. See Figure 11. In case he power supply drops down below he power-on rese level,uv,pon he TLE7257 blocks he communicaion beween he LIN bus and he microconroller, and also changes he operaion mode o Sleep mode afer supply recovery. The power-on rese level is acive in all operaion modes. See Figure 12. Supply volage Undervolage deecion level,uv,off Undervolage hyseresis,uv,hys Undervolage release level,uv,on Power-on rese level,uv,pon Blanking ime blank,uv Normal Operaion mode Device unpowered Sleep mode ( = low ) Normal Operaion mode ( = high ) Figure 12 Communicaion blocked Undervolage deecion and power-on rese TLE7257_UNDERVOLTAGE_RESET Daa Shee 15 Rev. 1.1, 2015-08-20
Funcional Descripion 4.9 Time-ou The ime-ou feaure proecs he LIN bus agains permanen blocking in case he logical signal on he inpu is coninuously low, caused by e.g. a malfuncioning microconroller or a shor circui on he prined circui board. In Normal Operaion mode, a logical low signal on he inpu for he ime disables he oupu sage of he ransmier (see Figure 13). The receiver will remain acive and he daa on he bus are sill moniored on he oupu. The TLE7257 will release he oupu sage afer a ime-ou even firs when deecing a logical high signal on he inpu for he ime o,rec. ime-ou due o e.g. microconroller error Recovery of he microconroller error Release afer ime-ou Normal communicaion o,rec Normal communicaion V TLE7257_TXD_TIMEOUT Figure 13 ime-ou 4.10 3.3 V and 5 V Logic Capabiliy The TLE7257 can be used for 3.3 V and 5 V microconrollers. The logic inpus and he oupus are capable o operae wih boh volage levels. The oupu needs an exernal pull-up resisor o he microconroller supply o define he volage level (see Chaper 7.6 Pull-up Resisor on Page 26 and Figure 16). 4.11 Shor Circui The pin of TLE7257 can wihsand shor circuis o eiher or o he power supply. The inegraed overemperaure proecion may disable he ransmier in case of a permanen shor circui on he bus pin is causing he overheaing. Daa Shee 16 Rev. 1.1, 2015-08-20
General Produc Characerisics 5 General Produc Characerisics 5.1 Absolue Maximum Raings Table 3 Absolue Maximum Raings Volages, Currens and Temperaures 1) All volages wih respec o ground; posiive curren flowing ino pin; unless oherwise specified Parameer Symbol Values Uni Noe / Tes Condiion Number Min. Max. Volages Baery supply volage -0.3 40 V LIN Spec 2.2A (Par. 11) 1.1.1 inpu volage V,G -27 40 V 1.1.2 Logic volages a,, V logic -0.3 6.0 V 1.1.3 volage V -0.3 + 0.3 V 1.1.4 Currens Oupu curren a I 0 15 ma 1.2.1 Oupu curren a I -5 5 ma 1.2.2 Temperaures Juncion emperaure T j -40 150 C 1.3.1 Sorage emperaure T s -55 150 C 1.3.2 ESD Suscepibiliy Elecrosaic discharge volage a, Elecrosaic discharge volage all oher pins Elecrosaic discharge volage all pins V ESD -10 10 kv Human Body Model (100 pf via 1.5 kω) 2) 1.4.1 V ESD -4 4 kv Human Body Model 1.4.2 (100 pf via 1.5 kω) 2) V ESD -1 1 kv Charged Device Model 3) 1.4.3 1) No subjec o producion es, specified by design 2) ESD suscepibiliy HBM according o ANSI / ESDA / JEDEC JS-001 3) ESD suscepibiliy, Charged Device Model CDM EIA / JESD 22-C101 or ESDA STM5.3.1 Noe: Sresses above he ones lised here may cause permanen damage o he device. Exposure o absolue maximum raing condiions for exended periods may affec device reliabiliy. Noe: Inegraed proecion funcions are designed o preven IC desrucion under faul condiions described in he daa shee. Faul condiions are considered as ouside normal operaing range. Proecion funcions are no designed for coninuous repeiive operaion. Daa Shee 17 Rev. 1.1, 2015-08-20
General Produc Characerisics 5.2 Funcional Range Table 4 Operaing Range Parameer Symbol Values Uni Noe / Tes Condiion Number Min. Max. Supply Volages Exended supply volage range for operaion Supply volage range for normal operaion Thermal Parameers (ex) 18 40 V Parameer deviaions 2.1.1 possible (nor) 5.5 18 V LIN Spec 2.2A (Par. 10) 2.1.2 Juncion emperaure T j -40 150 C 1) No subjec o producion es, specified by design 1) 2.2.1 Noe: Wihin he funcional range he IC operaes as described in he circui descripion. The elecrical characerisics are specified wihin he condiions given in he relaed elecrical characerisics able. 5.3 Thermal Characerisics Noe: This hermal daa was generaed in accordance wih JEDEC JESD51 sandards. For more informaion, go o www.jedec.org. Table 5 Thermal Resisance 1) Parameer Symbol Values Uni Noe / Tes Condiion Num Min. Typ. Max. ber Thermal Resisance, PG-DSO-8 Package Version Juncion ambien R hja 130 K/W 2) 3.1.1 Thermal Resisance, PG-TSON-8 Package Version Juncion ambien R hja 60 K/W 2) 3.2.1 190 K/W 3) 3.2.2 70 K/W 300 mm 2 heasink on PCB 3) 3.2.3 Thermal Shudown Juncion Temperaure Thermal shudown emperaure T JSD 150 175 200 C 3.3.1 Thermal shudown hyseresis T 10 K 3.3.2 1) No subjec o producion es, specified by design 2) Specified R hja value is according o Jedec JESD51-2,-7 a naural convecion on FR4 2s2p board; The Produc (TLE7257) was simulaed on a 76.2 x 114.3 x 1.5 mm board wih 2 inner copper layers (2 x 70 mm Cu, 2 x 35 mm Cu). Where applicable a hermal via array under he exposed pad conaced o he firs inner copper layer. 3) Specified R hja value is according o Jedec JESD51-3 a naural convecion on FR4 1s0p board; The produc (TLE7257) was simulaed on a 76.2 x 114.3 x 1.5 mm board wih 1 inner copper layer (1 x 70 mm Cu). Daa Shee 18 Rev. 1.1, 2015-08-20
Elecrical Characerisics 6 Elecrical Characerisics 6.1 Funcional Device Characerisics Table 6 Elecrical Characerisics 5.5 V < <18V; R L = 500 Ω; -40 C < T j <150 C; all volages wih respec o ground; posiive curren flowing ino pin; unless oherwise specified. Parameer Symbol Values Uni Noe / Tes Condiion Num Min. Typ. Max. ber Curren Consumpion Curren consumpion a, Recessive sae Curren consumpion a, Dominae sae Curren consumpion a, Sandby mode Curren consumpion a, Sleep mode Curren consumpion a, Sleep mode Curren consumpion a, Sleep mode. Bus shored o I S,rec 0.1 0.6 2.0 ma open, wihou R L ; V = high 4.1.1 I S,dom 0.1 1.1 3.0 ma open, wihou R L ; 4.1.2 V =0V I S,sandby 100 350 900 μa Sandby mode, 4.1.3 V = I S,sleep,yp 1 10 15 μa Sleep mode, T j <40 C; 4.1.4 = 13.5 V; V = I S,sleep 1 10 25 μa Sleep mode, 4.1.5 V = I S,SC_ 100 700 μa Sleep mode, 4.1.6 =13.5V; V =0V Undervolage Deecion Power-on rese level on,uv,pon 4.3 V Rese level for mode change 4.2.1 Undervolage hreshold, on,uv,on 4.7 5.15 5.5 V Rising edge 4.2.2 Undervolage hreshold, off,uv,off 4.4 4.85 5.2 V Falling edge 4.2.3 Undervolage deecion,uv,hys 300 mv 1) 4.2.4 hyseresis Undervolage blanking ime BLANK,UV 10 μs 1) 4.2.5 Receiver Oupu: High level leakage curren I RD,H,leak 5 μa V = 5 V; V = 4.3.1 Low level oupu curren I RD,L 1.3 ma V = 0.4 V; V = 0 V 4.3.2 Transmission Inpu: High level inpu volage range V TD,H 2 6.0 V Recessive sae 4.4.1 Low level inpu volage range V TD,L -0.3 0.8 V Dominan sae 4.4.2 Inpu hyseresis V TD,hys 200 mv 1) 4.4.3 Pull-up curren I TD -60-20 μa V = 0 V; Normal Operaion 4.4.4 mode or Sandby mode Enable Inpu: High level inpu volage range V,ON 2 6.0 V Normal Operaion mode 4.5.1 Daa Shee 19 Rev. 1.1, 2015-08-20
Elecrical Characerisics Table 6 Elecrical Characerisics (con d) 5.5 V < <18V; R L = 500 Ω; -40 C < T j <150 C; all volages wih respec o ground; posiive curren flowing ino pin; unless oherwise specified. Parameer Symbol Values Uni Noe / Tes Condiion Num ber Min. Typ. Max. Low level inpu volage range V,OFF -0.3 0.8 leep mode or Sandby 4.5.2 mode Inpu hyseresis V,hys 200 mv 1) 4.5.3 Pull-down resisance R 15 30 60 kω 4.5.4 Inhibi Oupu: Inhibi volage drop V 1.0 V I = -2.0 ma 4.6.1 Leakage curren I,lk -5.0 5.0 μa Sleep mode; V = 0 V 4.6.2 Bus Receiver: Receiver hreshold volage, recessive o dominan edge V h_dom 0.4 0.44 V 4.7.1 Receiver dominan sae V dom 0.4 V LIN Spec 2.2A (Par. 17) 4.7.2 Receiver hreshold volage, dominan o recessive edge V h_rec 0.56 0.6 V 4.7.3 V LIN Spec 2.2A (Par. 18) 4.7.4 0.5 0.525 V LIN Spec 2.2A (Par. 19) 2) 0.12 0.175 V LIN Spec 2.2A (Par. 20) 3) 0.5 0.6 V 4.7.7 V V V = high ; Receiver recessive sae V rec 0.6 Receiver cener volage V _CNT 0.475 4.7.5 Receiver hyseresis V HYS 0.07 4.7.6 Wake-up hreshold volage V,wk 0.40 Bus Transmier: Bus recessive oupu volage V,ro 0.8 4.8.1 S Open load Bus shor circui curren I _LIM 40 85 125 ma V = 13.5 V; 4.8.2 LIN Spec 2.2A (Par. 12); Leakage curren I _NO_ -1-0.5 ma = 0 V; V =-12V; 4.8.3 LIN Spec 2.2A (Par. 15) Leakage curren I _NO_BAT 1 5 μa = 0 V; V = 18 V; 4.8.4 LIN Spec 2.2A (Par. 16) Leakage curren I _PAS_do -1-0.5 ma = 18 V; V = 0 V; 4.8.5 m LIN Spec 2.2A (Par. 13) Leakage curren I _PAS_rec 1 5 μa = 8 V; V = 18 V; 4.8.6 Forward volage serial diode erdiode 0.4 1.0 V I SerDiode = 75 μa; 4.8.7 LIN Spec 2.2A (Par. 21) Bus pull-up resisance R slave 20 40 60 kω LIN Spec 2.2A (Par. 26) 4.8.8 Daa Shee 20 Rev. 1.1, 2015-08-20
Elecrical Characerisics Table 6 Elecrical Characerisics (con d) 5.5 V < <18V; R L = 500 Ω; -40 C < T j <150 C; all volages wih respec o ground; posiive curren flowing ino pin; unless oherwise specified. Parameer Symbol Values Uni Noe / Tes Condiion Num ber Min. Typ. Max. Bus dominan oupu volage maximum load Dynamic Transceiver Characerisics Propagaion delay: LIN bus dominan o low LIN bus recessive o high V,do rx_pdf 1 rx_pdr 1 3.5 3.5 1.4 2.0 6 6 V V μs μs V = 0 V; R L = 500 Ω; =7 V; =18 V; LIN Spec 2.2A (Par. 31) R = 2.4 kω; C = 20 pf Receiver delay symmery rx_sym -2 2 μs LIN Spec 2.2A (Par. 32) rx_sym = rx_pdf - rx_pdr ; R = 2.4 kω; C = 20 pf 4.9.2 Dominan ime for bus wake-up WK,bus 30 150 μs 4.9.3 Delay ime for mode change MODE 50 μs 4) 4.9.4 ime-ou 8 18 28 ms 4.9.5 recessive ime o release o,rec 10 μs 1) 4.9.6 ransmier Duy cycle D1 (for wors case a 20 kbi/s) D1 0.396 Duy cycle 1 5) TH Rec (max) = 0.744 ; TH Dom (max) =0.581 ; = 7.0 18 V; bi = 50 μs; D1 = bus_rec(min) / 2 bi ; LIN Spec 2.2A (Par. 27) 4.9.7 Duy cycle D1 for supply 5.5 V o 7.0 V (for wors case a 20 kbi/s) Duy cycle D2 (for wors case a 20 kbi/s) Duy cycle D2 for supply 6.1 V o 7.6 V (for wors case a 20 kbi/s) 4.8.9 4.9.1 D1 0.396 Duy cycle 1 5) TH Rec (max) = 0.760 ; TH Dom (max) = 0.593 ; 5.5 V < <7.0V; bi = 50 μs; D1 = bus_rec(min) / 2 bi 4.9.8 D2 0.581 Duy cycle 2 5) 4.9.9 TH Rec (min)= 0.422 ; TH Dom (min)= 0.284 ; = 7.6 18 V; bi = 50 μs; D2 = bus_rec(max) / 2 bi ; LIN Spec 2.2A (Par. 28) D2 0.581 Duy cycle 2 5) 4.9.10 TH Rec (min)= 0.410 ; TH Dom (min)= 0.275 ; 6.1 V < <7.6V; bi = 50 μs; D2 = bus_rec(max) / 2 bi Daa Shee 21 Rev. 1.1, 2015-08-20
Elecrical Characerisics Table 6 Elecrical Characerisics (con d) 5.5 V < <18V; R L = 500 Ω; -40 C < T j <150 C; all volages wih respec o ground; posiive curren flowing ino pin; unless oherwise specified. Parameer Symbol Values Uni Noe / Tes Condiion Num ber Min. Typ. Max. Duy cycle D3 (for wors case a 10.4 kbi/s) Duy cycle D3 for supply 5.5 V o 7.0 V (for wors case a 10.4 kbi/s) Duy cycle D4 (for wors case a 10.4 kbi/s) Duy cycle D4 for supply 6.1 V o 7.6 V (for wors case a 10.4 kbi/s) 1) No subjec o producion es, specified by design 2) V _CNT =(V h_dom + V h rec )/2 3) V HYS = V h_rec - V h_dom 4) Delay ime specified for a load of 10 kω / 20 pf on he oupu 5) Bus load concerning LIN Spec 2.2A: Load 1 = 1 nf / 1 kω = C / R L Load 2 = 6.8 nf / 660 Ω = C / R L Load 3 = 10 nf / 500 Ω = C / R L D3 0.417 Duy cycle 3 5) TH Rec (max) = 0.778 ; TH Dom (max) =0.616 ; = 7.0 18 V; bi = 96 μs; D3 = bus_rec(min) / 2 bi ; LIN Spec 2.2A (Par. 29) 4.9.11 D3 0.417 Duy cycle 3 5) 4.9.12 TH Rec (max) = 0.797 ; TH Dom (max) = 0.630 ; 5.5 V < <7.0V; bi = 96 μs; D3 = bus_rec(min) / 2 bi ; D4 0.590 Duy cycle 4 5) 4.9.13 TH Rec (min) = 0.389 ; TH Dom (min) = 0.251 ; = 7.6 18 V; bi = 96 μs; D4 = bus_rec(max) / 2 bi ; LIN Spec 2.2A (Par. 30) D4 0.590 Duy cycle 4 5) 4.9.14 TH Rec (min) = 0.378 ; TH Dom (min)= 0.242 ; 6.1 V < <7.6V; bi = 96 μs; D4 = bus_rec(max) / 2 bi ; Daa Shee 22 Rev. 1.1, 2015-08-20
Elecrical Characerisics 6.2 Diagrams 100 nf R VIO = 5 V R L R C Bus C TLE7257_TEST_CIRCUIT Figure 14 Simplified es circui Bi Bi Bi (inpu o ransmiing node) Bus_dom(max) Bus_rec(min) UP (Transceiver supply of ransmiing node) TH Rec(max) TH Dom(max) TH Rec(min) TH Dom(min) Thresholds of receiving node 1 Thresholds of receiving node 2 Bus_dom(min) Bus_rec(max) (oupu of receiving node 1) rx_pdf(1) rx_pdr(1) (oupu of receiving node 2) rx_pdr(2) rx_pdf(2) Duy Cycle D1, D3 = _rec(min) / (2 x BIT ) Duy Cycle D2, D4 = _rec(max) / (2 x BIT ) TLE7257_LIN_TIMING_DIAGRAM Figure 15 Timing diagram for dynamic characerisics Daa Shee 23 Rev. 1.1, 2015-08-20
Applicaion Informaion 7 Applicaion Informaion Noe: The following informaion is given as a hin for he implemenaion of he device only and shall no be regarded as a descripion or warrany of a cerain funcionaliy, condiion or qualiy of he device. 7.1 Applicaion Example V Ba 5 V or 3.3V 22μF 100nF V I TLE42xx V Q 10μF 100nF V CC LIN Maser Node 100nF 7 8 TLE7257 10kΩ 1 2.4kΩ Pull-up o MCU Supply Micro Conroller e.g XC22xx 1kΩ 4 1nF 6 2 5 ECU_1 5 V or 3.3V 22μF 100nF V I TLE42xx V Q 10μF 100nF V CC Slave Node 100nF 7 8 TLE7257 1 2.4kΩ Pull-up o MCU Supply Micro Conroller e.g XC22xx 4 220pF 6 2 5 ECU_X TLE7257_APPLICATION Figure 16 Simplified applicaion circui Daa Shee 24 Rev. 1.1, 2015-08-20
Applicaion Informaion 7.2 ESD Suscepibiliy according o IEC61000-4-2 Tes for ESD robusness according o IEC61000-4-2 Gun es (150 pf, 330 Ω) have been performed. The resuls and es condiions are available in a separae es repor. Table 7 ESD Suscepibiliy according o IEC61000-4-2 Performed Tes Resul Uni Remarks Elecrosaic discharge volage a pin, versus +10 kv 1) Posiive pulse Elecrosaic discharge volage a pin, versus -10 kv 1) Negaive pulse 1) ESD suscepibiliy ESD GUN according IEC 61000-4-2, esed by exernal es house. 7.3 Transien Robusness according o ISO 7637-2 Tes for ransien robusness according o ISO 7637-2 have been performed. The resuls and es condiions are available in a separae es repor. Table 8 Auomoive Transien Robusness according o ISO 7637-2 Performed Tes Resul Uni Remarks Pulse 1-100 V Pulse 2 +75 V Pulse 3a -150 V Pulse 3b +100 V 1) Auomoive Transien Robusness according o ISO 7637-2, esed by exernal es house. 1) 1) 1) 1) 7.4 LIN Physical Layer Compaibiliy The TLE7257 fulfills he Physical Layer Specificaion of LIN 1.2, 1.3, 2.0, 2.1, 2.2 and 2.2A. The differences beween LIN specificaion 1.2 and 1.3 is mainly he physical layer specificaion. The reason was o improve he compaibiliy beween he nodes. The LIN specificaion 2.0 is a super se of he 1.3 version. The 2.0 version offers new feaures. However, i is possible o use he LIN 1.3 slave node in a 2.0 node cluser, as long as he new feaures are no used. Vice versa i is possible o use a LIN 2.0 node in he 1.3 cluser wihou using he new feaures. In erms of he physical layer he LIN 2.1, LIN 2.2 and LIN 2.2A Specificaion does no include any changes and is fully complian o he LIN Specificaion 2.0. LIN 2.2A is he laes version of he LIN specificaion, released in December 2010. The physical layer specificaion of LIN 2.2A will be included in he ISO 17987-4 wihou modificaions. Addiionally, he TLE7257 is complian o he SAE J2602-2 sandard for usage in he US auomoive marke. 7.5 Fail-Safe Inpu The inpu has an inernal pull-up srucure o avoid any bus disurbance in case he inpu is open and floaing. In case of an no conneced inpu, he pin is pulled o an inernal volage supply (see Figure 1) and he oupu o he LIN bus on he pin is always recessive. Therefore he TLE7257 can no disurb he communicaion on he LIN bus. In order o opimize he quiescen curren of he TLE7257 in Sleep mode, he pull-up srucure inside he inpu is disabled in Sleep mode. The logic inside he inpu is no reacing a any signal change provide o he inpu pin and he ransmier is urned off. In Sleep mode he TLE7257 can no disurb or block he LIN bus in any case. Daa Shee 25 Rev. 1.1, 2015-08-20
Applicaion Informaion Table 9 Terminaion Operaion Mode Normal Operaion mode Sandby mode Sleep mode Remarks The inernal pull-up srucure is acive, in case he inpu is open he inpu signal is high and he oupu on he pin is recessive The inernal pull-up srucure is acive, in case he inpu is open he inpu signal is high. In Sandby mode he ransmier is urned off and herefore he oupu on he pin always is recessive The inernal pull-up srucure is inacive, in case he inpu is open he inpu signal is floaing. In Sleep mode he ransmier is urned off and herefore he oupu on he pin always is recessive 7.6 Pull-up Resisor The receive daa oupu () provides an open drain behavior for allowing he oupu level o be adaped o he microconroller supply volage. Thus 3.3 V microconroller derivaives wihou 5 V oleran pors can be used. In case he microconroller por pin does no provide an inegraed pull-up, an exernal pull-up resisor conneced o he microconroller s V CC supply volage is required. The ypical pin curren / volage characerisic over emperaure is given in Figure 17. Wih he applicaions microconroller por pins (Rx) minimum high -level and maximum low -level inpu volage he pull-up resisor can be dimensioned. For mos applicaions a pull-up resisor R Rx of 2.4 kω is recommended. 1.4 1.2 T j = 40 C T j = 27 C T j = 150 C 1 V [V] 0.8 0.6 0.4 0.2 0 0 1 2 3 4 5 6 7 8 I [ma] Figure 17 Typical oupu sink characerisics Daa Shee 26 Rev. 1.1, 2015-08-20
Applicaion Informaion 7.7 Compaibiliy wih oher Infineon LIN Transceivers Infineon offers a complee LIN ransceiver family consising of devices in PG-DSO-8 package (TLE7257SJ, TLE7258SJ and TLE7259-3GE) and PG-TSON-8 package (TLE7257LE, TLE7258D, TLE7258LE and TLE7259-3LE). All hese devices are pin-o-pin compaible, wih he only differences a he pins named N.C. ( = No Conneced). The N.C. pins can be lef open on he PCB in applicaions where hese funcionaliies are no needed. The N.C. pins are inernally no bonded, so he devices will no be affeced if hese pins are conneced o signals on he applicaion PCB. 1 8 2 7 WK 3 6 4 5 TLE7259-3GE 1 8 1 8 2 7 2 7 N.C. 3 6 N.C. 3 6 4 5 4 5 TLE7257SJ TLE7258SJ Figure 18 Pin compaibiliy beween TLE7257SJ, TLE7258SJ and TLE7259-3GE Table 10 Funcionaliy of LIN ransceiver family, PG-DSO-8 package Device TLE7257SJ TLE7258SJ TLE7259-3GE Applicaions Sandard LIN Maser node Sandard LIN Slave node High End LIN All kind of nodes Feaures Fas Programming mode Local Wake inpu Inhibi oupu usage VREG conrol VREG conrol VREG conrol Maser Terminaion Time-ou Power-Up mode Sleep mode Sandby mode Sandby mode The funcional difference beween he devices in he Infineon LIN ransceiver family is summarized in Table 10 and in Table 11. For mode deails on he funcional and parameric differences, please refer o he respecive par s daashee. Daa Shee 27 Rev. 1.1, 2015-08-20
Applicaion Informaion 1 8 2 7 WK 3 6 4 5 TLE7259-3LE 1 8 1 8 N.C. 1 8 2 7 2 7 2 7 N.C. 3 6 N.C. 3 6 N.C. 3 6 4 5 4 5 4 5 TLE7257LE TLE7258D TLE7258LE (Top side X-Ray view) Figure 19 Pin compaibiliy beween TLE7257LE, TLE7258LE, TLE7258D and TLE7259-3LE Table 11 Funcionaliy of LIN ransceiver family, PG-TSON-8 package Device TLE7257LE TLE7258LE TLE7258D TLE7259-3LE Applicaions Sandard LIN Maser node Sandard LIN Slave node K-Line MOST ECL High End LIN All kind of nodes Feaures Fas Programming mode Local Wake inpu Inhibi oupu usage VREG conrol VREG conrol VREG conrol Maser Terminaion Time-ou Power-Up mode Sleep mode Sandby mode Sandby mode Sandby mode Daa Shee 28 Rev. 1.1, 2015-08-20
Package Oulines 8 Package Oulines 0.41 1.27 +0.1 2) -0.06 0.175±0.07 (1.45) 1.75 MAX. 0.1 0.2 M A B 8x B 0.35 x 45 1) 4-0.2 C 6 ±0.2 +0.06 0.19 0.64 ±0.25 8 MAX. 0.2 M C 8x 8 5 1 4 1) 5-0.2 A Index Marking 1) Does no include plasic or meal prorusion of 0.15 max. per side 2) Lead widh can be 0.61 max. in dambar area GPS01181 Figure 20 PG-DSO-8 (Plasic Dual Small Ouline PG-DSO-8-44) 3 ±0.1 0.2 ±0.1 3 ±0.1 Pin 1 Marking 1±0.1 0 +0.05 0.05 0.25±0.1 0.1 ±0.1 0.3 ±0.1 ±0.1 0.07 MIN. ±0.1 0.81 0.56±0.1 2.4±0.1 0.38 1.63±0.1 0.4 ±0.1 1.58±0.1 0.65±0.1 0.3 ±0.1 Pin 1 Marking PG-TSON-8-1-PO V01 Figure 21 PG-TSON-8 (Plasic Thin Small Ouline Nonleaded PG-TSON-8-1) Green Produc (RoHS complian) To mee he world-wide cusomer requiremens for environmenally friendly producs and o be complian wih governmen regulaions he device is available as a green produc. Green producs are RoHS-Complian (i.e. Pbfree finish on leads and suiable for Pb-free soldering according o IPC/JEDEC J-STD-020). For furher informaion on alernaive packages, please visi our websie: hp://www.infineon.com/packages. Dimensions in mm Daa Shee 29 Rev. 1.1, 2015-08-20
Revision Hisory 9 Revision Hisory Table 12 Revision Hisory Revision Daa Changes 1.1 2015-08-20 Daa Shee updaed based on Daa Shee Rev. 1.0. Marking of SJ ype updaed: Chaper 1, Overview 1.0 2013-10-16 Daa Shee creaed. Daa Shee 30 Rev. 1.1, 2015-08-20
Ediion 2015-08-20 Published by Infineon Technologies AG 81726 Munich, Germany 2015 Infineon Technologies AG All Righs Reserved. Legal Disclaimer The informaion given in his documen shall in no even be regarded as a guaranee of condiions or characerisics. Wih respec o any examples or hins given herein, any ypical values saed herein and/or any informaion regarding he applicaion of he device, Infineon Technologies hereby disclaims any and all warranies and liabiliies of any kind, including wihou limiaion, warranies of non-infringemen of inellecual propery righs of any hird pary. Informaion For furher informaion on echnology, delivery erms and condiions and prices, please conac he neares Infineon Technologies Office (www.infineon.com). Warnings Due o echnical requiremens, componens may conain dangerous subsances. For informaion on he ypes in quesion, please conac he neares Infineon Technologies Office. Infineon Technologies componens may be used in life-suppor devices or sysems only wih he express wrien approval of Infineon Technologies, if a failure of such componens can reasonably be expeced o cause he failure of ha life-suppor device or sysem or o affec he safey or effeciveness of ha device or sysem. Life suppor devices or sysems are inended o be implaned in he human body or o suppor and/or mainain and susain and/or proec human life. If hey fail, i is reasonable o assume ha he healh of he user or oher persons may be endangered.