Fast Buffer / C FEATURES Slew rate............................... V/µs Wide range single or dual supply operation Bandwidth.............................. MHz High output drive............... ±V with Ω load Low phase non-linearity................ degrees Rise times.................................. 3ns High input resistance:....................... Ω High output current (peak)................. ma APPLICATIONS Coaxial Cable Driver Fast Op Amp Booster Flash Converter Driver Video Line Driver High Speed Sample and Hold ATE Pin Driver Video Amplifier Radar Sonar Boost OP Amp Output Isolate Capacitance Load GENERAL DESCRIPTION The is a high speed, FET input, voltage follower/buffer designed to provide high current drive (up to ma) at frequencies from DC to over MHz. The slews at V/µs and exhibits excellent phase linearity up to MHz. is intended to fulfill a wide range of buffer applications such as high speed line drivers, video impedance transformation, nuclear instrumentation amplifiers, op amp isolation buffers for driving reactive loads and high impedance input buffers for high speed A to Ds and comparators. In addition, the can continuously drive Ω coaxial cables or be used as a yoke driver for high resolution CRT displays. This device is constructed using specially selected junction FETs and active laser trimming to achieve guaranteed performance specifications. The is specified for operation from - o C to + o C and the C is specified from - o C to 8 o C. The is available in a.w metal TO-8 package. ORDERING INFORMATION Part Package Temperature Range G HA (TO8 Lead) - o C to o C CG HA (TO8 Lead) - o C to 8 o C CONNECTION DIAGRAM Metal Can Package NC NC C NC 4 3 PRESET 8 ADJUST NC V C Top View Case is electrically Isolated Package HA CALOGIC, 3 Whitney Place, Fremont, California 43, Telephone: --, FAX: --
/ C ABSOLUTE MAXIMUM RATINGS If Military/Aerospace specified devices are required, please contact Calogic Sales Office for availability and specifications. Supply Voltage ( - )........................... 4V Power Dissipation (See Curves) /C.............................W Junction Temperature.......................... o C Input Voltage............................... ±V Supply Continuous Output Current /C......................... ±ma Peak Output Current /C......................... ±ma Lead Temp. (Soldering, seconds)............... 3 o C Operating Temperature Range............................ - o C to + o C C........................... - o C to +8 o C Storage Temperature Range.......... - o C to + o C DC ELECTRICAL CHARACTERISTICS: The following specifications apply for supply voltage = ±V unless otherwise noted (Note ) SYMBOL CHARACTERISTICS C MIN TYP MAX MIN TYP MAX UNITS CONDITIONS VOS Output Offset Voltage. mv mv RS = Ω, TJ = o C, VIN = V (Note ), RS = Ω V OS T Average Temperature Coefficient of Offset Voltage µv/ o C RS = Ω, VIN = V (Note 3) IB Input Bias Current.. pa na na VIN = V TJ = o C (Note ) TA = o C (Note 4) TJ = TA = TMAX AV Voltage Gain..8...8. V/V VO = ±V, RS = Ω, RL =.kω RIN Input Impedance Ω RL = kω ROUT Output Impedance.. Ω VIN = ±.V, RL =.k V(SWING ) Output Voltage Swing ± ± V VI = ±4V, RL =.k V(SWING ) ±. ±. VI = ±.V, RL = Ω, TA = o C IS Supply Current 8 8 4 ma VIN = V (Note ) PD Power Consumption 4 4 mw VIN = V AC ELECTRICAL CHARACTERISTICS: T J = o C, V S = ± V, R S = Ω, R L =.KΩ (Note 3) SYMBOL CHARACTERISTICS C MIN TYP MAX MIN TYP MAX UNITS SR Slew Rate 4 V/µs VIN = ±V BW Bandwidth MHz VIN =.Vrms CONDITIONS Phase Non- Linearity.. degrees BW =.Hz to MHz RT Rise Time. 3. ns VIN =.V Propagation Delay.. ns VIN =.V Harmonic Distortion <. <. % f>khz Note : is % production tested as specified at o C. Specifications at temperature extremes are verified by sample testing, correlation or periodic characterization. Note : Specification is at o C junction temperature due to requirements of high speed automatic testing. Actual values at operating temperature will exceed the value at TJ = o C. When supply voltages are ±V, no-load operating junction temperature may rise 4- o C above ambient, and more under load conditions. Accordingly, VOS may change one to several mv, and IB will change significantly during warm-up. Note 3: Limits are guaranteed by sample testing, periodic characterization or correlation. Note 4: Measured in still air minutes after application of power. Guaranteed through correlated automatic pulse testing. Note : Guaranteed through correlated automatic pulse testing at TJ = o C. CALOGIC, 3 Whitney Place, Fremont, California 43, Telephone: --, FAX: --
/ C TYPICAL PERFORMANCE CHARACTERISTICS POWER DISSIPATION SUPPLY CURRENT vs SUPPLY VOLTAGE POWER DISSIPATION (W).... AMBIENT θ JA = C/W CASE θ JC = C/W SUPPLY CURRENT (±ma) 8 T C = + C T C = + C T C = - C TEMPERATURE ( C) SUPPLY VOLTAGE (±V) VOLTAGE (±V) 8 8 4 VOLTAGE vs SUPPLY VOLTAGE R L = kω 4 R S = kω T C = + C / VOLTAGE (-V) - -4 - -8 - - NEGATIVE PULSE RESPONSE V S = ±V R S = Ω R L = kω T C = + C 3 4 SUPPLY VOLTAGE (±V) TIME (ns) / VOLTAGE (V) 8 4 POSITIVE PULSE RESPONSE V S = ±V R L = kω, R S = Ω T C = + C VOLTAGE GAIN (V/V)..8..4. FREQUENCY RESPONSE V S = ±V R S = Ω R L = kω V IN =. Vrms Av φ 4 3 3 PHASE LAG (DEGREES) 3 4..... TIME (ns) FREQUENCY (MHz) CALOGIC, 3 Whitney Place, Fremont, California 43, Telephone: --, FAX: --
/ C TYPICAL PERFORMANCE CHARACTERISTICS (Continued) RISE AND FALL TIME (ns) 8.. 4.. V S = ±V R S = Ω R L = k RISE AND FALL TIME vs TEMPERATURE t f t r BIAS CURRENT (na).. BIAS CURRENT vs TEMPERATURE V S = ±V V S = ±V V S = ±V -. TEMPERATURE ( C) TEMPERATURE ( C) CURRENT NORMALIZED TO CURRENT AT TIME = NORMALIZED BIAS CURRENT DURING WARM-UP V S = ±V T A = C BIAS CURRENT (na).. BIAS CURRENT vs VOLTAGE V S = ±V PULSE TESTED (T J = C) 4 8 8 4 - - - TIME FROM POWER TURN-ON (MINUTES) VOLTAGE (V) CALOGIC, 3 Whitney Place, Fremont, California 43, Telephone: --, FAX: --
/ C APPLICATION INFORMATION: Recommended Layout Precautions RF/video printed circuit board layout rules should be followed when using the since it will provide power gain to frequencies over MHz. Ground planes are recommended and power supplies should be decoupled at each device with low inductance capacitors. In addition, ground plane shielding may be extended to the metal case of the device since it is electrically isolated from internal circuitry. Alternatively the case should be connected to the output to minimize input capacitance. Offset Voltage Adjustment The s offset voltages have been actively trimmed by laser to meet guaranteed specifications when the offset preset pin is shorted to the offset adjust pin. If offset null is desirable, it is simply obtained by leaving the offset preset pin open and connecting a trim pot of Ω for the between the offset adjust pin and V, as illustrated in Figure. Operation From Single Or Asymmetrical Power Supplies may be used in applications where symmetrical supplies are unavailable or not desirable. A typical application might be an interface to a MOS shift register where = +V and V = -V. In this case, an apparent output offset occurs due to the device s voltage gain of less than unity. This additional output error may be predicted by: V O ( A V) (V+ V ) =. ( V ) where: A V = No load voltage gain, typically. = Positive supply voltage V = Negative supply voltage For the above example, V O would be -3mV. This may be adjusted to zero as described in Figure. For AC coupled applications, no additional offset occurs if the DC input is properly biased as illustrated in the Typical Applications section. Short Circuit Protection In order to optimize transient response and output swing, output current limit has been omitted from the. Short circuit protection may be added by inserting appropriate value resistors between and C pins and V and V C pins as illustrated in Figure. Resistor values may be predicted by: R LIM V+ = V I SC I SC where: I SC ma for The inclusion of limiting resistors in the collectors of the output transistors reduces output voltage swing. Decoupling VC + and V C pins with capacitors to ground will retain full output swing for transient pulses. Alternate active current limit techniques that retain full DC output swing are shown in FIGURE. Offset Zero Adjust FIGURE. Resistor Current Limiting Using Resistor PRESET (OPEN) ADJUST Ω +V -V R LIM R LIM C.µF C.µF CALOGIC, 3 Whitney Place, Fremont, California 43, Telephone: --, FAX: --
/ C Figure 3. In Figure 3, the current sources are saturated during normal operation, thus apply full supply voltage to the V C pins. Under fault conditions, the voltage decreases as required by the overload. For Figure : R LIM = VBE =.V I SC ma = Ω Capacitive Loading The is designed to drive capacitive loads such as coaxial cables in excess of several thousand picofarads without susceptibility to oscillation. However, peak current resulting from (C d V/d t) should be limited below absolute maximum peak current ratings for the devices. Thus for the : ( VIN ) C t L I OUT ±ma In addition, power dissipation resulting from driving capacitive loads plus standby power should be kept below total package power rating: P Dpkg. P DC + P AC P Dpkg. ( V ) I S + P AC P AC (Vp-p) f C L where: Vp-p = Peak-to-peak output voltage swing f = Frequency C L = Load Capacitance Operation Within An Op Amp Loop may be used as a current booster or isolator buffer within a closed loop with op amps such as LH3, or CLM44. An isolation resistor of 4Ω should be used between the op amp output and the input of. The wide bandwidth and high slew rate of the assure that the loop has the characteristics of the op amp and that additional rolloff is not required. Hardware In order to utilize the full drive capabilities of, it should be mounted with a heat sink particulary for extended temperature operation. The case is isolated from the circuit and may be connected to the system chassis. Design Precaution Power supply bypassing is necessary to prevent oscillation. Low inductance ceramic disc capacitors with the shortest practical lead lengths must be connected from each supply lead (within < 4" to " of the device package) to a ground plane. Capacitors should be one or two.µf in parallel; adding a 4.µF solid tantalum capacitor will help troublsome instances. FIGURE 3. Current Limiting Using Current Sources +V R LIM Q Q 3k.µF Q3 Q = Q = N Q3 = Q4 = N Q4 R LIM -V CALOGIC, 3 Whitney Place, Fremont, California 43, Telephone: --, FAX: --
/ C TYPICAL APPLICATIONS High Input Impedance AC Coupled Amplifier 4.pF CASE.µF.µF.µF M f H MHz Coaxial Cable Driver C* 43 Ω *Select C for Optimum Pulse Response CALOGIC, 3 Whitney Place, Fremont, California 43, Telephone: --, FAX: --
/ C TYPICAL APPLICATIONS (Continued) High Input Impedance Comparator with Offset Adjust Instrumentation Shield/Line Driver V U.L. 3-4 + ADJUST V L.L. - + LM NO GO = LOGIC "" GO = LOGIC "" CASE Single Supply AC Amplifier 4.MHz Notch Filter V CC =.V C pf C pf.µf M CASE V IN R Ω R Ω C 3pF R Ω f = πr C R = R C = C CALOGIC, 3 Whitney Place, Fremont, California 43, Telephone: --, FAX: --
/ C TYPICAL APPLICATIONS (Continued) High Speed Sample and Hold ANALOG C* pf *Polycarbonate or Teflon TM LOGIC CALOGIC, 3 Whitney Place, Fremont, California 43, Telephone: --, FAX: --