3D D detectors at ITC-irst irst: process development, characterization and first irradiation studies S. Ronchin a, M. Boscardin a, L. Bosisio b, V. Cindro c, G.-F. Dalla Betta d, C. Piemonte a, A. Pozza a, A. Zoboli d, N. Zorzi a a ITC-IRST Microsystems Division, Povo, Trento, Italy b INFN and Physics Department, University of Trieste, Trieste, Italy c Jozef Stefan Institute, Ljubljana, Slovenia d INFN and ICT Department, University of Trento, Trento, Italy
Outline 3D Detectors: concept and functioning Fabrication process Electrical characterization First irradiation studies Preliminary CCE measurements Next technological step Conclusion
Standard 3D detectors - concept [Parker et al. NIMA395 (1997)] n-columns p-columns wafer surface ionizing particle carriers collected at the same time n-type substrate Distance between n and p electrodes can be made very short extremely radiation hard detector (low full depl. volt. and high CCE even at very high fluences) Drawbacks: - feasibility of large scale production still to be verified - electrodes are dead regions (or partially)
Single-Type Type-Column 3D detectors - concept [C. Piemonte et al NIMA 541 (2205)] n + electrodes on the way to a fully 3D device: 3D-STC ionizing particle n + n + electrons are swept away by the transversal field p-type substrate holes drift in the central region and diffuse towards p+ contact Uniform p+ layer Fabrication process is much simpler: column etching and doping performed only once holes not etched all through the wafer
Fabrication process information Two first productions: Substrate: Si, p-type, <100>: FZ (525 µm) resistivity > 5.0 kω cm Cz (300µm) resistivity > 1.8 kω cm Surface isolation: p-spray p-stop Holes performed at CNM (Barcelona, Spain): depth: 120-150 µm Third production: Substrate: Si, Resistivity ~1.6 kωcm, p-type, <111>, 380 µm Surface isolation: combined p-stop and p-spray Holes performed by IBS (Peynier, France): depth: 180 µm
Layout example - strip detectors guard ring bias line metal p-stop hole AC and DC coupling Inter-columns pitch 80-100 µm Two different p-stop layouts Holes Ø 6 or 10 µm Contact opening n +
Leakage current Measurement on long strips (area about 1cm 2 ) Two first runs Ileak [A] 1.0E-05 1.0E-06 1.0E-07 1.0E-08 1.0E-09 1.0E-10 p-spray p-stop Bias line Guard ring 0 50 100 150 200 V bias [V] Ileak [A] 1.E-05 1.E-06 1.E-07 1.E-08 Increase of current caused by surface effects. No guard rings were implemented. Bias line Guard ring Third run Average leakage current < 1pA/column for both processes 1.E-09 1.E-10 0 25 50 75 V bias [V]
Strip detectors Current distribution @ 40V 30 Detectors count 25 20 15 10 5 0 0 5 10 15 20 25 30 35 40 45 50 >50 I bias line [na] Leakage current < 1pA/column in most of the detectors: same process with two different holes producers Good process yield for both processes Detectors count Two first runs 70 detectors 50 45 40 35 30 25 20 15 10 5 0 0 12000-15000 columns for each detector Third run 90 detectors 5 10 15 20 25 30 35 40 45 50 >50 I bias line [na]
5.0 4.0 3.0 2.0 1.0 0.0 Full depletion evaluation in 3D-stc 3D diode matrix of 10x10 holes guard ring C^-2 (pf-2) Phase 1 pitch=80um pitch=80um simulation Phase 2 Back C backtot f=10khz 1/C back 2 characteristic C inttot 0 10 20 30 40 50 60 Bias Voltage (V) Phase 1 Region between columns not fully depleted high C back ~ zero C int Phase 2 Full depletion between columns Depletion proceeds toward the back max C int slowly dec. C back undepleted Si undepleted Si full depletion between columns: Two first runs: ~5V for 80µm column pitch, 7 V for 100 µm pitch Third run: ~15V for 80µm column pitch, 28 V for 100 µm pitch
Radiation damage studies (1) [performed in collaboration with V. Cindro, Ljubljana] Devices: 3D diodes, p-type FZ 525µm thick substrate, p-stop isolation Irradiation: neutrons at TRIGA research reactor in Ljubljana; 6 fluences: F1: 5e13n/cm 2 F2: 1e14n/cm 2 F3: 2e14n/cm 2 F4: 5e14n/cm 2 F5: 1e15n/cm 2 F6: 5e15n/cm 2 Annealing: 15 days at room temperature (~ minimum depletion voltage). Measurements: IV and CV (series model @10kHz) @ 23C Aim: study of the depletion characteristic (at the moment)
1.E-04 1.E-05 1.E-06 Radiation damage studies (2) n-irrad 3D diodes (D2) 1) 3D Diode current (80µm pitch) Idiode (A) 1.E-07 1.E-08 1.E-09 F1 F6 before irradiation Normal current behavior: current increases with fluence 1.E-10 Conc [cm-3] 1.E-11 0 50 100 150 200 250 300 Vrev (V) 1.0E+16 n-irradiated 3D diodes 1.0E+15 1.0E+14 1.0E+13 F1 F2 F4 F3 F5 F6 1.0E+12 0 50 100 150 200 Voltage [V] 2) CV measurements difficult measurement as it depends on frequency and model (series/parallel) we look only for kinks in the CV related to full lateral depletion Conc 80µm pitch dv d 100µm pitch 2 C back 1
Radiation damage studies (3) Depletion Voltage (V) 10000 1000 100 10 1 col. pitch = 80um col. pitch = 100um expected from planar diode300µm 1.0E+13 1.0E+14 1.0E+15 1.0E+16 Fluence (n/cm^2) lateral depletion Neff=β*Φ (*) β=0.021cm -1 see Cindro s talk at 8 th RD50 workshop: http://rd50.web.cern.ch/rd50/ Simulating the full lateral depletion voltage with N sub estimated from equation (*) we obtain values comparable with those reported on the plot. 40/50µm40/50µm Each column depletes half col. pitch the lateral depletion voltage is very low. undepleted Si
3D diode CCE measurements Carlo Tosi, Mara Bruzzi, Antonio De Sio INFN and University of Florence 90Sr β- particlesource amplifier/shaper circuit Amptek, Shaping time=2.4µs, ENC<1500e - rms plastic scintillator coupled to a photomultiplier tube triggering the sampling and ADC circuits. Collected Charge [# electrons] 40000 35000 30000 25000 20000 15000 10000 5000 0 (preliminary) collected charge as a function of the bias voltage counts signal 0 20 40 60 80 100 120 140 160 Reverse Bias [V] 525-µm thick FZ silicon wafer 100 µm pitch large signal at 5V is observed 1) about 27% CCE already at 0V: high collection probability even below full depletion due to the short collection path (~half pitch). CCE ~column depth/substrate thickness. 2) as the voltage is increased, the collected charge increases: 100% CCE at a Full Depletion Voltage ~ 190V
Next technological step Double-sided Double-Type-Column 3D detectors 50µm 50µm 300µm Good performance of standard 3D + simplified process of 3D-STC Layout designed, with pixel and strip detectors n + bulk contact p-type columns
Conclusion IRST is developing the technology for the production of 3D detectors with encouraging results. First device produced, 3D-STC detector, simple fabrication process: low leakage current, high process yield, reproducibility, hole producer independent extremely important step to learn aspects of the technology and to understand 3D functioning. First irradiations and characterization of 3D-STC: confirm low depletion voltage after irradiation of 3D detectors First CCE measurements: high efficiency even below full depletion FUTURE WORK CCE and signal shape measurements after irradiation; Early next year first prototypes of 3D-DTC will be available.
Next technological steps 50µm 50µm 300µm Double-sided Double-Type-Column front side identical to 3D-STC Layout designed, with pixel and strip detectors Bulk contact p-type columns PIN diode Planar detectors with active edge n+ doping
Strip detectors CV measurements Capacitance measurement between one strip and the two first neighboring p-stop; DC coupling; strip pitch=80µm Det3 196 columns per strip 93µm 80µm Det1 230 columns per strip Cint [pf] 8 7 6 5 4 3 2 1 0 f=100khz Det4 Det8 Det1 Det3 Typical inter-column capacitance range 12 19 ff/column 0 10 20 30 40 Vback [V] Det8 184 columns per strip 100µm 80µm Det4 230 columns per strip Other capacitance measurement results Typical single-strip backplane capacitance (after lateral full depletion) <5pF (~200 columns) Typical coupling capacitance for AC detectors ~ 60pF