FET-Input, Low Power INSTRUMENTATION AMPLIFIER FEATURES LOW BIAS CURRENT: ±4pA LOW QUIESCENT CURRENT: ±4µA LOW INPUT OFFSET VOLTAGE: ±µv LOW INPUT OFFSET DRIFT: ±µv/ C LOW INPUT NOISE: nv/ Hz at f = khz (G =) HIGH CMR: 6dB WIDE SUPPLY RANGE: ±.V to ±8V LOW NONLINEARITY ERROR:.% max INPUT PROTECTION TO ±4V 8-PIN DIP AND SO-8 SURFACE MOUNT APPLICATIONS LOW-LEVEL TRANSDUCER AMPLIFIERS Bridge, RTD, Thermocouple PHYSIOLOGICAL AMPLIFIERS ECG, EEG, EMG, Respiratory HIGH IMPEDANCE TRANSDUCERS CAPACITIVE SENSORS MULTI-CHANNEL DATA ACQUISITION PORTABLE, BATTERY OPERATED SYSTEMS GENERAL PURPOSE INSTRUMENTATION DESCRIPTION The is a FET-input, low power instrumentation amplifier offering excellent accuracy. Its versatile three-op amp design and very small size make it ideal for a variety of general purpose applications. Low bias current (±4pA) allows use with high impedance sources. Gain can be set from V to,v/v with a single external resistor. Internal input protection can withstand up to ±4V without damage. The is laser-trimmed for very low offset voltage (±µv), low offset drift (±µv/ C), and high common-mode rejection (6dB at G = ). It operates on power supplies as low as ±.V (4.V), allowing use in battery operated and single V systems. Quiescent current is only 4µA. Package options include 8-pin plastic DIP and SO-8 surface mount. All are specified for the 4 C to 8 C industrial temperature range. 7 V Over-Voltage Protection A kω G = kω A 3 6 8 kω 3 Over-Voltage Protection A 4 V International Airport Industrial Park Mailing Address: PO Box 4, Tucson, AZ 8734 Street Address: 673 S. Tucson Blvd., Tucson, AZ 876 Tel: () 746- Twx: 9-9- Internet: http://www.burr-brown.com/ FAXLine: (8) 48-633 (US/Canada Only) Cable: BBRCORP Telex: 66-649 FAX: () 889- Immediate Product Info: (8) 48-63 997 Burr-Brown Corporation PDS-4A Printed in U.S.A. May, 998 SBOS78
SPECIFICATIONS: V S = ±V At T A = C, V S = ±V, R L = kω, and IA reference = V, unless otherwise noted. P, U PA, UA PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS INPUT Offset Voltage, RTI ±±/G ±±/G ±3±/G ±±/G µv vs Temperature ±±/G ±±/G ±±/G µv/ C vs Power Supply V S = ±.V to ±8V ±±/G ±±/G µv/v Long-Term Stability ±. µv/mo Impedance, Differential Ω pf Common-Mode = V Ω pf Input Voltage Range See Text and Typical Curves Safe Input Voltage ±4 V Common-Mode Rejection V CM =.V to 3.V G = 78 86 7 db G = 9 8 db G = 96 6 9 db G = 6 db BIAS CURRENT V CM = V ±4 ± pa vs Temperature See Typical Curve Offset Current ±. pa vs Temperature See Typical Curve NOISE, RTI R S = Ω Voltage Noise: f = Hz G = 3 nv/ Hz f = Hz G = nv/ Hz f = khz G = nv/ Hz f =.Hz to Hz G = µvp-p Current Noise: f = khz fa/ Hz GAIN Gain Equation (kω/ ) V/V Range of Gain, V/V Gain Error = 4V to 3.V G = ±. ±. ±. % G = ±.3 ±.4 ±. % G = ±. ±. ±.7 % G = ±. % Gain vs Temperature () G = ± ± ppm/ C G > ± ± ppm/ C Nonlinearity = 4V to 3.V G = ±. ±. ±. % of FSR G = ±. ±. ±.8 % of FSR G = ±. ±. ±.8 % of FSR G = ±. % of FSR OUTPUT Voltage: Positive R L = kω (V).9 V Negative R L = kω (V). V Positive R L = kω (V). (V).9 V Negative R L = kω (V) (V). V Capacitance Load Drive pf Short-Circuit Current ±4 ma FREQUENCY RESPONSE Bandwidth, 3dB G = 6 khz G = 3 khz G = khz G = khz Slew Rate = ±V, G.7 V/µs Settling Time,.% G = to µs G = 3 µs G = 6 µs Overload Recovery % Input Overload µs POWER SUPPLY Voltage Range ±. ± ±8 V Quiescent Current I O = V ±4 ± µa TEMPERATURE RANGE Specification 4 8 C Operating C Storage C Thermal Resistance, θ JA 8-Lead DIP C/W SO-8 Surface Mount C/W Specification same as P, U. NOTE: () Temperature coefficient of the Internal Resistor in the gain equation. Does not include TCR of gain-setting resistor,.
PIN CONFIGURATION Top View 8-Pin DIP and SO-8 ELECTROSTATIC DISCHARGE SENSITIVITY Top View V IN V IN 3 V 4 8 7 6 V This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS () Supply Voltage... ±8V Analog Input Voltage Range... ±4V Output Short-Circuit (to ground)... Continuous Operating Temperature... C to C Storage Temperature... C to C Junction Temperature... C Lead Temperature (soldering, s)... 3 C NOTE: () Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. PACKAGE/ORDERING INFORMATION PACKAGE SPECIFIED DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE NUMBER() RANGE MARKING NUMBER() MEDIA Single P 8-Pin DIP 6 4 C to 8 C P P Rails PA 8-Pin DIP 6 4 C to 8 C PA PA Rails U SO-8 Surface-Mount 8 4 C to 8 C U U Rails " " " " " U/K Tape and Reel UA SO-8 Surface-Mount 8 4 C to 8 C UA UA Rails " " " " " UA/K Tape and Reel NOTES: () For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. () Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /K indicates devices per reel). Ordering pieces of U/K will get a single -piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. 3
TYPICAL PERFORMANCE CURVES At T A = C, V S = ±V, unless otherwise noted. Gain (db) 6 4 3 G = V/V G = V/V G = V/V G = V/V GAIN vs FREQUENCY k k k M M Frequency (Hz) Common-Mode Rejection (db) 8 6 4 COMMON-MODE REJECTION vs FREQUENCY k k k M Frequency (Hz) G = V/V G = V/V G = V/V G = V/V Power Supply Rejection (db) 8 6 4 POSITIVE POWER SUPPLY REJECTION vs FREQUENCY G = V/V G = V/V G = V/V G = V/V Power Supply Rejection (db) 8 6 4 G = V/V G = V/V G = V/V NEGATIVE POWER SUPPLY REJECTION vs FREQUENCY G = V/V k k k M Frequency (Hz) k k k M Frequency (Hz) Common-Mode Voltage (V) INPUT COMMON-MODE RANGE vs OUTPUT VOLTAGE, V S = ±V V V D/ V O V D/ V CM V G = G Output Voltage (V) Common-Mode Voltage (V) 4 3 3 4 INPUT COMMON-MODE RANGE vs OUTPUT VOLTAGE, V S = ±V, ±.V G G = V S = ±V V S = ±.V G G = 4 3 3 4 Output Voltage (V) 4
TYPICAL PERFORMANCE CURVES (CONT) At T A = C, V S = ±V, unless otherwise noted. k INPUT BIAS CURRENT vs TEMPERATURE m INPUT BIAS CURRENT vs COMMON-MODE INPUT VOLTAGE k µ Bias Current (pa). I B I OS Input Bias Current (A) µ p p µ. 7 7 Temperature ( C) µ m Common-Mode Voltage (V) Input Current (ma) IN V INPUT OVER-VOLTAGE V/I CHARACTERISTICS.8 G = V/V.6.4...4 Flat region represents normal linear operation. G = V/V V.6.8 G = V/V G = V/V I 4 3 3 4 Input Voltage (V) Settling Time (µs) SETTLING TIME vs GAIN.%.% Gain (V/V) QUIESCENT CURRENT AND SLEW RATE vs TEMPERATURE.4 ± SHORT-CIRCUIT CURRENT vs TEMPERATURE Quiescent Current (µa) 47 4 4 4 I Q SR..8.6 Slew Rate (V/µs) Short-Circuit Current (µa) ±4 ±3 ± ± I SC I SC 37.4 7 7 Temperature ( C) ± 7 7 Temperature ( C)
TYPICAL PERFORMANCE CURVES (CONT) At T A = C, V S = ±V, unless otherwise noted. Output Voltage Swing (V) OUTPUT VOLTAGE SWING vs OUTPUT CURRENT V (V).3 (V).6 8 C C (V).9 4 C, C (V). C (V). (V). (V). (V).9 (V).6 (V).3 (V) C 8 C C 4 C, C ± ±4 ±6 ±8 ± Output Current (ma) Peak-to-Peak Output Voltage (Vp-p) 3 G = MAXIMUM OUTPUT VOLTAGE vs FREQUENCY G = to G = k k k M Frequency (Hz) Offset Voltage Change (µv) 8 6 4 4 6 INPUT OFFSET VOLTAGE WARM-UP Percent of Units (%) 8 6 4 8 6 4 INPUT OFFSET VOLTAGE DRIFT PRODUCTION DISTRIBUTION Typical production distribution of packaged units. 8 3 4 Time (µs)... 3 3. 4 4.. 6 6. 7 7. 8 8. 9 9. Offset Voltage Drift (µv/ C) INPUT-REFERRED NOISE VOLTAGE vs FREQUENCY VOLTAGE NOISE. TO Hz INPUT-REFERRED, G Voltage Noise (nv/ Hz) G = G = G = (BW Limit) G =.µv k k Frequency (Hz) s /div 6
TYPICAL PERFORMANCE CURVES (CONT) At T A = C, V S = ±V, unless otherwise noted. SMALL-SIGNAL STEP RESPONSE (G =, ) SMALL-SIGNAL STEP RESPONSE (G =, ) G = G = mv/div mv/div G = G = µs/div µs/div LARGE-SIGNAL STEP RESPONSE (G =, ) LARGE-SIGNAL STEP RESPONSE (G =, ) G = G = V/div V/div G = G = µs/div µs/div 7
APPLICATION INFORMATION Figure shows the basic connections required for operation of the. Applications with noisy or high impedance power supplies may require decoupling capacitors close to the device pins as shown. The output is referred to the output reference () terminal which is normally grounded. This must be a low-impedance connection to assure good common-mode rejection. A resistance of 8Ω in series with the pin will cause a typical device to degrade to approximately 8dB CMR (G = ). SETTING THE GAIN Gain of the is set by connecting a single external resistor,, connected between pins and 8: G = kω Commonly used gains and resistor values are shown in Figure. () The kω term in Equation comes from the sum of the two internal feedback resistors of A and A. These on-chip metal film resistors are laser trimmed to accurate absolute values. The accuracy and temperature coefficient of these resistors are included in the gain accuracy and drift specifications of the. The stability and temperature drift of the external gain setting resistor,, also affects gain. s contribution to gain accuracy and drift can be directly inferred from the gain equation (). Low resistor values required for high gain can make wiring resistance important. Sockets add to the wiring resistance which will contribute additional gain error (possibly an unstable gain error) in gains of approximately or greater. DYNAMIC PERFORMANCE The typical performance curve Gain vs Frequency shows that, despite its low quiescent current, the achieves wide bandwidth, even at high gain. This is due to the current-feedback topology of the. Settling time also remains excellent at high gain. V.µF 7 DESIRED NEAREST % GAIN (Ω) (Ω) NC NC.k 49.9k.k.4k.6k.6k.63k.6k.k.k..3 49.. 49.9. 4.9.. 4.99 V IN 8 3 Over-Voltage Protection Over-Voltage Protection A kω kω A 4.µF A 3 6 = G ( ) G = kω Load NC: No Connection. Also drawn in simplified form: V FIGURE. Basic Connections. 8
The provides excellent rejection of high frequency common-mode signals. The typical performance curve, Common-Mode Rejection vs Frequency shows this behavior. If the inputs are not properly balanced, however, common-mode signals can be converted to differential signals. Run the and connections directly adjacent each other, from the source signal all the way to the input pins. If possible use a ground plane under both input traces. Avoid running other potentially noisy lines near the inputs. NOISE AND ACCURACY PERFORMANCE The s FET input circuitry provides low input bias current and high speed. It achieves lower noise and higher accuracy with high impedance sources. With source impedances of kω to kω the INA4, INA8, or INA9 may provide lower offset voltage and drift. For very low source impedance ( kω), the INA3 may provide improved accuracy and lower noise. At very high source impedances (> MΩ) the INA6 is recommended. Input circuitry must provide a path for this input bias current if the is to operate properly. Figure 3 shows various provisions for an input bias current path. Without a bias current return path, the inputs will float to a potential which exceeds the common-mode range of the and the input amplifiers will saturate. If the differential source resistance is low, the bias current return path can be connected to one input (see the thermocouple example in Figure 3). With higher source impedance, using two resistors provides a balanced input with possible advantages of lower input offset voltage due to bias current and better high-frequency common-mode rejection. Crystal or Ceramic Transducer MΩ MΩ OFFSET TRIMMING The is laser trimmed for low offset voltage and drift. Most applications require no external offset adjustment. Figure shows an optional circuit for trimming the output offset voltage. The voltage applied to terminal is summed at the output. The op amp buffer provides low impedance at the terminal to preserve good commonmode rejection. Trim circuits with higher source impedance should be buffered with an op amp follower circuit to assure low impedance on the pin. Thermocouple kω V µa / REF Center-tap provides bias current return. OPA77 ±mv Adjustment Range kω () Ω () Ω () V REF Bridge Bridge resistance provides bias current return. NOTE: () For wider trim range required in high gains, scale resistor values larger µa / REF FIGURE. Optional Trimming of Output Offset Voltage. INPUT BIAS CURRENT RETURN PATH The input impedance of the is extremely high approximately Ω. However, a path must be provided for the input bias current of both inputs. This input bias current is typically 4pA. High input impedance means that this input bias current changes very little with varying input voltage. V FIGURE 3. Providing an Input Common-Mode Current Path. INPUT COMMON-MODE RANGE The linear input voltage range of the input circuitry of the is from approximately.v below the positive supply voltage to.v above the negative supply. A differential input voltage causes the output voltage to increase. The linear input range, however, will be limited by the output voltage swing of amplifiers A and A. So the linear common-mode input range is related to the output voltage of the complete amplifier. This behavior also depends on supply voltage see typical performance curve Input Common-Mode Range vs Output Voltage. 9
A combination of common-mode and differential input voltage can cause the output of A or A to saturate. Figure 4 shows the output voltage swing of A and A expressed in terms of a common-mode and differential input voltages. For applications where input common-mode range must be maximized, limit the output voltage swing by connecting the in a lower gain (see performance curve Input Common-Mode Voltage Range vs Output Voltage ). If necessary, add gain after the to increase the voltage swing. Input-overload can produce an output voltage that appears normal. For example, if an input overload condition drives both input amplifiers to their positive output swing limit, the difference voltage measured by the output amplifier will be near zero. The output of A 3 will be near V even though both inputs are overloaded. LOW VOLTAGE OPERATION The can be operated on power supplies as low as ±.V. Performance remains excellent with power supplies ranging from ±.V to ±8V. Most parameters vary only slightly throughout this supply voltage range see typical performance curves. Operation at very low supply voltage requires careful attention to assure that the input voltages remain within their linear range. Voltage swing requirements of internal nodes limit the input common-mode range with low power supply voltage. Typical performance curves, Input Common-Mode Range vs Output Voltage show the range of linear operation for ±V, ±V, and ±.V supplies. INPUT FILTERING The s FET input allows use of an R/C input filter without creating large offsets due to input bias current. Figure shows proper implementation of this input filter to preserve the s excellent high frequency commonmode rejection. Mismatch of the common-mode input time constant (R C and R C ), either from stray capacitance or mismatched values, causes a high frequency common-mode signal to be converted to a differential signal. This degrades common-mode rejection. The differential input capacitor, C 3, reduces the bandwidth and mitigates the effects of mismatch in C and C. Make C 3 much larger than C and C. If properly matched, C and C also improve ac CMR. V CM G V D V V D A kω G = kω A 3 = G V D V D kω V CM A V CM G V D V FIGURE 4. Voltage Swing of A and A. R C f 3dB = 4πR C 3 C V Bridge G = R C 3 Ω C R = R C = C C 3 C FET input allows use of large resistors and small capacitors. FIGURE. Input Low-Pass Filter. FIGURE 6. Bridge Transducer Amplifier.
C ±6V to ±8V Isolated Power V V ±V C R R f c = πr C ISO4 NOTE: To preserve good low frequency CMR, make R = R and C = C. FIGURE 7. High-Pass Input Filter. Isolated Common FIGURE 8. Galvanically Isolated Instrumentation Amplifier. OPA77 C nf R C MΩ.µF R kω R OPA77 f 3dB = πr C =.9Hz Make G where G = k Load V I IN L = G R FIGURE 9. AC-Coupled Instrumentation Amplifier. FIGURE. Voltage Controlled Current Source. V AC R R C C Null Transducer FIGURE. Capacitive Bridge Transducer Circuit.
V V REF Channel Channel 8 MPC8 MUX In In ADS786 Bits Out Serial FIGURE. Multiplexed-Input Data Acquisition System..kΩ.kΩ Ω NOTE: Driving the shield minimizes CMR degradation due to unequally distributed capacitance on the input line. The shield is driven at approximately V below the common-mode input voltage. Ω OPA3 For G = = Ω // (.kω) effective = Ω FIGURE 3. Shield Driver Circuit. =.6kΩ.8kΩ G = RA LA /.8kΩ Low bias current allows use with high electrode impedances. RL 39kΩ 39kΩ / OPA3 kω V G / OPA3 V G NOTE: Due to the s current-feedback topology, V G is approximately.7v less than the common-mode input voltage. This DC offset in this guard potential is satisfactory for many guarding applications. FIGURE 4. ECG Amplifier With Right-Leg Drive.
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