Course Introduction Purpose: The purpose of this course is to give you a brief overview of Freescale s S8 Controller Area Network (mscan) module, including an example for computing the mscan bit time parameters. Objectives: Explain how to connect the mscan to the CAN bus. Identify the mscan s of operation. Describe the mscan Clock and Baud Rate Configuration Describe the mscan Acceptance Filter Describe the message handling Content 55 pages 7 questions Learning Time 8 minutes or service names are the property of their respective owners. Freescale Semiconductor, Inc. 25. This course will present you with a brief overview of the Freescale S8 multi-purpose Controller Area Network (mscan) module. You will learn how the mscan operates, as well as a method to compute the CAN bit time parameters. By the end of this course, you will have a better understanding of the basic functionality of the mscan module, and you will be capable of configuring the mscan to transmit and receive messages.
S8 mscan Features Supports CAN protocol specification version 2.A/B Five receive buffers in FIFO storage scheme Three transmit buffers with local prioritization Flexible maskable identifier acceptance filter Internal time stamp support Wake up functionality with internal low pass filter Loopback for self-testing Listen-only for monitoring the bus or service names are the property of their respective owners. Freescale Semiconductor, Inc. 25. Let s start with main features of the S8 mscan. The S8 mscan has been developed according to the CAN protocol specification version 2.A/B and therefore the mscan supports standard and extended message identifier, remote frames, data frame length from up to 8 bytes and a programmable CAN bus bit rate up to Mbit/s. The S8 mscan has five receive buffers in a First-In First-Out (FIFO) storage scheme, with one foreground receive buffer and four background receive buffers. In order to use an optimized real-time concept for message transmission, the mscan supports three transmit buffers with local prioritization. For less CPU overhead, the mscan has a configurable identifier acceptance filter which prevents unwanted messages from being handled by the CPU. The mscan provides a 6 bit internal free-running counter for time stamping received or transmitted messages. To reduce power consumption, the mscan can be put in to a sleep. The mscan module has the ability to be woken up by detecting a message transfer on the CAN bus. With an implemented low pass filter, the mscan will not wake up when spikes on the CAN bus occur. The Loopback can be used for self-testing the mscan. In this, the mscan does not need to be connected to the CAN bus. A transmitted message will be handled and received internally. In order to monitor the CAN bus, the mscan uses the Listen-only. In this, the mscan receives all messages but cannot transmit messages. 2
mscan Connection to the CAN Bus CAN node CAN node 2 CAN node 3 MCU mscan 3 mapped transmit buffers foreground and 4 background receive buffers Priority based scheduler Acceptance filters Tx Rx CAN Transceiver CAN_H CAN_L CAN_H CAN_L CAN_H CAN_L Dual wire CAN bus or service names are the property of their respective owners. Freescale Semiconductor, Inc. 25. Here you can see a how the mscan should be connected to the dual wire CAN bus. The microcontroller unit (MCU) with an on-chip mscan module is not directly connected to the CAN bus. A physical layer called the CAN transceiver has to be used to connect the mscan to the CAN bus. The transceiver transforms the received signal from the dual wire bus to a signal which can be detected by the mscan via the Rx line. In transmit, the transceiver feeds back the signal from the Tx line to the Rx line to detect bit errors and transforms the signal from the Tx line to the dual wire bus signal. 3
S8 mscan Memory Map x + Offset xb + Offset xc + Offset xd + Offset xe + Offset xf + Offset x + Offset xf + Offset x2 + Offset x2f + Offset x3 + Offset x3f + Offset mscan Control Register (2 bytes) Reserved ( byte) mscan Control Register ( byte) mscan Error Counter (2 bytes) Identifier Acceptance Filter (28 bytes) Foreground Receive Buffer (6 bytes) Transmit Buffer (6 bytes) Background receive buffers are not accessible. Content is shifted to foreground buffer with FIFO scheme Background Receive Buffer (6 bytes) Background Receive Buffer 2 (6 bytes) Background Receive Buffer 3 (6 bytes) Transmit Buffer (6 bytes) Background Receive Buffer 4 (6 bytes) Transmit Buffers are paged. Selection via TX bits in mscan Transmit Buffer Selection Register Transmit Buffer 2 (6 bytes) Transmit Buffer 3 (6 bytes) or service names are the property of their respective owners. Freescale Semiconductor, Inc. 25. This is the mscan memory map. The mscan control register block is 3 bytes and includes the registers for the mscan configuration, such as the CAN bit time configuration, and the registers for controlling the message transmission and receiving. The mscan has one 8 bit receiver error counter and one 8 bit transceiver error counter. Both registers cannot be manipulated by the CPU at any time. In order to configure the mscan acceptance filter, the mscan provides 6 registers of 8 bytes. Each receive buffer is 6 bytes. Only one of the five receive buffers, the foreground receive buffer, is accessible by the CPU. If a valid message has been received in one of the four background receive buffers and the receive buffer empty flag is cleared, then the mscan will shift this message into the foreground receive buffer. The shifting of the message in the foreground receive buffer is handled with the FIFO scheme. The three transmit buffers of the S8 mscan are paged. This means that all three transmit buffers use the same address space in the memory and therefore only one of the three transmit buffers can be accessed at one time. The selection of which buffer to access must be done in the mscan Transmit Buffer Selection Register. All three transmit buffers are 6 bytes. 4
S8 mscan Modes of Operation RESET Disabled CANE = Initialization INITRQ = by CPU INITAK = by mscan CPU enters stop3 or CPU enters wait with CSWAI= or CPU enters wait with CSWAI= or CPU leaves wait INITRQ = by CPU INITAK = by mscan Run CPU enters stop, 2 or 3 or CPU enters wait with CSWAI= INITRQ = by CPU INITAK = by mscan SLPRQ = by CPU SLPAK = by mscan Wake up interrupt or SLPRQ = by CPU SLPAK = by mscan CPU leaves wait and stop3 Power Down Sleep CPU leaves low power s without the mscan Wake-up Interrupt has been occurred CPU enters stop or 2 or CPU enters wait with CSWAI= or service names are the property of their respective owners. Freescale Semiconductor, Inc. 25. Here you can see all the S8 mscan s of operation and the required parameters for a transition from one operation to another. After the MCU is reset, the S8 mscan is disabled by default. In order to enable the mscan, the mscan Enable bit has to be set in the mscan Control Register. After the mscan has been enabled, the mscan moves in to initialization. The mscan can no longer be disabled because the mscan enable bit is a write once bit, which means that it can be written just once after a reset. In order to leave the initialization, the application has to clear the Initialization Mode request bit (INITRQ) in the mscan Control Register. The mscan acknowledges the leaving of the initialization by clearing the Initialization Mode Acknowledge flag (INITAK) in the mscan Control Register. After doing so, the mscan changes the from Initialization to Run. From the Run, the mscan can enter the initialization by setting the Initialization Mode request bit to in the mscan Control Register. The mscan is in Initialization when the mscan has acknowledged the initialization by setting the Initialization Mode Acknowledge flag to in the mscan Control Register. If the CPU enters the wait with the CAN Stops in Wait Mode bit in mscan Control Register cleared, the mscan stays in run. In this case, the mscan is capable of waking up the CPU when the mscan interrupts are enabled. The mscan stays in run when the CPU leaves wait. If the CPU enters the wait with the CAN Stops in Wait Mode bit in mscan Control Register set, the mscan enters Power Down. Another cause of the transition from run to power down is when the CPU enters one of the stop s. 5
Modes of Operation - continued RESET Disabled CANE = Initialization INITRQ = by CPU INITAK = by mscan CPU enters stop3 or CPU enters wait with CSWAI= or CPU enters wait with CSWAI= or CPU leaves wait INITRQ = by CPU INITAK = by mscan Run CPU enters stop, 2 or 3 or CPU enters wait with CSWAI= INITRQ = by CPU INITAK = by mscan SLPRQ = by CPU SLPAK = by mscan Wake up interrupt or SLPRQ = by CPU SLPAK = by mscan CPU leaves wait and stop3 Power Down Sleep CPU leaves low power s without the mscan Wake-up Interrupt has been occurred CPU enters stop or 2 or CPU enters wait with CSWAI= or service names are the property of their respective owners. Freescale Semiconductor, Inc. 25. For a transition from run to sleep, the application has to set the Sleep Mode Request bit in the mscan Control Register. Once the mscan has set the Sleep Mode Acknowledge flag to in the mscan Control Register, the mscan has entered sleep. In sleep, it is possible to change to Initialization when the application sets the Initialization Mode Request bit to in the mscan Control Register. The mscan has entered the Initialization when the mscan has set the Initialization Mode Acknowledge flag to in the mscan Control Register. If the mscan is in sleep and the CPU enters stop3 or wait where the CAN Stops in Wait Mode bit is cleared in mscan Control Register, then the mscan stays in sleep. In this case, the mscan can wake up the CPU from the low power when the mscan Wake-up Interrupt is enabled and the Wake-up Enable bit is set to in mscan Control Register. If the CPU leaves the low power by any interrupt other than the mscan wake-up Interrupt, then the mscan stays in sleep. If the mscan wakes up by the Wake-up Interrupt, then the mscan changes from Sleep to run Mode. The application can also wake up the mscan by clearing the Initialization Mode request bit in the mscan Control Register. The mscan has entered the Run when the mscan has cleared the Sleep Mode Acknowledge flag in the mscan Control Register. If the CPU enters stop2 or stop or wait where the CAN Stops in Wait Mode bit is set to in mscan Control Register, then the mscan enters Power Down. The mscan can only recover from Power Down to Run when the CPU leaves the wait or stop3. In the case where the CPU leaves stop or stop2, a reset has occurred, which means that the mscan has been reset and is Disabled. The application has to reinitialize the mscan when the CPU has left stop or stop2. 6
RESET Disabled Initialization Question Label each of operation correctly by dragging each label to its correct location on the diagram. Click Done when you are finished. CANE = INITRQ = by CPU INITAK = by mscan INITRQ = by CPU INITAK = by mscan INITRQ = by CPU INITAK = by mscan Initialization Run CPU enters wait with CSWAI= or CPU leaves wait Done Run CPU enters stop, 2 or 3 or CPU enters wait with CSWAI= SLPRQ = by CPU SLPAK = by mscan Wake up interrupt or SLPRQ = by CPU SLPAK = by mscan CPU leaves wait and stop3 Power Down or service names are the property of their respective owners. Freescale Semiconductor, Inc. 25. Sleep CPU enters stop or 2 or CPU enters wait with CSWAI= Sleep Power Down Show Solution Let s take a moment to review the mscan s of operation. 7
Disabled Mode Default after a MCU RESET CAN Enable (CANE) bit is write once bit CANCTL, CANBTR, CANBTR, CANIDAR and CANIDMR are accessible Other mscan registers are held in reset state or service names are the property of their respective owners. Freescale Semiconductor, Inc. 25. After MCU reset, the mscan is disabled, which is indicated with the cleared CAN Enable bit in the MSCAN Control Register. The CAN Enable bit is a write once bit, which means that it can be written just once after a reset. The mscan Control Register, the mscan Bus Timing Register and, the mscan Identifier Acceptance Registers and the mscan Identifier Mask Registers are accessible when the mscan is disabled. The other registers are held in reset state. 8
Initialization Mode When entering Initialization Any on-going transmission or reception is aborted > can cause CAN protocol violations Loss of synchronization to the CAN bus TXCAN pin will be driven into a recessive state During Initialization Mode mscan is stopped Enables the write access to the registers CANCTL, CANBTR, CANBTR, CANIDAC, CANIDAR and CANIDMR CANCTL, CANRFLG, CANRIER, CANTFLG, CANTIER, CANTARQ, CANTAACK and CANBSEL are held in reset state or service names are the property of their respective owners. Freescale Semiconductor, Inc. 25. When the mscan enters the Initialization, all on-going transmissions or receptions are immediately aborted. This can cause CAN protocol violations. Furthermore, the mscan loses the synchronization to the CAN bus and the TXCAN pin is driven into a recessive state. During the Initialization, the mscan is stopped. The initialization enables the write access for the mscan Control Register, the mscan Bus Timing Register and, the mscan Identifier Acceptance Registers and the mscan Identifier Mask Register. The following registers are held in reset state and cannot be written: the mscan Control Register, the mscan Receiver Flag Register, the mscan Receiver Interrupt Enable Register, the mscan Transmitter Flag Register, the mscan Transmitter Interrupt Enable Register, the mscan Transmitter Message Abort Request Register, the mscan Transmitter Message Abort Acknowledge Register, and the mscan Transmit Buffer Selection Register. 9
Safe Entry Into Init Mode Initialization INITRQ = by CPU INITAK = by mscan Run SLPRQ = by CPU SLPAK = by mscan with WUPE= Sleep or service names are the property of their respective owners. Freescale Semiconductor, Inc. 25. Since the direct transition from Run into Initialization can cause CAN protocol violations, direct transition should not be used. For a safe transfer from the Run to Initialization, the mscan should be transferred first into the sleep where the Wake-Up Enable is cleared in mscan Control Register. This prevents the mscan from waking up by detecting traffic on the CAN bus. In order to transfer the mscan from Run to Sleep, the application will set the Sleep Mode Request bit to in the mscan Control Register. The mscan has entered the Sleep Mode when the mscan has set the Sleep Mode Acknowledge flag to in mscan Control Register. After the mscan has entered the sleep, it can be transferred into Initialization safely by setting the Initialization Mode request bit to in the mscan Control Register and waiting until the mscan has set the Initialization Mode Acknowledge flag to in the mscan Control Register.
Sleep Mode The mscan acknowledges the sleep when the mscan is idle All message buffers have been transmitted or aborted successfully A current receiving message has been fully received During Sleep : mscan clock is disabled Registers are still accessible except the registers which are accessible in Initialization only TXCAN pin is in the recessive state Transmit buffers and the foreground receive buffer are accessible Shifting messages from background to foreground receive buffer will not take place or service names are the property of their respective owners. Freescale Semiconductor, Inc. 25. It is safer to enter into the sleep before entering the Initialization because the mscan will not acknowledge the sleep before the mscan has finished all its current jobs. This means that all message buffers have been transmitted or aborted successfully and are empty. If the mscan is receiving a message while requesting the sleep, then the mscan will wait until this message has been received and the CAN bus becomes idle. In the case where the mscan is idle, it will immediately acknowledge the sleep. During the sleep, the mscan clock is disabled. However, all registers, except the registers which are accessible in initialization only, are accessible and the TXCAN pin is in the recessive state. All three transmit message buffers are accessible. Therefore it is possible to schedule the transmit message buffers for transmission and to request an abort of a transmission, but neither the transmission nor the abort will take place during sleep. A received message that has been shifted to the foreground receive buffer before entering the sleep is accessible, but a shifting of message from the background into the foreground receive buffer is not performed in sleep.
Programmable Wake Up mscan can be woken up by CPU setting SLPRQ = and mscan sets SLPACK = Detecting traffic on the CAN bus > Wake-Up Enable bit (WUPE) = > Optional wake up features are Wake-up detection by the application polling the wake-up interrupt flag mscan generates Wake-Up Interrupt Usage of low pass filter with configuration of the Wake-Up Mode bit (WUPM) WUPM = : low pass filter is disabled and any dominant level will wake up the mscan WUPM = : low pass filter is enabled and wakes up the mscan with a dominant pulse > 5µs or service names are the property of their respective owners. Freescale Semiconductor, Inc. 25. The mscan has a programmable wake up functionality from sleep. The mscan can be woken up by the CPU when the application clears the Sleep Mode Request bit in the mscan Control Register. The mscan signals the leaving of the sleep by clearing the Sleep Mode Acknowledge flag in the mscan Control Register. Another way to wake up the mscan is when traffic has been detected on the CAN bus. This wake up feature has to be enabled by setting the Wake-Up Enable bit to in mscan Control Register. There are two ways to detect an mscan wake up by the application. The first way is to poll the Wake-up Interrupt flag in the mscan Receiver Flag Register. The second way is to set the Wake-up Interrupt Enable bit in the mscan Receiver Interrupt Enable Register and the mscan generates an interrupt when mscan has been woken up. With the Wake-Up Mode bit in the mscan Control Register, a low pass filter on the RXCAN pin can be enabled during sleep. If the low pass filter is disabled, then any dominant level on the CAN bus will wake up the mscan. If the low pass filter is enabled, then a dominant pulse greater-than or equal-to 5µs will wake up the mscan. The low pass filter prevents the wake up of the mscan by unwanted spikes on the CAN bus. 2
Power Down Mode When entering Power Down All on-going transmissions or receptions areaborted immediately > can cause CAN protocol violations Loss of synchronization to the CAN bus TXCAN pin will be driven into a recessive state During Power Down mscan is stopped All registers are not accessible or service names are the property of their respective owners. Freescale Semiconductor, Inc. 25. When the mscan enters the Power Down, all on-going transmissions and receptions are immediately aborted. This may cause CAN protocol violations. Furthermore, the mscan loses the synchronization to the CAN bus and the TXCAN pin is driven into a recessive state. During the Power Down, the mscan is stopped and the mscan registers are not accessible. 3
Safe Entry into Power Down Mode Run SLPRQ = by CPU SLPAK = by mscan Sleep CPU enters stop3 or CPU enters wait with CSWAI= CPU enters stop or 2 or CPU enters wait with CSWAI= Power Down or service names are the property of their respective owners. Freescale Semiconductor, Inc. 25. Since the direct transition from Run into Power Down can cause CAN protocol violations, the direct transition should not be used. For a safe transfer from Run into Power Down, the mscan should be transferred first into the sleep. The Wake-Up Enable bit in mscan Control Register must be cleared in order to prevent the mscan from waking up by detecting traffic on the CAN bus. In order to transfer the mscan from Run to Sleep, the application will set the Sleep Mode Request bit to in the mscan Control Register. The mscan has entered the Sleep Mode when the mscan has set the Sleep Mode Acknowledge flag to in mscan Control Register. After the mscan has entered the sleep, it can be transferred into Power Down safely when the CPU enters stop, stop2, or wait with the CAN Stops in Wait Mode bit set to in mscan Control Register. If the mscan is in sleep and the CPU enters stop3 or wait with the CAN Stops in Wait Mode bit cleared in mscan Control Register, then the mscan stays in sleep. The mscan can then wake up the CPU with the mscan wake-up interrupt. 4
Run Mode Initialization INITRQ = INITAK = INITRQ = INITAK = INITRQ = INITAK = Listen INITRQ = INITAK = LOOPB = LISTEN = Loopback INITRQ = INITAK = LOOPB = LISTEN = INITRQ = INITAK = LOOPB = LISTEN = Normal run Run Mode or service names are the property of their respective owners. Freescale Semiconductor, Inc. 25. The run of the mscan has three sub s: the listen, the loopback, and the normal run. The three run s are defined with the bits LOOPB and LISTEN in MSCAN Control Register. mscan Control Register is write-accessible only in Initialization and therefore the Run s can only be set in Initialization. In order to run in Listen, the LOOPB has to be cleared and the LISTEN bit has to be set to in Initialization. In order to run in Loopback, the LOOPB has to be set to and the LISTEN bit has to be cleared in Initialization. In Normal run, both the LOOPB and the LISTEN bit have to be cleared when leaving the Initialization Mode. 5
Run in Listen Mode mscan monitors the CAN bus Receives any message on the CAN bus that has been received successfully Sends recessive bits only Dominant bits that are required to be sent by CAN protocol will be routed internally mscan cannot transmit a message or service names are the property of their respective owners. Freescale Semiconductor, Inc. 25. In Listen, the mscan monitors the CAN bus. The mscan can receive all data frame messages and remote frame messages. If bits must be sent to the CAN bus, then the mscan can only send recessive bits while in this. All bits that have to be sent as dominant bits will be routed internally and are not presented on the CAN bus. The mscan cannot transmit a message on the CAN bus in Listen. 6
Run in Loopback Mode Self-test operation for the mscan TXCAN pin is in recessive state Transmitted messages are routed internally and will be received by the mscan mscan ignores the acknowledge field of the message field or service names are the property of their respective owners. Freescale Semiconductor, Inc. 25. In loopback, the mscan performs an internal loopback that can be used for self-test operation. The TXCAN pin goes in to a recessive state. Message transmission is routed internally and will not be presented to the CAN bus. The transmitted message is handled by the mscan as a normal received message that has been sent by a remote node. The receive and transmit interrupts are generated when enabled. No message will be received from the CAN bus. To operate properly, the mscan ignores the acknowledge field of the message field. 7
Run in Normal Mode Operates according to the CAN Protocol Receives and transmits messages normally or service names are the property of their respective owners. Freescale Semiconductor, Inc. 25. In Normal run, the mscan operates according to the CAN protocol. It receives messages from the CAN bus and transmits messages to the CAN bus. 8
Question Which of the following is NOT a sub of the mscan run? Click the correct answer and then click Done. A. Loopback B. Listen C. Sleep D. Normal run Done or service names are the property of their respective owners. Freescale Semiconductor, Inc. 25. Consider this question about the mscan s of operation. Correct! Sleep is not a sub of the mscan run. The three run s (loopback, listen, and normal run) are defined with the bits LOOPB and LISTEN in MSCAN Control Register. 9
mscan Input Clock Configuration Bus clock mscan clock Oscillator clock CLKSRC (mscan Clock Source) or service names are the property of their respective owners. Freescale Semiconductor, Inc. 25. The mscan can choose one of two input clock sources. The default clock source is the external oscillator clock. The second clock source is the S8 bus clock. With the mscan Clock Source bit in mscan Control Register, the required clock source can be configured as the mscan clock. In order to configure the clock source, the mscan has to be in Initialization since it is the only in which the mscan Control Register is writeable. 2
mscan Input Clock Configuration MCG CLKS Internal Clock reference PLLS FLL PLL MCGOUT 2 Bus clock mscan clock CLKSRC Oscillator clock ERCLKEN MCGERCLK External Oscillator or service names are the property of their respective owners. Freescale Semiconductor, Inc. 25. The current S8 devices with an on-chip mscan have a Multi-Purpose Clock Generator (MCG) module to generate the required clock signals. The MCG can provide numerous clock signals for the MCU, including the oscillator clock, which is called the MCG External Reference Clock, and the Bus clock, which is the MCG Output Clock divided by two. If the MCG External Reference Clock is to be used as the clock source for the mscan, then this clock must be enabled during the MCG initialization. In order to enable the MCG External Reference Clock the bit External Reference Enable in MCG Control Register must be set to. If the Bus clock is selected as the mscan clock source, then the MCG Output Clock divided by two is used. The MCG Output Clock can be the output clock from the PLL or FLL, the internal clock reference, or the external clock reference. This depends on the configuration of the Clock Source Select bit in MCG Control Register and the PLL Select bit in MCG Control Register 3. The PLL and FLL should not be used because they generate a jitter in the clock that can affect the CAN communication. Furthermore, the internal clock reference is not accurate enough for the CAN communication. Consequently, if the bus clock is selected as the clock source, then the MCG Output Clock must be driven by the external clock reference. 2
CAN Bit Structure SYNCH_SEG PROP_SEG PHASE_SEG PHASE_SEG2 Sample Point Nominal CAN bit time or service names are the property of their respective owners. Freescale Semiconductor, Inc. 25. The CAN protocol specification states that the nominal CAN bus bit time is divided into four separate, non-overlapping time segments which are: the synchronization segment, the propagation time segment, the phase buffer segment, and the phase buffer segment 2. The Sample Point defines the point at which the mscan samples the CAN bus. It is configurable so that one or three sample points can be chosen for the application. 22
Generating CAN Bit Time Oscillator or Bus Clock Baud Rate Prescaler CAN System Clock t t Q CAN Bit Period PROP_SEG PHASE_SEG PHASE_SEG2 =..8 t Q =..8 t Q =MAX(IPT,t PHASE_SEG ) SYNC_SEG = t Q CAN bit time = 8..25 t Q or service names are the property of their respective owners. Freescale Semiconductor, Inc. 25. The S8 mscan can either be clocked with the MCU bus or the oscillator clock divided by a programmable prescaler called the Baud Rate Prescaler. The period of the generated mscan system clock is called t Q or Time Quantum. Each time segment of the CAN bit is an integer multiple of the Time Quantum t Q. The synchronization segment is not programmable and is fixed at one Time Quantum. The propagation time segment is programmable and has a range from to 8 Time Quanta. The phase buffer segment is programmable and also has a range from to 8 Time Quanta. The phase buffer segment 2 is programmable and its duration is the maximum of the Information Processing Time and the duration of phase buffer segment. The Information Processing Time is 2 Time Quanta except if 3 sample points are selected, in which case the Information Processing Time is 3 Time Quanta. The CAN protocol defines a range of 8 to 25 Time Quanta per CAN bit time. 23
Synchronization Jump Width (SJW) Number of Time Quanta by which a bit period may be extended or shortened due to re-synchronization Cannot exceed 4 Time Quanta and must not exceed the number of Time Quanta in the PHASE_SEG Minimum value is Time Quantum or service names are the property of their respective owners. Freescale Semiconductor, Inc. 25. The last CAN bus bit timing value that can be configured is the synchronization jump width. The synchronization jump width is the number of Time Quanta by which a bit period may be extended or shortened due to resynchronisation. The re-synchronization jump width cannot exceed 4 Time Quanta, nor must it exceed the number of Time Quanta in the phase buffer segment. The minimum value for the re-synchronization jump width is Time Quantum. 24
Question Which time segment of the CAN bit is indicated by the red arrow below? Click the correct answer, then click Done. A. SYNC SEG B. PROP SEG C. PHASE SEG D. PHASE SEG2 Oscillator or Bus Clock CAN System Clock Baud Rate Prescaler t t Q CAN Bit Period Done or service names are the property of their respective owners. Freescale Semiconductor, Inc. 25. CAN bit time = 8..25 t Q Here s a question for you about generating CAN bit time. Correct. The red arrow is pointing to the synchronization segment (SYNC SEG). The SYNC SEG is not programmable and is fixed at one Time Quantum. 25
Calculation of the Bit Timing Step : Determine correct mscan system clock Calculate CAN system clock mscan system clock = mscan input clock Baud Rate Prescaler Calculate the Number of Time Quanta per CAN bus bit time Number of Time Quanta per bit = CAN bus bit time mscan system clock Check number of Time Quanta per bit. Choose a higher or lower CAN system frequency and re-calculate when the value is not: An integer value In the range of 8 to 25 t Q or service names are the property of their respective owners. Freescale Semiconductor, Inc. 25. There are six steps to determine the CAN bit time parameters. The first step is to determine the correct mscan system clock. To do this, you must first define the mscan input clock and the mscan Baud Rate Prescaler, then calculate the mscan system clock by dividing the mscan input clock by the Baud Rate Prescaler. Next calculate the number of Time Quanta per CAN bus bit time by dividing the CAN bus bit time by the mscan system clock. If the calculated Number of Time Quanta per bit is not an integer value or in the range of 8 to 25, then change the CAN system clock and re-calculate the Number of Time Quanta per bit. 26
Calculation of the Bit Timing Step 2: Determine duration of propagation time segment Depends on the propagation delay of the: Transmitter (t Tx ) and receiver (t Rx ) part of the physical interface Signal along the longest length of the bus (t BUS ) between two nodes Formula to calculate the PROP_SEG ( t + t t ) 2 BUS Tx + PROP _ SEG = ROUND _ UP tq If the PROP_SEG is > 8, go back to step and choose a lower mscan system frequency. Rx or service names are the property of their respective owners. Freescale Semiconductor, Inc. 25. The second step is to determine the duration of the propagation time segment. The duration of the propagation time segment depends on the propagation delay of the transmitter and receiver of the physical interface and the propagation delay of the signal along the longest length of the bus between two nodes. The Formula to calculate the propagation time segment is shown here. If the propagation time segment is greater than 8, go back to step and choose a lower mscan system frequency. 27
Calculation of the Bit Timing Step 3: Determine duration of phase buffer segment and 2 Calculate the Time Quanta which has to be assigned to PHASE_SEG and PHASE_SEG2. PHASE_SEG+PHASE_SEG2 = Number of Time Quanta per bit PROP_SEG Depending on the result, do one of the following: Result < 3 Go back to step and select a higher mscan system frequency. Result is Odd Add to PROP_SEG and re-calculate the unused and >3 Time Quanta. Result = 3 PHASE_SEG is equal and PHASE_SEG2 is equal 2 and just one sample per bit must be used. Else Divide remaining number by 2 and assign the result to PHASE_SEG and PHASE_SEG2. In this case, one sample point or three sample points can be used. or service names are the property of their respective owners. Freescale Semiconductor, Inc. 25. The third step is to determine duration of phase buffer segment and 2. In order to do so, subtract from the Number of Time Quanta per bit the Time Quanta of the propagation time segment and Time Quantum for the synchronization segment. After calculating the remaining number of Time Quanta per bit, follow the steps below. If the remaining number is less than 3, go back to step and select a higher mscan system frequency. If the remaining number is an odd number greater than 3, add to the propagation time segment and re-calculate the Time Quanta which has to be assigned to phase buffer segment and 2. If the remaining number is equal to 3, then phase buffer segment is equal to and phase buffer segment 2 is equal to 2 and just sample per bit must be configured. Otherwise divide the remaining number by 2 and assign the result to phase buffer segment and 2. In this case, sample point or 3 sample points can be used. 28
Calculation of the Bit Timing Step 4: Determine duration of synchronization jump width (SJW) SJW is smaller of 4 and PHASE_SEG. That means that If the PHASE_SEG is greater than 4, the SJW is 4. Otherwise the SJW is equal to PHASE_SEG. or service names are the property of their respective owners. Freescale Semiconductor, Inc. 25. The fourth step is to determine duration of synchronization jump width. The synchronization jump width is the smaller of 4 and phase buffer segment. This means that if the phase buffer segment is greater than 4, the synchronization jump width is 4. Otherwise the synchronization jump with is equal to phase buffer segment. 29
Calculation of the Bit Timing Step 5: Determine values for the mscan Bus Timing Register mscan Bus Timing Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit Bit SJW SJW BRP5 BRP4 BRP3 BRP2 BRP BRP SJW- which define the synchronization jump width where: SJW- = SJW - BRP-5 which define the Baud Rate Prescaler with where: BRP-5 = Baud Rate Prescaler - CANBTR = ((SJW-)<<6) (PRESCALER-) or service names are the property of their respective owners. Freescale Semiconductor, Inc. 25. The fifth step is to determine values for the mscan Bus Timing Register. The mscan Bus Timing Register contains the synchronization jump width and the mscan Baud Rate Prescaler. The register value of the synchronization jump width is equal to the calculated synchronization jump width minus. The register value of the mscan Baud Rate Prescaler is equal to the calculated mscan Baud Rate Prescaler minus. By configuring the mscan Bus Timing Register as shown here, the calculated values will be placed into the register correctly. 3
Calculation of the Bit Timing Step 6: Determine values for the mscan Bus Timing Register mscan Bus Timing Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit Bit SAMP TSEG22 TSEG2 TSEG2 TSEG3 TSEG2 TSEG TSEG SAMP which defines the number of samples per bit time. or 3 TSEG2-2 which define the time segment 2 where: TSEG2-2 = PHASE_SEG2 - TSEG-3 bits defines the time segment (TSEG) where: TSEG2-3 = PROP_SEG + PHASE_SEG - CANBTR = (SAMPLE<<7) ((PHASE_SEG2-)<<4) (PROP_SEG+PHASE_SEG-) or service names are the property of their respective owners. Freescale Semiconductor, Inc. 25. The last step is to determine values for the mscan Bus Timing Register. The mscan Bus Timing Register defines the number of sample points and the time segments and 2. The number of sample points can be or 3. The time segment 2 is equal to the phase buffer segment 2 minus. The time segment is phase buffer segment plus propagation segment minus. By configuring the mscan Bus Timing Register as shown here, the calculated values will be placed into the register correctly. 3
Question When calculating the Time Quanta that has to be assigned to PHASE SEG and 2, what should be done if the result is <3? Click the correct answer, then click done. A. Add to PROP SEG and re-calculate the unused Time Quanta. B. Go back to step and select a higher mscan system frequency. C. Divide the remaining number by 2 and assign the result to PHASE SEG and 2. D. Nothing else should be done. Done or service names are the property of their respective owners. Freescale Semiconductor, Inc. 25. Here s a question about calculating the bit timing parameters. Correct! When calculating the Time Quanta that has to be assigned to PHASE SEG and 2, if the result is <3, then you need to go back to step and select a higher mscan system frequency. 32
mscan Acceptance Filter Prevents certain unwanted received messages from being handled by the CPU Size of the filter is configurable Two 32 bit Filters Four 6 bit Filters Eight 8 bit filters or service names are the property of their respective owners. Freescale Semiconductor, Inc. 25. Because the CAN standard allows a very large number of nodes on a single network, if each individual node received all transmitted messages, the CPU would spend a lot of time just analyzing messages which are usually not of interest to that particular node. Typically a node is just interested in a subset of the transmitted messages. In order to decrease the evaluation time of the received messages, the mscan module provides filters which prevent certain unwanted messages from being handled by the CPU. The size of the S8 mscan filter is configurable in the MSCAN Identifier Acceptance Control Register. 33
32 Bit Filter Extended CAN ID Standard CAN ID ID28 IDR ID2 ID2 IDR ID5 ID4 IDR2 ID7 ID6 IDR3 IDR ID ID3 ID2 IDR IDE RTR AM7 IDMR AM AM7 IDMR AM IDMR2 AM7 AM AM7 IDMR3 AM Filter AC7 IDAR AC AC7 IDAR AC AC7 IDAR2 AC AC7 IDAR3 AC ID Accepted (Filter Hit) AM7 IDMR4 AM AM7 IDMR5 AM IDMR6 AM7 AM AM7 IDMR7 AM Filter 2 AC7 IDAR4 AC AC7 IDAR5 AC AC7 IDAR6 AC AC7 IDAR7 AC ID Accepted (Filter Hit) or service names are the property of their respective owners. Freescale Semiconductor, Inc. 25. Depending on the Filter configuration the mscan provides two 32- bit Filters. In order to configure Filter the MSCAN Identifier Acceptance Register to 3 and the MSCAN Identifier Mask Register to 3 are used. In order to configure Filter2 the MSCAN Identifier Acceptance Register 4 to 7 and the MSCAN Identifier Mask Register 4 to 7 are used. For the extended message the 32 bit filter checks for the 29 bits of the ID plus the remote transmition request bit plus the identifier extension bit and the substitute remote request bit. If a standard message has been received, then the bits of the ID plus the remote transmission request (RTR) bit plus the identifier extension (IDE) bit are checked. 34
6 Bit Filter Extended CAN ID Standard CAN ID Filter Filter 2 IDR ID28 IDR ID IDMR AM7 IDAR AC7 ID2 ID2 IDR ID5 IDR2 ID3 ID2 AM AM7 AC AC7 IDR IDE IDMR IDAR AM AC ID Accepted (Filter Hit) IDMR2 AM7 IDAR2 AC7 AM AM7 AC AC7 IDMR3 IDAR3 AM AC ID4 ID7 ID6 IDR3 RTR ID Accepted (Filter Hit) Filter 3 IDMR4 AM7 IDAR4 AC7 AM AM7 AC AC7 IDMR5 IDAR5 AM AC ID Accepted (Filter 2 Hit) Filter 4 IDMR6 AM7 IDAR6 AC7 AM AM7 AC AC7 IDMR7 IDAR7 AM AC ID Accepted (Filter 3 Hit) or service names are the property of their respective owners. Freescale Semiconductor, Inc. 25. Depending on the Filter configuration the mscan provides four 6- bit Filters. In order to configure Filter, the MSCAN Identifier Acceptance Register to and the MSCAN Identifier Mask Register to are used. In order to configure Filter 2, the MSCAN Identifier Acceptance Register 2 to 3 and the MSCAN Identifier Mask Register 2 to 3 are used. In order to configure Filter 3, the MSCAN Identifier Acceptance Register 4 to 5 and the MSCAN Identifier Mask Register 4 to 5 are used. In order to configure Filter 4, the MSCAN Identifier Acceptance Register 6 to 7 and the MSCAN Identifier Mask Register 6 to 7 are used. For the extended message the 6 bit filter checks the 4 most significant bits of the ID plus the identifier extension bit and the substitute remote request bit. If a standard message has been received, then the bits of the ID plus the remote transmission request (RTR) bit plus the identifier extension (IDE) bit are checked. 35
8 Bit Filter IDR IDR IDR2 ID28 ID2 ID2 ID5 ID4 ID7 ID6 IDR IDR ID ID3 ID2 IDE AM7 IDMR AM AC7 IDAR AC ID Accepted (Filter Hit) AM7 IDMR AM AC7 IDAR AC ID Accepted (Filter Hit) AM7 IDMR2 AM AC7 IDAR2 AC ID Accepted (Filter 2 Hit) AM7 IDMR3 AM AC7 IDAR3 AC ID Accepted (Filter 3 Hit) AM7 IDMR4 AM AC7 IDAR4 AC ID Accepted (Filter 4 Hit) AM7 IDMR5 AM AC7 IDAR5 AC ID Accepted (Filter 5 Hit) AM7 IDMR6 AM AC7 IDAR6 AC ID Accepted (Filter 6 Hit) AM7 IDMR7 AM AC7 IDAR7 AC IDR3 RTR Freescale ID Accepted and the Freescale (Filter logo 7 Hit) are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 25. The eight 8 bit filters check the 8 most significant bits of the ID of the standard ID and extended ID message. 36
mscan Filter Functionality Message ID will be compared against following values Logic Logic Don t care Example Bit Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bit Filter Value X X Message Message 2 Message 3 or service names are the property of their respective owners. Freescale Semiconductor, Inc. 25. A bit of the message ID, which is used for filtering, will be compared against the following values: Logic, Logic, and Don t care. For example, the following filter value is used where represents the logical, represents the logical, X represents don t care, and the bits of the standard message ID shall be filtered. In this case, the message ID bits and 6 are ignored because these bits are represented as X in the filter value. The other filter bits will be compared against the received message ID. In this example, the Message 2 will be rejected since the bit 8 of the message ID is different from the bit 8 of the filter value. 37
mscan Filter Config Registers The S8 mscan filter has two configuration registers MSCAN Identifier Mask Register -7 CANIDMR MSCAN Identifier Acceptance Register -7 CANIDAR Example Bit Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bit Filter Value X X CANIDMR CANIDAR or service names are the property of their respective owners. Freescale Semiconductor, Inc. 25. The S8 mscan filter has two configuration registers. The MSCAN Identifier Mask Register to 7 define which bits are don t care and which bits are used for comparing. The MSCAN Identifier Acceptance Register to 7 defines the compare value of the bits which are used for comparing. In order to configure the Filter with a value as highlighted, the MSCAN Identifier Mask Register and the MSCAN Identifier Acceptance Register have to be configured as follows. The Filter bits which are defined as don t care must be set to in the MSCAN Identifier Mask Register. The bits which are in the MSCAN Identifier Mask Register are used for comparing against the MSCAN Identifier Acceptance Register. The bits 6 and, which are don t care, can be or in the MSCAN Identifier Acceptance Register since they are meaningless. 38
Acceptance Filters mscan has 2, 4, or 8 acceptance filters All received messages will be compared to all available filters. A message which is rejected by a filter can pass another filter. Example Bit Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bit Filter Value X X Filter Value 2 X X X Message Message 2 Message 3 or service names are the property of their respective owners. Freescale Semiconductor, Inc. 25. Depending on its configuration, the S8 mscan has 2, 4, or 8 filters and all received messages will be compared to all available filters. This means that if a message is rejected by one filter, the same message can pass another filter. The same sample is used from the previous page plus an additional filter value 2. The Filter accepts Message and 3. The Filter 2 accepts Message 2 and 3. The message 3 is accepted by both filters. In the case where a message has been accepted by more than one filter, the filter with the lowest number has the highest priority and will be indicated as filter hit in the MSCAN Identifier Acceptance Control Register. 39
Is the following statement true or false? Click on the correct answer, then click Done when you are finished. The size of the S8 mscan filter is configurable. A. True B. False Question Done or service names are the property of their respective owners. Freescale Semiconductor, Inc. 25. Please take a moment to consider this question about the mscan acceptance filter. Correct. The size of the S8 mscan filter is configurable. There are two 32 bit filters, four 6 bit filters, and eight 8 bit filters. They are configurable in the mscan Identifier Acceptance Control Register. 4
Message Buffer Organization Offset Address Register xx Identifier Register xx Identifier Register xx2 Identifier Register 2 xx3 Identifier Register 3 xx4 Data Segment Register xx5 Data Segment Register xx6 Data Segment Register 2 xx7 Data Segment Register 3 xx8 Data Segment Register 4 xx9 Data Segment Register 5 xxa Data Segment Register 6 xxb Data Segment Register 7 xxc Data Length Register xxd Transmit Buffer Priority Register xxe Time Stamp Register High 2 xxf Time stamp Register Low 2 NOT AVAIALBLE Freescale and the Freescale FOR logo are RECEIVE trademarks of Freescale BUFFERS Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 25. 2 READ-ONLY FOR CPU You can see how the S8 mscan buffers are organized. The mscan consists of four Identifier Registers. It has eight Data Segment Registers. It also has one Data Length Register. The mscan has one Transmit Buffer Priority Register, which is available for the transmit buffer only. It also has at least two Time Stamp Registers, which are read-only for the CPU. 4
Identifier Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bit IDR ID ID9 ID8 ID7 ID6 ID5 ID4 ID3 IDR ID2 ID ID RTR IDE IDR2 IDR3 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bit IDR ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID2 IDR ID2 ID9 ID8 SRR IDE ID7 ID6 ID5 IDR2 ID4 ID3 ID2 ID ID ID9 ID8 ID7 IDR3 ID6 ID5 ID4 ID3 ID2 or service names are the property of their respective owners. Freescale Semiconductor, Inc. 25. ID ID RTR Here you can see how the Identifier Registers are used for Standard Identifier. The standard identifier consists of identifier bits, the RTR bit, and the IDE bit. The identifier bits do not just define the message ID, they also define the priority of the message during CAN bus arbitration. The highest priority is assigned to the smallest binary number. The RTR indicates the status of the remote transmission request bit in the CAN message frame. In case of a transmit buffer, this bit defines whether a remote frame request or a data frame shall be sent. For the receive buffer, this bit indicates whether the remote frame has been requested and an answer message must be sent. The IDE defines whether the message ID is a standard or extended ID. For the standard ID, this bit is always. The grey bits are unused fields for the standard identifier. The extended message identifier consists of 29 identifier bits, the RTR bit, the IDE bit and the SRR bit. The 29 identifier bits define the message ID and the priority of the message during CAN bus arbitration. The highest priority is assigned to the smallest binary number. The SRR is a fixed recessive bit. The user must set this to for the transmission buffer and it is stored automatically for the receive buffer. The IDE defines whether the message ID is a standard or extended ID. For the extended ID, this bit is always. The RTR indicates the status of the remote transmission request bit in the CAN message frame. In case of the transmit buffer, this bit defines whether a remote frame request shall be sent or not. For the receive buffer, this bit indicates whether the remote frame has been requested and an answer message must be sent. 42
Data Segment Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bit DR D7 D6 D5 D4 D3 D2 D D DR D7 D6 D5 D4 D3 D2 D D DR2 D7 D6 D5 D4 D3 D2 D D DR3 D7 D6 D5 D4 D3 D2 D D DR4 D7 D6 D5 D4 D3 D2 D D DR5 D7 D6 D5 D4 D3 D2 D D DR6 D7 D6 D5 D4 D3 D2 D D DR7 D7 D6 D5 D4 D3 D2 D D or service names are the property of their respective owners. Freescale Semiconductor, Inc. 25. For the transmit buffer, the data segment registers contain the data that shall be transmitted. For the receive buffer, the data segment registers contain the data that has been received. The number of bytes that have to be transmitted or have been received is dependent on the content of the Data Length Register. 43
Data Length Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bit DLR DLC3 DLC2 DLC DLC or service names are the property of their respective owners. Freescale Semiconductor, Inc. 25. The Data Length Register defines how many bytes shall be sent or how many bytes have been received. The range of the data length is from to 8. 44
Tx Buffer Priority Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bit TBPR P7 P6 P5 P4 P3 P2 P P or service names are the property of their respective owners. Freescale Semiconductor, Inc. 25. The Transmit Buffer Priority Register defines the local priority of the transmit buffer, which is used for the internal prioritization of the message transmission. The transmit buffer with the smallest binary number in the transmit buffer priority register has the highest priority. This mechanism is used when more than one transmit buffer is ready to transmit a message. In the case where more than one transmit buffers have the same local priority, the buffer with the lowest index number will win the prioritization. 45
Time Stamp Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bit TSRH TSR5 TSR4 TSR3 TSR2 TSR TSR TSR9 TSR8 TSRL TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR TSR or service names are the property of their respective owners. Freescale Semiconductor, Inc. 25. The Time Stamp Register can only be read by the CPU. Any write to this register has no effect. If the time stamp mechanism is enabled by setting the Timer Enable bit in mscan Control register, then the mscan writes a time stamp from the mscan internal free running timer into the Time Stamp Registers of the active transmit or receive buffer after a message has been acknowledged on the CAN bus. For the transmit buffer, this time stamp is only accessible after this buffer has been flagged empty. 46