Lecture # 1 E3-238 : Analog VLSI Circuits Associate Professor, ECE Department Indian Institute of Science, Bangalore-560012 Email: navakant@ece.iisc.ernet.in URL: http://ece.iisc.ernet.in/~navakant August 2007 1
Logistics Instructors : Navakanta Bhat, Sundarajan Krishnan, Srinivasan Teaching Assistants : Rakesh Gnana David, Manodeepan Sahu Class timings : Friday 8:00am-9:00am Saturday 9:00am-11:00am Lab session : Involves circuit design, simulation and analysis using any circuit simulator (Spice3f5, WinSpice, T-Spice, P-Spice, H-Spice, Spectre, Eldo ) Grading : Home work (lab assignments) : 20% Mid term exam : 20 % Course project : 20 % Final exam : 40% 2
List of Reference books Due to the advent of mixed signal SOCs, numerous books have been published on Analog Design. A partial list : 1. Analog CMOS Design Razavi, McGraw Hill Publication 2. CMOS: Circuit Design, Layout, and Simulation Boise, Baker, Lee, Prentice Hall Publication 3. Analog VLSI : Signal and Information Processing Ismail and Feiz, McGraw Hill Publication 4. Analysis and Design of Analog Integrated Circuits Gray and Meyer, Wiley Publication 5. Trade-offs in Analog Circuit Design: The Designer s Companion, Ed: C. Toumazou and other, Kluwer 3
Course details Logistics, Technology trend, Need for Analog design, Simple long channel MOSFET theory, Sub-micron transistor theory, SCE, NWE, DIBL, Sub-threshold conduction, Reliability, Digital metrics, Analog metrics SPICE simulator, Transistor models, BSIM3 models, Model extraction, Models for : Vt, I-V, Capacitance, Substrate current, S/D parasitics, Temp dependence, NQS effect, Noise, RF Modeling, Gate leakage Concept of negative feedback; Ideal opamp feedback circuits; Introduce idea of nullator/norator ; Real opamp feedback circuits-effect of finite A0, wu Review of Bode plots; Stability of feedback systems; location of nondominant poles for stability; Judging stability from magnitude and phase plots; Review of linear networks. Nonlinear networks and notion of incremental linearity. Small signal linear equivalents of nonlinear one and two port networks. Y-parameter two port amplifier constraints on small signal y parameters to realize gain - MOS Transistor Characteristics Derivation of the common source amplifier with biasing and swing limits. Several variants of biasing : current source in the source, feedback from drain to gate, current mirror, use of an opamp for biasing 4
Course details Derive the other controlled sources VCVS (Common drain), CCCS (Common Gate), CCVS (Transimpedance Amp), VCCS (Transconductor)., multi-stage amplifiers Introduce bipolar transistor as another candidate device, run through all the above with BJTs. Illustrate poweradvantage of Bipolar vs MOS Frequency response of the basic amplifier configurations, Ft of transistor; Common source amplifier response with varying Cgd-show miller multiplication, pole splitting Differential pair, small and large signal analysis; Concept of common mode rejection Effect of Random mismatch in integrated circuits 5
Course details Differential to Single-Ended Conversion: Use of active loads leading to the 5-transistor single-stage opamp; also introduce slewing in more detail --> extend to gain enhancement techniques like cascodes, telescopic cascodes; Two-stage differential amplifiers with various types of compensation (dominant pole, miller, pole-zero)-pole splitting, effect of RHP zero, zero cancellation Two-stage differential amplifiers with various types of compensation (dominant pole, miller, pole-zero) Single-stage differential op-amp with common-mode feedback Passives in Analog Circuits Bandgap references Current mirrors: Cascode, Nagative feedback, Wilson, Regulated cascode, Layout issues 6
Why Analog? Interaction with the Physical World Physical Environment Input Sensing Computing Platform Output Actuation Physical Environment Human perception is inherently analog in nature 7
Why Analog? An Interesting Comparison Transistor / Neuron Wire / Fibre Integration Architecture CMOS Digital Computer 1ps 10 8 m/sec ~1 Billion Digital (RISC/CISC ) Biological Neural System 100mS 2m/sec ~ 1 Trillion Analog (Adaptive learning) Neural networks outperform the digital computers, in certain class of applications such as speech recognition, pattern recognition The architecture and massive parallelism are distinguishing features 8
The First IC : 1958 First IC demonstrated by J.S.Kilby of Texas Instruments in 1958 Phase shift oscillator, an analog circuit! A thin slice of germanium with Blue tinge was created by a light shown on the chip. First IC using planar process and photolithography was demonstrated by Robert Noyce at Fairchild semiconductors 1 bipolar transistor (under the large bar of aluminum in the center), 1 capacitor, 3 resistors (the germanium functioned as its own so-called bulk resistor) 4 input/output terminals (the small vertical aluminum bars) ground pad (the large bar on the far right), and wires of gold. Connected together with wax Actual size: 0.040 x 0.062 inches 9
Metal Oxide Semiconductor Field Effect Transistor (MOSFET) Field effect transistor concept proposed in 1930s by Lilienfeld First MOSFET fabricated in 1960 by Kahng and Atalla PMOSFET metal oxide p+ p+ n Silicon NMOSFET metal oxide n+ n+ p Silicon Early MOS technology was based on PMOSFETs MOSFETS were thought to be unfriendly for Analog circuits! 10
CMOS Technology Today (2007) 65nm digital technology in volume production Number of transistors per chip is ~ 1 billion( DRAMs), ~ 100 million (microprocessors) Technology scaling for future is more challenging and expensive State of the art fab set-up costs more than US$2 billion Recovering the fab cost requires a modular process technology approach capable of producing diverse products What do we do with the technology capable of making millions of transistor on a tiny area in Si? : Mixed Signal Systems On Chip (SOC) 11
BJT versus MOSFET speed p n+ p n- Base width defined by diffusion process p p metal oxide n+ n+ p Silicon Channel length defined by Photolythography process Historically BJT used to be faster than MOSFET CMOS scaling has brought MOSFET on par with BJT 12
Cut-off frequency, f T Cut-off frequency trend ft 120 100 80 60 40 20 0 0 0.2 0.4 0.6 0.8 1 1.2 Channel length ft MOSFET f T has increased considerably with scaling 13
Analog Design on Digital Technology Microprocessors are today s technology drivers The most elegant analog designs make use of the existing digital technology Every modification to the baseline technology adds on to the manufacturing cost Design For Manufacturability (DFM) CMOS analog circuits are logical choice 14
Long channel MOSFET Theory 15
Transistor abstraction D G B S schematic switch model gate n+ n+ A A P-well lay out cross section Si 16
Simple 3-D picture of MOSFET Wg Lg n+ gate x j Tox Oxide n+ source n+ drain The 2 important dimensional parameters of MOSFET under circuit designer s control are: Lg = Length of the gate Wg = Width of the gate p substrate Doping concentration = Na 17
Simple MOS Theory Vgs < Vt, MOSFET is in cut off region Ids = 0 Vgs > Vt, Vds < Vgs-Vt, MOSFET is in linear region Ids = με ox T ox W L 2 ( Vgs Vt) Vds Vds Vgs > Vt, Vds > Vgs-Vt, MOSFET is in saturation region 2 Ids ( Vgs Vt) W = με ox T L 2 ox 2 where μ is mobility, ε ox is permittivity of the oxide, and Vt is the threshold voltage of the MOSFET V t = V fb T + 2 φ + b ox 4ε qn φ ε s ox a b 18
Output Characteristics I-V characteristics Transfer Characteristics Ids Vg3 Vg2 Vg1 Ids Saturation Vds=Vdd Linear Vds~0.1V Vds Vgs Ids is constant and independent of Vds in saturation Ids is zero in sub-threshold region Both of these idealities are incorrect especially for the sub-micron MOS transistor 19
Channel length modulation n+ source Vg > Vt ΔL Vd > Vg - Vt n+ drain Ids R out = ΔV ΔI ds ds electron channel p-substrate Vds=Vgs-Vt Vds Effective channel length is Leff = L - ΔL, where ΔL=f(Vds) I ds oxw = με T L ox eff ( Vgs Vt) 2 2 I ds 2 ( Vgs Vt) ( + λv ) με oxw = 1 T L 2 Ids increases slightly in saturation region with increasing Vds This limits the AC output resistance for analog applications λ is channel length modulation parameter in SPICE ox ds 20
Vs Vbs Body effect Vg Vd n+ n+ p-substrate γ = T V V ox V 2φ t0 = fb + b + t = V ox γ = body effect factor (γ = 0.3-0.7) Vt increases due to body effect This results in a transconductance term T ox 4ε qn ε s ox 21 a φ ( ) V + 2φ φ t0 + bs b 2qε N ε s γ 2 a b b
Sub-micron transistor theory, SCE, NWE, DIBL, Sub-threshold conduction, Digital metrics, Analog metrics The Sub-micron MOS Transistor for Analog Design 22
Constant field scaling Technology scaling Scaling factor K > 1 SCALING IS DRIVEN BY DIGITAL CIRCUIT REQUIREMENTS Primary scaling factors: Tox, L, W, Xj (all linear dimensions) 1/K Na, Nd (doping concentration) K Vdd (supply voltage) 1/K Derived scaling behavior of transistor: Electric field 1 Ids 1/K Capacitance 1/K Derived scaling behavior of circuit: Delay (CV/I) 1/K Power (VI) 1/K 2 Power-delay product 1/K 3 Circuit density (α 1/A) K 2 23
n+ depletion Short Channel Effect (SCE) Vg L n+ depletion p-substrate L (μm) Fraction of the depletion charge (Qd in Vt equation) is supported by the source and drain junctions and hence Vg need not support this When L is very small (~ 1μm) this charge becomes significant fraction of the total depletion charge and can not be neglected => Vt decreases with decreasing L Impacts matching of transistors in analog applications Vt ~1μm 24
Reverse Short Channel Effect Vt dv t dl = ve dv t = + dl ve L Invariably exists in almost all the sub-micron technologies The techniques used to suppress SCE are responsible for RSCE Vt becomes very sensitive function of L 25
Drain Induced Barrier Lowering (DIBL) Vs n+ Vg Vd n+ Vt Vds=0.1V Vds=Vdd Vds=Vdd Potential barrier Vds=0.1V L Vt is also a function of drain voltage in sub-micron transistors DIBL effect is negligible in the long channel regime 26
Narrow Width Effect Vg Vt depletion n+ W ~1μm p-substrate W (μm) Additional depletion charge at the edge of source & drain should be supported by the Vg before inverting the channel When W is very small (~ 1μm) this charge becomes significant fraction of the total depletion charge and can not be neglected => Vt increases with decreasing W 27
Sub threshold conduction Log Ids The inverse slope of this line is S, the sub threshold slope (S~80-100mV/decade) Vt Vgs For Vg < Vt, current is non zero and is exponential function of Vg S = 2.3kT/q (1 + Csi/Cox) mv/decade Csi=depletion capacitance in Si, Cox=oxide capacitance,kt/q=thermal voltage MOSFET should be designed to have minimum possible S Sub threshold analog circuits work below Vt S G D 28
v 10 7 cm/sec at T=300 o K Velocity saturation Ids Ids α (Vgs-Vt) 2 Ids α (Vgs-Vt) ~10 4 V/cm E v=μevalid only at low electric fields (E) For velocity saturated transistor, the saturation drive current is W ( Vgs Vt ) vsat Ids = ε Tox Transconductance will be independent of L For L=0.1μm transistor operating at Vd=1V: E=10 5 V/cm => transistor is velocity saturated Vds Ids will be less than expected due to velocity saturation 29
Transistor design methodology for Digital Technology Circuit characteristics: Delay (Vt/Vdd) Active power (Vdd) Standby power (Vt) Hot carrier reliability Vdd, L, N System compatibility Vdd Gate oxide reliability Vdd, Tox Design parameters: L, Vdd, Tox, N, Xj S/D engineering Channel engineering 30
Vt-Vdd design plane Normalized delay Delay Vt Pac Psb 0.4 Vt/Vdd Delay increases significantly for Vt/Vdd > 0.4 Pactive (Pac) = CV dd2 f Vdd Pstandby (Psb) = WV dd I off Delay and Power are the only trade-off points for digital design 31
Analog Circuit Performance Metrics The Analog Octagon: NOISE LINEARITY POWER GAIN I/O IMPEDANCE SUPPLY VOLTAGE SPEED VOLTAGE SWINGS B. Razavi Multiple trade-offs involved in Analog Design make it very interesting 32
Summary Scaling is driven by digital technology Analog design is indispensable for interaction with physical world Sub-micron transistors present unique challenges for analog design Characterize the behaviour of the MOSFETs in any given technology by doing simple I-V simulations and extracting Vt, Rout etc. as a function of dimensions and bias points The voltage swings in analog circuits will be limited by the reliability constraints While delay and power are the only two metrics for digital design, analog design involves optimization and trade-off between several conflicting metrics 33