Innovation to Advance Moore s Law Requires Core Technology Revolution Klaus Schuegraf, Ph.D. Chief Technology Officer Silicon Systems Group Applied Materials UC Berkeley Seminar March 9 th, 2012
Innovation to Advance Moore s Law Thank you for coming Semiconductor Value Chain - Equipment Moore s Law Challenges Opportunities for Innovation Core Technology Focus 2
APPLIED MATERIALS WAFER FAB DEVICES DRAM VERTICAL TRANSISTOR INTEGRATED CIRCUITS LOGIC FINFET NAND VERTICAL BIT STACK 3
Leadership Strategy - Accelerate Innovation Collaborate earlier and deeper with customers on inflections Deposition Metals Inspection Plating Thermal Planarization Etch Implant Provide the broadest suite of solutions with unmatched integration benefits Extend the technology roadmap with fast cadence in product innovation Drive to atomic precision on interfaces with multi-chamber platforms Enable faster learning with Maydan Technology Center 4
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Moore s Law in Context Cost Performance Moore s Law: Performance, Power Efficiency, Cost From: W. Nordhaus, Yale 6
Logic Technology Scaling Projection Logic Roadmap Scenario 2009 2011 2013 2015 2017 2019 2021 2023 2025 2027 Node and Lg (nm) 32 22 14 10 7 5 3.5 2.5 1.8 1.3 Interconnect CD (nm) 60 40 30 20 15 10 7.5 5 3.5 2.5 Planar CMOS FinFET III-V FinFET Gate Fin New Fin Material STI Oxide STI Oxide Identify challenges and opportunities to enable scaling Focus university research on the big problems 7
Inflections Add Complexity and Opportunity Advanced Transistors Advanced Interconnects Advanced Patterning Wafer-Level Packaging 8
Scaling + Increasing Complexity Innovation Big 3: Logic, DRAM, NAND US-centric innovation Customer consolidation, JV partnerships Logic Foundry/Fabless NOR NAND DRAM 8F 2 6F 2 200mm 300mm Single-wafer processing TODAY Add to Big 3: Image sensor, MRAM, RRAM Global innovation Extreme customer concentration Fabless Vertical fabless system houses 300mm 450mm Logic FinFET NAND 3D NAND DRAM 6F 2 3D 4F 2 New energy sources: (E-beam, Laser, UV, X-ray) Deep-UV laser lithography Memory Double patterning Patterning films Lamp-based processing Reflow HDP DRAM Capacitor Hi-K ALD DPN SiON gate LAST 15 YEARS Epi Single-wafer cleans Copper damascene Low-k dielectric CMP Bumping PVD Metal CVD E-beam inspection Sacrificial films CVD: Hidden films, more steps CMP: New materials, steps, atomic precision Etch: New mtls, high aspect ratio Wafer-level packaging Packaging interposer Optical interconnect NEXT 5 YEARS EUV Double patterning for logic Quad patterning for memory Laser-based processing Flowable films New materials: III-V, Ge Universal ALD (metal, dielectric) 9
Advanced Transistor Challenges Spacer Conventional approach: high AR gate Alternative: Spacer transfer Alternative: Selective deposition Challenge: Spacer-k and Hi-k parasitic Fin Fin Formation Precision etch Structural integrity (collapse, erosion, thermal shock) Recess Channel materials STI Oxide Gate Stack Dummy gate considerations Ternary materials Planarization Removal Hi-k scalability Metal gate considerations Workfunction Resisitivity Fill Self-aligned contact Fin Junctions Conformal doping Stressor alternatives Annealing considerations Silicide Barrier modification New materials 10
Gate Dielectric Scaling Challenge 10 1000 Poly/SiON High-k/Metal 100 T INV (nm) 1 Slowed 10 1 0.1 Gate Leakage (Rel.) 2 nm Applied Internal Data 350 250 180 130 90 65 45 32 22 15 11 7 0.01 Scaling EOT limited by SiO2 IL Technology Node (nm) Thinner EOT requires innovation in interfaces 11
Interfaces Matter Even More Electrically Peak Mobility Improved Mobility 5 to 10% Less Trap Assisted Tunneling Gate Leakage Temperature Acceleration - 30% Applied Internal Data Applied Internal Data Air Exposure After Interface Layer Fully Integrated Gate Stack Air Exposure After Interface Layer Fully Integrated Gate Stack RadiancePlus RadiancePlus DPN3 Nitridation ALD High- Centura cluster enables solution path 12
New il technology improves BTI Reliability NBTI PBTI ChemOx IL 3A new IL ChemOx IL 0.1 5A new IL delta Vt @ 1000 sec 0.1 3A new IL 5A new IL 0.01 0.6 Applied Internal Data Vg - Vt (V) 0.01 0.7 Applied Internal Data Vg - Vt (V) 13
Advanced Interconnect Challenges( 20nm) Patterning Pitch division CD distributions, CDU Overlay Pattern integrity Line bending, collapse LWR/LER Resistance Copper Conformal barriers Liner/barrier Volume Gap-fill Scattering Barrier-Cu interface Grain size Higher aspect ratio Patterning Gap-fill Reliability Electromigration BLOk-Cu interface Barrier-Cu interface TDDB/BTS Patterning(Overlay, LWR/LER) Interface management Barrier and moisture integrity Capacitance Packaging High modulus at lower k Interface adhesion Integrated k BLOk thickness Integration damage Higher k adhesion layers Architecture Air-gap Single Damascene Non-Damascene
Interconnect Improvement: RC-Delay RC Delay (ns/mm) 80 70 60 50 40 30 20 RC Delay Outlook Conventional Disruptive Disruptive 10 0 32nm 22nm 15nm 11nm Technology Node Metal-Insulator Barrier Replacement Low-k Diel. Low-k Dielectric Copper Innovate new technologies to resolve RC-delay challenge 15
3 2 1 0-1 -2-3 New Process Flow for RC Reduction Applied Internal Data Low k SiN BLOk % Probability 0.99 0.95 0.90 0.75 0.50 0.25 0.10 0.05 RC Product No damage Cu-Low k interconnect USG/Cu Interconnect BLOk Cu-Lowk Conventional flow 15% Damage Applied Internal Data Integrated k = Bulk k = No Damage No damage interconnect flow enables pathway to k < 2 16
3 2 1 0-1 -2-3 Selective CVD Metal Caps for EM Enhancement 0.99 300 C, 1.5 MA/cm 2 0.95 % Probability 0.90 0.75 0.50 80x 0.25 0.10 0.05 1 10 100 1000 10000 MTTF (hrs) Applied Internal Data Selective Metal Cap shows >80x EM improvement 17
Innovation to Advance Moore s Law Semiconductor Value Chain - Equipment Moore s Law Challenges Opportunities for Innovation Core Technology Focus 18
Future of Moore s Law G. Dewey, Intel, IEDM 2011 S. Salahuddin, UCB, IEDM 2011 T.-J. King Liu, UCB, IEDM 2009 Alternative Devices F. Yang, TSMC, VLSI 2004 Extend FinFET Gate all-around 2D 3D S. Bangsaruntip, IBM, IEDM 2009 Problem: Physical limits as features approach 3nm Need: Solutions to advance density, power and performance 19
New Device Scorecard Packing density: Unit area per transistor (SRAM equiv.) Performance: Switching delay Power: Switching energy Integration Complexity: Compatibility with Si CMOS Device Integration Compatibility V op * (V) SS (mv/dec) Delay (psec) Energy (fj) Unit Area (nm 2 ) CMOS 32 nm High 0.9 <100 0.2 0.1 28000 CMOS 11 nm (extrapolated) CMOS 5 nm (extrapolated) High 0.63 <70 0.02 0.03 3500 High 0.55 <70 0.01 0.015 900 New Device?????? *V op based on 2011 ITRS Roadmap for LOP Inverter FO = 1, logic depth = 10, activity = 0.1 (Philip Wong, Stanford, IEDM 2010)
Future of Moore s Law: 3D GAA as alternative? Junction Conformal doping V dd Gate Stack Conformal high-k and metal gate Out In Channel New channel materials Gnd Patterning Gates and junctions defined at planar level Local contacts and interconnect between planes Opportunity for new CMOS architectures with many challenges
Focus Areas for Research Core Technology Energy sources Chemical delivery systems & chemistries E-beam Variability management Materials Screening methods Alternative materials: Graphene, Metal Oxide, III-V, optical Devices 100mV switches High packing density logic Alternate channel, Optical interconnect, Interposer EUV Lithography 22