TSV MEOL (Mid-End-Of-Line) and its Assembly/Packaging Technology for 3D/2.5D Solutions

TSV MEOL (Mid-End-Of-Line) and its Assembly/Packaging Technology for 3D/2.5D Solutions Seung Wook YOON, D.J. Na, *K. T. Kang, W. K. Choi, C.B. Yong, *Y.C. Kim and Pandi C. Marimuthu STATS ChipPAC Ltd. 5 Yishun Street 23, Singapore 768442 * STATS ChipPAC Korea Ltd. Ichon, Kyunggi-Do, Korea 467-701 Seungwook.yoon@statschppac.com Abstract Increasing demand for new and more advanced electronic products with a smaller form factor, superior functionality and performance with a lower overall cost has driven semiconductor industry to develop more innovative and emerging advanced packaging technologies. One of the hottest topics in the semiconductor industry today is a 3D packaging using Through Silicon Via (TSV) technology. Driven by the need for improved electrical performance or the reduction of timing delays, methods to use short vertical interconnects have been developed to replace the long interconnects found in 2D packaging. The industry is gearing up to move from technology path finding phase for TSV into commercialization phase, where economic realities will determine the technologies that can be adopted. Choosing the right process equipment and materials, combined with innovative design solutions addressing thermal and electrical issues will be the key success factors. The synergies and intersections among three parallel developing areas of packaging technology i.e. traditional die and package stacking on substrates, fanin and fan-out wafer level packaging and 3D Si integration and the resulting future path for packaging technology is quite critical for future microelectronics packaging. This paper addresses TSV MEOL processes as well as TSV assembly/packaging process. The status of bridge technologies such as interposers and TSV substrates as an interim play prior to full productization of the active Si TSV approach is reviewed with specific examples of configurations approaching volume production in real products. Latest developments in the key elements of 2.5D/3D TSV integration such as TSV backside via revelation, CMP/planarization, wafer thinning, micro bumping. For TSV assembly/packaging, thin die handling, dicing and microbump bonding, underfill characterization will be discussed. TSV Packaging challenges and experimental results will be presented for thermocompression bonding with ultra fine pitch microbump interconnections in this paper. In addition, TSV business model/supply-chain challenges including logical hand off points among silicon fab foundries and OSAT (outsourced semiconductor assembly and test) are presented. TSV technology, which allows stacking of LSIs thereby enabling products to be made smaller with more functionality. 3D technology realizes miniaturization by 300-400% compared to conventional packaging. Introduction One of the hottest topics in the semiconductor industry today is 3D Packaging using Through Silicon Via (TSV) technology. Driven by the need for improved performance and the reduction of timing delays, methods to use short vertical interconnects have been developed to replace the long interconnects found in 2D packaging. The industry is moving past the feasibility (R&D) phase for TSV technology into the commercialization phase, where economic realities will determine the technologies that can be adopted. Low-cost, high aspect ratio, reliable via formation and via filling technologies are the need of the hour. Choosing the right process equipment and materials with innovative design solutions addressing thermal and electrical issues will be the key winner. As functional integration requirements increase, assembly and wafer fabrication companies are looking to 3D Fig.1 Advanced Wafer Level Integration Technology 1

Evolution passives, device partitioning, as well as overall cost view point. There should be cost/performance crossover between Si interposer and advanced substrates in the near future. 2.5D TSV interposer approach is an efficient and practical approach to solving die integration challenges, such as embedded die separation,. Many microsystem device applications that will have to move to wafer-level packaged silicon form factor devices, thereby also facilitating further integration using silicon TSV interposers. Micro-bump II. TSV MEOL TECHNOLOGY TSV MEOL Mid-End of Line process flow that occurs between the wafer fabrication and back-end assembly process. MEOL processes support the advanced manufacturing requirements of 2.5D and 3D TSV as well as wafer level packaging, flip chip and embedded die technology. Flip chip and wafer level packaging are important drivers of mid-end processing in addition to the anticipated growth in 3D solutions utilizing TSV technology, particularly with the integration of memory and logic devices at advanced technology nodes. The initial markets that are expected to embrace 2.5D and 3D TSV technology are mobile applications and high performance processors for the computing/network segment. Figure 2. 3D integration packaging with microbump and TSV, 3D-TSV, 2.5D TSV interposer 3D integration is progressing on three fronts starting with package-level (die, package stacking), wafer level (die-to-wafer bonding, fan out WLP) and more recently at the Si level (TSV) as shown in Fig.1. The demand for high density and multifunctional microelectronics leads to the development of 3D and wafer level packaging, which provides an optimal solution for the shortened interconnects, increased performance and functionality, miniaturization in size and weight, integration of heterogeneous technologies and complex multi-chip systems as well as reduced power consumption. Such packaging technology normally requires the use of ultrathin devices (less than 100µm in thickness). The key benefits from thinned wafers include improved heat dissipation and reduced electrical resistance which offers better flexibility for 3D stacking. However, it brings up a challenge for assembly and packaging; thinning and handling ultrathin semiconductor devices in both front-end and back-end processes due to its fragility and tendency to warp. and practical approach to die-level integration using the capabilities of TSV technology. TSV interposers provide flexibility for the integration of die from different semiconductor technology nodes and deliver advantages in miniaturization, thermal performance and fine line-width/line-spacing in a semiconductor package[1]. 2.5D interposers are one of candidates that would be useful for ELK devices and high performance applications (i.e., Graphic, GPU/MPU, network device, FPGA). TSV interposers also have good candidate to replace advanced substrates due to advantages in thermal performance, precise dimension control, fine line-width/line-spacing, embedded Figure 3. TSV-MEOL/BEOL process in overall TSV process flow. Temporary bonding/debonding: Thin wafer handling There are many ways to overcome current issues to get better process compatibility and repeatability of handling TSV thin wafers for packaging process. Because the TSV wafer is thinned down to 40~50um thickness, handling of this wafer for packaging process is another challenge in order to meet the different and varying needs, such as temperature and chemical 2

stability, temporary adhesion strength et al. For example, polymer bonding/debonding process is based on high temperature, so it may not suitable for solder bumped wafer. And 12 wafer applications have more challenges than 8 applications and need to optimize the process and materials for larger area bonding/debonding. and electroplating processes, which is compatible with conventional IC fabrication. The fabrication process of wafer level process starts with bare Si wafer using Ultra Violet (UV)- light lithography of spin on dielectric material. Secondly, Redistribution line (RDL) layer plating to re-route the Al/Cu bond pads to microbump locations. Thirdly, passivation of RDL layer using spin on dielectric coating and UV lithography to open the RDL metal pads at the bump pads. Fourthly, deposition of Ti/Cu seed layer and patterning of thick photoresist film using lithography to copper pillar plating and then solder plating. SEM micrographs of microbump are shown in Fig.5 for 40 um height microbumps for 40 and 50 um bump pitch. Backside Via Reveal (BVR) Process As shown in Fig.4, TSV is to be reveal to backside for 3D vertical interconnection after front-end TSV formation. With temporary bonding/debonding system, TSV wafer from fab is to be back grinded and Si etched to expose Cu via with fab process. Fig.4 shows the successfully exposed Cu via on backside with 12 TSV wafer. There was TOF SIMS (Time-of-Flight Secondary Ion Mass Spectroscopy) analysis for Cu contamination on Si wafer during CMP process and verified non-detectable Cu content after chemical composition analysis along whole 12 TSV wafer. Figure 5. Micrographs of Cu pillar micro bump of 40um height with 20um diameter. Thin TSV Wafer Thickness and Warpage Thin Wafer thickness and warpage control are also a challenge in the TSV MEOL process and further reliability in process or after packaging. This serious warpage causes higher stress in TSV structures thus catastrophic failure will happen at the further process or package/assembly processes. Selection of temporary bonding materials and its thermal, mechanical stability is critical for warpage behavior during BVR process. Therefore, it should be studied more and characterized with further experiments. Fig.6 shows thickness variation in Si and Cairrer in temporary carrier bonding process. Figure 4. SEM micrographs of backside TSV via reveal process and cross-section view of TSV after BVR in 12 3D TSV wafer. Microbump Cu pillar Process Micro bumping technology where bump pitches are less than 50 micrometers using solder is explored extensively in industry for realization of miniaturized 3D IC integration. Cu pillar with solder cap microbumps have been studied with the objective to develop reliable fine pitch solder micro joints at low cost. Microbump fabrication is based on photolithography Figure 6. Warpage monitoring of carrier and si 3

thickness for TSV BVR process chip die fabrication with bump, the die attachment was carried out with thermo-compression flip chip bonders. Several DOE (design of experimental)s were carried out to find optimized process conditions as functions of time, stage temperature, pickup tool temperature as well as pressure. Fig. 9 shows x-ray image after thermo-compression successful flipchip bonding without void. 40μm and 50μm both microbump test vehicles were sent to JEDEC standard reliability tests. Reliability samples passed MSL-3 with 3x reflow process at Pb-free 260oC peak temperature. All samples passed unbiased HAST and HTS reliability tests. There was no failure found after 1000 T/C. III. 3D TSV ASSEMBLY AND PACKAGING Compared to conventional flipchip process, TSV assembly process is more complex due to TSV wafer as well as microbump. As shown in Fig. 7, there are additional materials, like as additional encapsulation in between bump and flipchip die or bump and TSV die. There are quite critical challenges for assembly view point both in materials and assembly process. Figure 7. Challenges of TSV Assembly/Packaging. (c) Figure 8. Process flow of 3D TSV assembly and packaging. Figure 9. SEM micrographs of 40/ 50 um pitch of chip-to-chip, chip-to-substrate, (c) X-ray micrograph of Cu column bump interconnects of 40/50um bump pitch. In advanced 3D stacking technologies, one of the important steps is to develop and assembly fine pitch and high density solder microbumps. Solder microbumps for flip-chip interconnections allow high wiring density in the Si-carrier, as compared to organic or ceramic substrates, and enable high-performance signal and power connections [2]. Flip chip package assembly was carried out to investigate the bonding quality and interconnections with microbump flip chip as shown in Fig. 8. After flip IV. 3D WAFER LEVEL INTEGRATION WITH WLP (ewlb), TSV AND IPD TECHNOLOGY TSV is typically not a packaging solution by itself. TSV uses only back-end manufacturing techniques 4

such as bonding, fine pitch bumping, back grinding and thin wafer handling. Final packaging is required to connect the device to the PWB. Due to assembly constraints, the choice of the final package solution could affect the entire TSV process flow. This final packaging could be a BGA package, a fan-out WLP type, an embedded die in substrate (EDS), or other. Here, it is interesting to notice how complementary 3D IC configurations with TSV and 3D packaging can be. In effect, 3D ewlb(embedded Wafer Level BGA) can enable designs to fully benefit from the 3D IC integration and can reduce the package footprint with more aggressive design rules than BGA packages. A truly seamless wafer level integrated 3D packaging module that will incorporate aspects of 3D stacking, as well as Si package with IPD, actives in 3D ewlb packaging with TSV, flip chip, and microbump as well as 3D WLPs.[3] Passive devices such as resistors, de-coupling capacitors, filters and resonators are key building blocks of RF circuitry but are also relatively large devices, consuming 70% or more of available board space in some cases. There is powerful argument for combining IPD with TSV Integrating (stacking) the passive components reduces overall package footprint and so saves space. Use of 3D TSV reduces the interconnect length between the passive and active components, thereby reducing parasitic impedance effects and so improving system performance. Whilst the advantages of TSV+IPD integration are clear, systems manufactured using this approach must also be reliable, and, to date, little has been published on the reliability of such systems. Integration of IPD and TSV into a thinned silicon interposer has been successfully demonstrated[4]. By combining ewlb (embedded wafer level BGA) technology with our Through Silicon Via (TSV) and Integrated Passive Device (IPD) technology we are achieving new levels of heterogeneous integration in a wide range of design configurations including small die, large die, multi-die, multi-layer and stacked packages. Although active and stacked ICs are a highly functional and important component of the overall system, they are only one set of components; many other components including other actives, passives, power systems, wiring, and connectors must be considered in a complete system. As a result, there is a need to think at module and system levels and this need is largely met by the current technology domain in the areas of through silicon vias (TSVs), 3D stacking, and wafer level packaging. There should be further study on integration, focusing on TSVs, 3D stacking and 3D ewlb with better electrical and thermal performance, greater system reliability, and reduced form factor and overall cost. It will go far beyond this to realize a truly seamless wafer level integrated 3D packaging module that will incorporate aspects of 3D stacking, as well as Si package with embedded passive, actives in 3D ewlb packaging with TSV, flip chip, and microbump as well as 3-D WLPs. VI. CONCLUSION In this paper, recent development of TSV MEOL process for 3D integration and 2.5D TSV interposer technology, and TSV packaging/assembly were discussed. For successful implementation of TSV technology to microsystem products, TSV MEOL process and TSV packaging/assembly both should be well developed without major reliability and manufacturing concerns, and established with close collaboration and clear understanding from integration process perspective. TSV technology enables the integration of semiconductor die fabricated in different technology nodes with diverse testing requirements. The short vertical TSV interconnections through the silicon wafer achieve greater space efficiencies for a smaller form factor and higher electrical performance. Integrating TSV and IPD technology delivers clear advantages such as advanced heterogeneous system integration, higher electrical performance and reduced form factor packaging. The ability to integrate TSV and IPD technology opens up a wide range of possible design configurations for SiP and 3D packaging at the silicon level. This is an effective approach to system partitioning which offers an overall outstanding system performance. REFERENCE [1]. Knickerbocker, J. U. et al, Development of next generation system-on-package (SOP) technology based on silicon carriers with fine-pitch interconnection, IBM J. Res. Dev. Vol. 49, No. 4/5 (2005), pp. 725-754 (2005) [2]. Newsletter on 3D Packaging, 3D IC, TSV, WLP & Embedded Technologies, MARCH 2009, No.10, Yole Development (2009) [3]. Seung Wook YOON, Meenakshi PADMANATHAN, Andreas BAHR, Xavier BARATON and Flynn CARSON 3D ewlb (embedded wafer level BGA) Technology: Next Generation 3D Packaging solutions, San Francisco, IWLPC 2009 (2009) [4]. Dzafir Shariff et al., Integration of Fine-Pitched Through-Silicon Vias and Integrated Passive Devices, Proceedings of ECTC 2011, Orlando, US (2011) 5