Transient Load Tester for Time Domain PDN Analysis Ethan Koether (Oracle) Istvan Novak (Oracle)
Speakers Ethan Koether Hardware Engineer, Oracle ethan.koether@oracle.com He is currently focusing on system power-distribution network design, measurement, and analysis. He received his master's degree in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology. Istvan Novak Senior Principal Engineer, Oracle istvan.novak@oracle.com Besides signal integrity design of high-speed serial and parallel buses, he is engaged in the design and characterization of powerdistribution networks and packages for mid-range servers. He creates simulation models, and develops measurement techniques for power distribution. Istvan has twenty plus years of experience with high-speed digital, RF, and analog circuit and system design. He is a Fellow of IEEE for his contributions to signal-integrity and RF measurement and simulation methodologies. Image Image 2
Outline Motivation for Time Domain PDN Validation Transient Load Tester Circuit Design The GaN FET Transient Load Tester Implementation and Performance Conclusion 3
Outline Motivation for Time Domain PDN Validation Transient Load Tester Circuit Design The GaN FET Transient Load Tester Implementation and Performance Conclusion 4
Target Impedance Methodology Estimates upper bound for rail s impedance Voltage fluctuation on rail: V Maximum current step: I Target Impedance: Z Target = V/ I Valid for linear and time-invariant PDN Approximation unless impedance strictly resistive 1.E+00 Impedance magnitude [ohm] 1.E-01 1.E-02 Frequency [Hz] 1.E-03 1.E+02 1.E+04 1.E+06 1.E+08 5
Time Domain PDN Validation Load device under test (DUT) with current who s waveform follows input voltage waveform. Input Voltage Waveform Load Current t 0 t 0 For PDN design, can load DUT with worst case current in worst case time to analyze simulated behavior in live system. 6
Outline Motivation for Time Domain PDN Validation Transient Load Tester Circuit Design The GaN FET Transient Load Tester Implementation and Performance Conclusion 7
Transient Load Tester (TLT) Circuit Design GaN FET I Load Only works in one I-V quadrant 8
Outline Motivation for Time Domain PDN Validation Transient Load Tester Circuit Design The GaN FET Transient Load Tester Implementation and Performance Conclusion 9
The Gallium Nitride FET (GaN FET) Maximum Ratings V DS Drain-to-Source Voltage (up to 10,000 5ms pulses at 150 C) 48 Drain-to-Source Voltage (Continuous) 40 I D Continuous (T A = 25 C, R θja = 6 C/W) 53 A Pulsed (25 C, T PULSE = 300 µs) 235 Gate-to-Source Voltage 6 V GS Gate-to-Source Voltage -4 V T J Operating Temperature -40 to 150 T STG Storage Temperature -40 to 150 V C 10
The Gallium Nitride FET (GaN FET) The enhancement mode GaN FET used compared to silicon MOSFETs with similar electrical characteristics: Faster switching speeds and shorter delay time C GD is exceptionally small in value C GS is relatively small in value Lower threshold voltage Lower package inductance Lower R DS ON 11
Outline Motivation for Time Domain PDN Validation Transient Load Tester Circuit Design The GaN FET Transient Load Tester Implementation and Performance Conclusion 12
TLT Circuit Breadboard Implementation High Speed Op Amp DUT Sense Resistors 13
TLT Circuit Breadboard Implementation GaN FET Buffer Circuit 14
TLT Implementation and Test Results TLT voltages measured at inverting and non-inverting inputs of op amp For figure below: DUT voltage of 1V, rise/fall times of 100ns 15
TLT Implementation and Test Results TLT voltages measured at inverting and non-inverting inputs of op amp For figure below: DUT voltage of 1V, rise/fall times of 100ns 16
Current Step (A) Current Step (A) TLT Implementation and Test Results Limitation of max operating current of individual circuit can be overcome by operating circuits in parallel The measurements below were captured from boards operating alone with 100ns rise/fall time on a DUT supplying 1V TLT board #1 TLT board #2 50 45 40 35 30 25 20 15 10 5 0-0.5 0 0.5 1 1.5 2 2.5 Time (μs) 50 45 40 35 30 25 20 15 10 5 0-0.5 0 0.5 1 1.5 2 2.5 Time (μs) 17
Current Step (A) TLT Implementation and Test Results The measurements below were captured from TLT boards #1 and #2 operating in parallel with 100ns rise/fall time on a DUT supplying 1V 50 45 40 35 30 25 20 15 10 5 0-0.5 0 0.5 1 1.5 2 2.5 Time (µs) Parallel operation does not affect operational behavior of TLT circuit 18
TLT Full PCB Implementation Side and top views of 16 TLT circuits implemented in CPU BGA plug-in PCB for parallel operation Control Circuitry Loading GaN FETs 19
TLT Usage for DC-DC Converter and its PDN s Time Domain Performance Testing Verify PDN can supply necessary current to devices DUT can be tested with complex waveforms using arbitrary waveform generator TLT validation uses current pulse train with magnitude equal to max current step PDN must support Can vary frequency and duty cycle to explore exacerbations from resonances 20
MAX VOLTAGE FLUCTUATION (V) DUTY CYCLE (%) TLT Usage for DC-DC Converter and its PDN s Time Domain Performance Testing Verify PDN can supply necessary current to devices DUT can be tested with complex waveforms using arbitrary waveform generator TLT validation uses current pulse train with magnitude equal to max current step PDN must support Can vary frequency and duty cycle to explore exacerbations from resonances 0.011 0.01 0.009 0.008 0.007 1E+3 2E+3 3E+3 4E+3 5E+3 6E+3 7E+3 8E+3 9E+3 1E+4 18 26 10 FREQUENCY (HZ) 21
Outline Motivation for Time Domain PDN Validation Transient Load Tester Circuit Design The GaN FET Transient Load Tester Implementation and Performance Conclusion 22
Conclusion Time domain validation of PDNs important for thorough PDN design and analysis The GaN FET offers faster turn on speeds and relatively low threshold voltage compared to silicon MOSFETs with similar electrical characteristics Implementation of GaN FET with TLT circuit topology along with parallel operation of TLT circuits delivers fast slew of current at 100ns rise/fall time with virtually unlimited current magnitude TLT allows for simulation of worst case loading conditions on a PDN in system within a lab setting for thorough PDN validation. 23
Acknowledgements The authors wish to thank for their help Kavitha Narayandass, Alex Miranda, Guy Phillips, Dan Sullivan, Dave Michaud, Bill Tata, Khan Nguyen, Dan Rich, Randy Luckenbihl, Jerome Gentillet, Sandra Brescia, Raja Burney, Gustavo Blando, Laura Kocubinski, all of Oracle Corporation. 24
More Information ethan.koether@oracle.com istvan.novak@oracle.com 25
Thank You! --- QUESTSIONS? 26
Current (A) Voltage (V) TLT Implementation and Test Results Inherent fight between V GS and V DS, convergence of which determines operational behavior of TLT Figures below captured with DUT supplying 1V, show V DS, V GS, and resulting load current at steps of 20A and 40A with 100ns rise and fall times 45 40 35 30 4 3.5 3 2.5 25 2 20 1.5 15 1 10 0.5 5 0-1 0 1 2 3 Time (µs) 0-1 0 1 2 3 Time (µs) VGS(ID=20A) VDS(ID=20A) VGS(ID=20A) VGS(ID=40A) VGS(ID=40A) VDS(ID=40A) 27
Current Load Step (A) TLT Implementation and Test Results PCB implementation of TLT circuits operating in parallel demands loading FETs be in close proximity to one another Little thermal dependence of TLT operational behavior Data below captured with TLT operating at 100ns rise/fall time connected to DUT supplying 1V 25 20 15 10 5 0 0 0.1 0.2 0.3 0.4 0.5 Time (µs) 5 Degree C 10 Degree C 15 Degree C 20 Degree C 25 Degree C 30 Degree C 35 Degree C 40 Degree C 45 Degree C 28