TPS7675Q, TPS7678Q, TPS76725Q, TPS76727Q A Low-Dropout Voltage Regulator Available in.5-v,.8-v, 2.5-V, 2.7-V, 2.8-V, 3.-V, 3.3-V, 5.-V Fixed Output and Adjustable Versions Dropout Voltage Down to 23 mv at A (TPS7675) Ultralow 85 µa Typical Quiescent Current Fast Transient Response 2% Tolerance Over Specified Conditions for Fixed-Output Versions Open Drain Power-On Reset With 2-ms Delay (See TPS768xx for PG Option) 8-Pin SOIC and 2-Pin TSSOP PowerPAD (PWP) Package Thermal Shutdown Protection GND/HSK GND/HSK GND NC EN NC GND/HSK GND/HSK PWP PACKAGE (TOP VIEW) 2 3 4 5 6 7 8 9 2 9 8 7 6 5 4 3 2 NC No internal connection D PACKAGE (TOP VIEW) GND/HSK GND/HSK NC NC RESET FB/NC GND/HSK GND/HSK description V DO Dropout Voltage mv This device is designed to have a fast transient response and be stable with -µf low ESR capacitors. This combination provides high performance at a reasonable cost. 3 2 DROP VOLTAGE FREE-AIR TEMPERATURE IO = A IO = ma IO = Co = µf 2 6 4 2 2 4 6 8 2 4 TA Free-Air Temperature C VO Change in Output Voltage mv I O Output Current A 5 5.5 GND EN LOAD TRANSIENT RESPONSE Co = µf 2 3 4 8 7 6 5 RESET FB/NC 2 3 4 5 6 7 8 9 t Time µs Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 22, Texas Instruments Incorporated POST OFFICE BOX 65533 DALLAS, TEXAS 75265
description (continued) Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 23 mv at an output current of A for the TPS7675) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically 85 µa over the full range of output current, ma to A). These two key specifications yield a significant improvement in operating life for battery-powered systems. This LDO family also features a sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent current to µa at T J = 25 C. The RESET output of the TPS767xx initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS767xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage. The TPS767xx is offered in.5-v,.8-v, 2.5-V, 2.7-V, 2.8-V, 3.-V, 3.3-V, and 5.-V fixed-voltage versions and in an adjustable version (programmable over the range of.5 V to 5.5 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges. The TPS767xx family is available in 8-pin SOIC and 2-pin PWP packages. AVAILABLE OPTIONS TJ PUT VOLTAGE (V) TYP PACKAGED DEVICES TSSOP (PWP) SOIC (D) 5. TPS7675Q TPS7675Q 3.3 Q Q 3. TPS7673Q TPS7673Q 2.8 TPS76728Q TPS76728Q 4 C C to25 C 2.7 TPS76727Q TPS76727Q 2.5 TPS76725Q TPS76725Q.8 TPS7678Q TPS7678Q.5 TPS7675Q TPS7675Q Adjustable.5 V to 5.5 V TPS767Q TPS767Q The TPS767 is programmable using an external resistor divider (see application information). The D and PWP packages are available taped and reeled. Add an R suffix to the device type (e.g., TPS767QDR). VI. µf 6 7 5 EN TPS767xx GND 3 RESET 6 4 3 RESET VO Co + µf See application information section for capacitor selection details. Figure. Typical Application Configuration (For Fixed Output Options) 2 POST OFFICE BOX 65533 DALLAS, TEXAS 75265
functional block diagram adjustable version EN _ + RESET Vref =.834 V + _ 2 ms Delay FB/NC R R2 GND External to the device functional block diagram fixed-voltage version EN _ + RESET Vref =.834 V + _ 2 ms Delay R R2 GND POST OFFICE BOX 65533 DALLAS, TEXAS 75265 3
SOIC Package TERMAL NAME NO. I/O EN 2 I Enable input Terminal Functions DESCRIPTION FB/NC 7 I Feedback input voltage for adjustable device (no connect for fixed options) GND Regulator ground 3, 4 I Input voltage 5, 6 O Regulated output voltage RESET 8 O RESET output PWP Package NAME TERMAL NO. I/O EN 5 I Enable input DESCRIPTION FB/NC 5 I Feedback input voltage for adjustable device (no connect for fixed options) GND 3 Regulator ground GND/HSK, 2, 9,,, Ground/heatsink 2, 9, 2 6, 7 I Input voltage NC 4, 8, 7, 8 No connect 3, 4 O Regulated output voltage RESET 6 O RESET output 4 POST OFFICE BOX 65533 DALLAS, TEXAS 75265
timing diagram VI Vres Vres t VO VIT + VIT + Threshold Voltage Less than 5% of the VIT output voltage VIT t Output Undefined RESET Output ÎÎ ÎÎ ÎÎ ÎÎ 2 ms Delay 2 ms Delay ÎÎ ÎÎ ÎÎ ÎÎt Output Undefined Vres is the minimum input voltage for a valid RESET. The symbol Vres is not currently listed within EIA or JEDEC standards for semiconductor symbology. VIT Trip voltage is typically 5% lower than the output voltage (95%VO) VIT to VIT+ is the hysteresis voltage. POST OFFICE BOX 65533 DALLAS, TEXAS 75265 5
absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Input voltage range, V I...........................................................3 V to 3.5 V Voltage range at EN............................................................3 V to V I +.3 V Maximum RESET voltage................................................................. 6.5 V Peak output current.............................................................. Internally limited Output voltage, V O (, FB)................................................................ 7 V Continuous total power dissipation...................................... See dissipation rating tables Operating virtual junction temperature range, T J..................................... 4 C to 25 C Storage temperature range, T stg................................................... 65 C to 5 C ESD rating, HBM.......................................................................... 2 kv Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network terminal ground. PACKAGE D AIR FLOW (CFM) DISSIPATION RATG TABLE FREE-AIR TEMPERATURES TA < 25 C POWER RATG DERATG FACTOR ABOVE TA = 7 C POWER RATG TA = 85 C POWER RATG 568 mw 5.68 mw/ C 32 mw 227 mw 25 94 mw 9.4 mw/ C 497 mw 36 mw PACKAGE PWP AIR FLOW (CFM) DISSIPATION RATG TABLE 2 FREE-AIR TEMPERATURES TA < 25 C POWER RATG DERATG FACTOR ABOVE TA = 7 C POWER RATG TA = 85 C POWER RATG 2.9 W 23.5 mw/ C.9 W.5 W 3 4.3 W 34.6 mw/ C 2.8 W 2.2 W 3 W 23.8 mw/ C.9 W.5 W PWP 3 7.2 W 57.9 mw/ C 4.6 W 3.8 W This parameter is measured with the recommended copper heat sink pattern on a -layer PCB, 5-in 5-in PCB, oz. copper, 2-in 2-in coverage (4 in2). This parameter is measured with the recommended copper heat sink pattern on a 8-layer PCB,.5-in 2-in PCB, oz. copper with layers, 2, 4, 5, 7, and 8 at 5% coverage (.9 in2) and layers 3 and 6 at % coverage (6 in2). For more information, refer to TI technical brief SLMA2. recommended operating conditions M MAX UNIT Input voltage, VI# 2.7 V Output voltage range, VO.5 5.5 V Output current, IO (see Note ). A Operating virtual junction temperature, TJ (see Note ) 4 25 C # To calculate the minimum input voltage for your maximum output current, use the following equation: VI(min) = VO(max) + VDO(max load). NOTE : Continuous current and operating junction temperature are limited by internal protection circuitry, but it is not recommended that the device operate under conditions beyond those specified in this table for extended periods of time. 6 POST OFFICE BOX 65533 DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range, V I = V O(typ) + V, I O = ma, EN = V, C o = µf (unless otherwise noted) Output voltage ( µa to A load) (see Note 2) PARAMETER TEST CONDITIONS M TYP MAX UNIT TPS767 TPS7675 TPS7678 TPS76725 TPS76727 TPS76728 TPS7673 TPS7675.5 V VO 5.5 V, TJ = 25 C VO.5 V VO 5.5 V, TJ = 4 C to 25 C.98VO.2VO TJ = 25 C, 2.7 V < V < V.5 TJ = 4 C to 25 C, 2.7 V < V < V.47.53 TJ = 25 C, 2.8 V < V < V.8 TJ = 4 C to 25 C, 2.8 V < V < V.764.836 TJ = 25 C, 3.5 V < V < V 2.5 TJ = 4 C to 25 C, 3.5 V < V < V 2.45 2.55 TJ = 25 C, 3.7 V < V < V 2.7 TJ = 4 C to 25 C, 3.7 V < V < V 2.646 2.754 TJ = 25 C, 3.8 V < V < V 2.8 TJ = 4 C to 25 C, 3.8 V < V < V 2.744 2.856 TJ = 25 C, 4. V < V < V 3. TJ = 4 C to 25 C, 4. V < V < V 2.94 3.6 TJ = 25 C, 4.3 V < V < V 3.3 TJ = 4 C to 25 C, 4.3 V < V < V 3.234 3.366 TJ = 25 C, 6. V < V < V 5. TJ = 4 C to 25 C, 6. V < V < V 4.9 5. Quiescent current (GND current) µa < IO < A, TJ = 25 C 85 EN = V, (see Note 2) IO = A, TJ = 4 C to 25 C 25 Output voltage line regulation ( VO/VO) (see Notes 2 and 3) VO + V < VI V, TJ = 25 C. %/V Load regulation 3 mv Output noise voltage (TPS7678) BW = 2 Hz to khz, IC = A, Co = µf, TJ = 25 C V µa 55 µvrms Output current limit VO = V.7 2 A Thermal shutdown junction temperature 5 C Standby current EN = VI, TJ = 25 C, 2.7 V < VI < V EN = VI, TJ = 4 C to 25 C 2.7 V < VI < V µa µa FB input current TPS767 FB =.5 V 2 na High level enable input voltage.7 V Low level enable input voltage.9 V Power supply ripple rejection (see Note 2) f = KHz, TJ = 25 C Co = µf, NOTES: 2. Minimum operating voltage is 2.7 V or VO(typ) + V, whichever is greater. Maximum voltage V. 3. If VO.8 V then VImax = V, VImin = 2.7 V: Line Reg. (mv).% V. If VO 2.5 V then VImax = V, VImin = VO + V: Line Reg. (mv).% V. V O. VImax 2.7 V. V O.V Imax.V O V.. 6 db POST OFFICE BOX 65533 DALLAS, TEXAS 75265 7
electrical characteristics over recommended operating free-air temperature range, V I = V O(typ) + V, I O = ma, EN = V, C o = µf (unless otherwise noted) (continued) Reset PARAMETER TEST CONDITIONS M TYP MAX UNIT Minimum input voltage for valid RESET IO(RESET) = 3 µa. V Trip threshold voltage VO decreasing 92 98 %VO Hysteresis voltage Measured at VO.5 %VO Output low voltage VI = 2.7 V, IO(RESET) = ma.5.4 V Leakage current V(RESET) = 5 V µa RESET time-out delay 2 ms Input current (EN) Dropout voltage (see Note 4) NOTE 4: TPS76728 TPS7673 TPS7675 EN = V EN = VI IO = A, TJ = 25 C 5 IO = A, TJ = 4 C to 25 C 825 IO = A, TJ = 25 C 45 IO = A, TJ = 4 C to 25 C 675 IO = A, TJ = 25 C 35 IO = A, TJ = 4 C to 25 C 575 IO = A, TJ = 25 C 23 IO = A, TJ = 4 C to 25 C 38 voltage equals VO(typ) mv; TPS767 output voltage set to 3.3 V nominal with external resistor divider. TPS7675, TPS7678, TPS76725, and TPS76727 dropout voltage limited by input voltage range limitations (i.e., TPS7673 input voltage needs to drop to 2.9 V for purpose of this test). µa mv TYPICAL CHARACTERISTICS Table of Graphs FIGURE VO Output voltage Output current 2, 3, 4 Free-air temperature 5, 6, 7 Ground current Free-air temperature 8, 9 Power supply ripple rejection Frequency Output spectral noise density Frequency Input voltage (min) Output voltage 2 Zo Output impedance Frequency 3 VDO Dropout voltage Free-air temperature 4 Line transient response 5, 7 Load transient response 6, 8 VO Output voltage Time 9 Dropout voltage Input voltage 2 Equivalent series resistance (ESR) Output current 22 25 8 POST OFFICE BOX 65533 DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS 3.2835 3.283 PUT VOLTAGE PUT CURRENT VI = 4.3 V.4985.498 TPS7675 PUT VOLTAGE PUT CURRENT VI = 2.7 V V O Output Voltage V 3.2825 3.282 3.285 3.28 V O Output Voltage V.4975.497.4965.496 3.285.4955 3.28..2.3.4.5.6.7.8.9 IO Output Current A Figure 2.495..2.3.4.5.6.7.8.9 IO Output Current A Figure 3 TPS76725 PUT VOLTAGE PUT CURRENT PUT VOLTAGE FREE-AIR TEMPERATURE 2.496 2.4955 VI = 3.5 V 3.32 3.3 VI = 4.3 V V O Output Voltage V 2.495 2.4945 2.494 2.4935 2.493 V O Output Voltage V 3.3 3.29 3.28 3.27 IO = A IO = ma 2.4925 3.26 2.492..2.3.4.5.6 IO Output Current A Figure 4.7.8.9 3.25 6 4 2 2 4 6 8 2 4 TA Free-Air Temperature C Figure 5 POST OFFICE BOX 65533 DALLAS, TEXAS 75265 9
TYPICAL CHARACTERISTICS TPS7675 PUT VOLTAGE FREE-AIR TEMPERATURE TPS76725 PUT VOLTAGE FREE-AIR TEMPERATURE.55 2.55 VI = 2.7 V VI = 3.5 V.5 2.5 V O Output Voltage V.55.5.495 IO = A IO = ma V O Output Voltage V 2.55 2.5 2.495 2.49 IO = A IO = ma.49 2.485.485 6 4 2 2 4 6 8 2 TA Free-Air Temperature C Figure 6 4 2.48 6 4 2 2 4 6 8 2 TA Free-Air Temperature C Figure 7 92 9 88 GROUND CURRENT FREE-AIR TEMPERATURE VI = 4.3 V Ground Current µ A 86 84 82 8 78 76 IO = A IO = 5 ma IO = ma 74 72 6 4 2 2 4 6 8 2 4 TA Free-Air Temperature C Figure 8 POST OFFICE BOX 65533 DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS Ground Current µ A 95 9 85 8 TPS7675 GROUND CURRENT FREE-AIR TEMPERATURE VI = 2.7 V IO = ma IO = A IO = 5 ma PSRR Power Supply Ripple Rejection db 9 8 7 6 5 4 3 2 POWER SUPPLY RIPPLE REJECTION FREQUENCY VI = 4.3 V Co = µf IO = A 75 6 4 2 2 4 6 8 2 4 TA Free-Air Temperature C Figure 9 k k k M f Frequency Hz Figure Output Spectral Noise Density µv Hz 5 6 7 PUT SPECTRAL NOISE DENSITY FREQUENCY IO = A IO = 7 ma VI = 4.3 V Co = µf 8 2 3 4 5 f Frequency Hz Figure POST OFFICE BOX 65533 DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS 4 IO = A PUT VOLTAGE (M) PUT VOLTAGE Input Voltage (Min) V 3 2.7 TA = 25 C TA = 4 C V I 2.5.75 2 2.25 2.5 2.75 VO Output Voltage V Figure 2 3 3.25 3.5 VI = 4.3 V Co = µf PUT IMPEDANCE FREQUENCY 3 2 DROP VOLTAGE FREE-AIR TEMPERATURE IO = A Zo Output Impedance Ω IO = ma IO = A V DO Dropout Voltage mv IO = ma 2 2 3 4 5 6 f Frequency khz Figure 3 IO = Co = µf 2 6 4 2 2 4 6 8 2 4 TA Free-Air Temperature C Figure 4 2 POST OFFICE BOX 65533 DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS Input Voltage V V I 3.7 2.7 TPS7675 LE TRANSIENT RESPONSE V O Change in Output Voltage mv 5 5 TPS7675 LOAD TRANSIENT RESPONSE Co = µf VO Change in Output Voltage mv Co = µf I O Output Current A.5 2 4 6 8 2 4 6 8 2 t Time µs Figure 5 2 3 4 5 6 7 8 9 t Time µs Figure 6 LE TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE VO Change in V I Input Voltage V Output Voltage mv 5.3 4.3 Co = µf VO Change in Output Voltage mv I O Output Current A 5 5.5 Co = µf 2 4 6 8 2 4 6 8 2 t Time µs Figure 7 2 3 4 5 6 7 8 9 t Time µs Figure 8 POST OFFICE BOX 65533 DALLAS, TEXAS 75265 3
TYPICAL CHARACTERISTICS V O Output Voltage V Enable Pulse V 4 3 2 Co = µf IO = A PUT VOLTAGE TIME (AT STARTUP)..2.3.4.5.6.7.8.9 t Time ms Figure 9 Dropout Voltage mv V DO 9 8 7 6 5 4 3 2 2.5 TPS767 DROP VOLTAGE PUT VOLTAGE TA = 4 C 3 3.5 4 VI Input Voltage V Figure 2 IO = A TA = 25 C 4.5 5 VI To Load EN GND + Co ESR RL Figure 2. Test Circuit for Typical Regions of Stability (Figures 22 through 25) (Fixed Output Options) 4 POST OFFICE BOX 65533 DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE PUT CURRENT TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE PUT CURRENT ESR Equivalent Series Resistance Ω VO = 3.3 V Co = 4.7 µf VI = 4.3 V Region of Instability Region of Stability. 2 4 6 8 ESR Equivalent Series Resistance Ω Region of Instability Region of Stability IO Output Current ma Figure 22. 2 4 6 8 VO = 3.3 V Co = 4.7 µf VI = 4.3 V TJ = 25 C IO Output Current ma Figure 23 TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE PUT CURRENT TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE PUT CURRENT ESR Equivalent Series Resistance Ω VO = 3.3 V Co = 22 µf VI = 4.3 V Region of Instability Region of Stability. 2 4 6 8 ESR Equivalent Series Resistance Ω Region of Instability Region of Stability IO Output Current ma Figure 24. 2 4 6 8 VO = 3.3 V Co = 22 µf VI = 4.3 V TJ = 25 C IO Output Current ma Figure 25 Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co. POST OFFICE BOX 65533 DALLAS, TEXAS 75265 5
APPLICATION FORMATION The TPS767xx family includes eight fixed-output voltage regulators (.5 V,.8 V, 2.5 V, 2.7 V, 2.8 V, 3. V, 3.3 V, and 5. V), and an adjustable regulator, the TPS767 (adjustable from.5 V to 5.5 V). device operation The TPS767xx features very low quiescent current, which remains virtually constant even with varying loads. Conventional LDO regulators use a pnp pass element, the base current of which is directly proportional to the load current through the regulator (I B = I C /β). The TPS767xx uses a PMOS transistor to pass current; because the gate of the PMOS is voltage driven, operating current is low and invariable over the full load range. Another pitfall associated with the pnp-pass element is its tendency to saturate when the device goes into dropout. The resulting drop in β forces an increase in I B to maintain the load. During power up, this translates to large start-up currents. Systems with limited supply current may fail to start up. In battery-powered systems, it means rapid battery discharge when the voltage decays below the minimum required for regulation. The TPS767xx quiescent current remains low even when the regulator drops out, eliminating both problems. The TPS767xx family also features a shutdown mode that places the output in the high-impedance state (essentially equal to the feedback-divider resistance) and reduces quiescent current to 2 µa. If the shutdown feature is not used, EN should be tied to ground. minimum load requirements The TPS767xx family is stable even at zero load; no minimum load is required for operation. FB pin connection (adjustable version only) The FB pin is an input pin to sense the output voltage and close the loop for the adjustable option. The output voltage is sensed through a resistor divider network to close the loop as shown in Figure 27. Normally, this connection should be as short as possible; however, the connection can be made near a critical circuit to improve performance at that point. Internally, FB connects to a high-impedance wide-bandwidth amplifier and noise pickup feeds through to the regulator output. Routing the FB connection to minimize/avoid noise pickup is essential. external capacitor requirements An input capacitor is not usually required; however, a ceramic bypass capacitor (.47 µf or larger) improves load transient response and noise rejection if the TPS767xx is located more than a few inches from the power supply. A higher-capacitance electrolytic capacitor may be necessary if large (hundreds of milliamps) load transients with fast rise times are anticipated. Like all low dropout regulators, the TPS767xx requires an output capacitor connected between and GND to stabilize the internal control loop. The minimum recommended capacitance value is µf and the ESR (equivalent series resistance) must be between 5 mω and.5 Ω. Capacitor values µf or larger are acceptable, provided the ESR is less than.5 Ω. Solid tantalum electrolytic, aluminum electrolytic, and multilayer ceramic capacitors are all suitable, provided they meet the requirements described above. Most of the commercially available µf surface-mount ceramic capacitors, including devices from Sprague and Kemet, meet the ESR requirements stated above. 6 POST OFFICE BOX 65533 DALLAS, TEXAS 75265
external capacitor requirements (continued) APPLICATION FORMATION TPS767xx VI C. µf 6 7 5 EN RESET GND 6 4 3 RESET 25 kω VO + Co µf 3 Figure 26. Typical Application Circuit (Fixed Versions) programming the TPS767 adjustable LDO regulator The output voltage of the TPS767 adjustable regulator is programmed using an external resistor divider as shown in Figure 27. The output voltage is calculated using: V V. R. O ref R2 () Where: V ref =.834 V typ (the internal reference voltage) Resistors R and R2 should be chosen for approximately 5-µA divider current. Lower value resistors can be used but offer no inherent advantage and waste more power. Higher values should be avoided as leakage currents at FB increase the output voltage error. The recommended design procedure is to choose R2 = 3. kω to set the divider current at 5 µa and then calculate R using: R. V O V ref. R2 (2) VI. µf.7 V.9 V TPS767 RESET EN Reset Output 25 kω VO R Co PUT VOLTAGE 2.5 V 3.3 V 3.6 V 4.75 V PUT VOLTAGE PROGRAMMG GUIDE R 33.2 53.6 6.9 9.8 R2 3. 3. 3. 3. UNIT kω kω kω kω FB / NC GND R2 Figure 27. TPS767 Adjustable LDO Regulator Programming POST OFFICE BOX 65533 DALLAS, TEXAS 75265 7
reset indicator APPLICATION FORMATION The TPS767xx features a RESET output that can be used to monitor the status of the regulator. The internal comparator monitors the output voltage: when the output drops to between 92% and 98% of its nominal regulated value, the RESET output transistor turns on, taking the signal low. The open-drain output requires a pullup resistor. If not used, it can be left floating. RESET can be used to drive power-on reset circuitry or as a low-battery indicator. RESET does not assert itself when the regulated output voltage falls outside the specified 2% tolerance, but instead reports an output voltage low relative to its nominal regulated value (refer to timing diagram for start-up sequence). regulator protection The TPS767xx PMOS-pass transistor has a built-in back diode that conducts reverse currents when the input voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be appropriate. The TPS767xx also features internal current limiting and thermal protection. During normal operation, the TPS767xx limits output current to approximately.7 A. When current limiting engages, the output voltage scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds 5 C(typ), thermal-protection circuitry shuts it down. Once the device has cooled below 3 C(typ), regulator operation resumes. power dissipation and junction temperature Specified regulator operation is assured to a junction temperature of 25 C; the maximum junction temperature should be restricted to 25 C under normal operating conditions. This restriction limits the power dissipation the regulator can handle in any given application. To ensure the junction temperature is within acceptable limits, calculate the maximum allowable dissipation, P D(max), and the actual dissipation, P D, which must be less than or equal to P D(max). The maximum-power-dissipation limit is determined using the following equation: P D(max) T J max T A R θja Where: T J max is the maximum allowable junction temperature. R θja is the thermal resistance junction-to-ambient for the package, i.e., 72 C/W for the 8-terminal SOIC and 32.6 C/W for the 2-terminal PWP with no airflow. T A is the ambient temperature. The regulator dissipation is calculated using: P D.V I V O. I O Power dissipation resulting from quiescent current is negligible. Excessive power dissipation will trigger the thermal protection circuit. 8 POST OFFICE BOX 65533 DALLAS, TEXAS 75265
D (R-PDSO-G**) 4 P SHOWN MECHANICAL DATA PLASTIC SMALL-LE PACKAGE 4.5 (,27).2 (,5).4 (,35) 8. (,25) M PS ** DIM A MAX A M 8.97 (5,).89 (4,8) 4.344 (8,75).337 (8,55) 6.394 (,).386 (9,8).57 (4,).5 (3,8).244 (6,2).228 (5,8).8 (,2) NOM 7 Gage Plane A. (,25) 8.44 (,2).6 (,4) Seating Plane.69 (,75) MAX. (,25).4 (,).4 (,) 4447/ B 3/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed.6 (,5). D. Four center pins are connected to die mount pad. E. Falls within JEDEC MS-2 POST OFFICE BOX 65533 DALLAS, TEXAS 75265 9
PWP (R-PDSO-G**) 2-P SHOWN MECHANICAL DATA PowerPAD PLASTIC SMALL-LE PACKAGE,65 2,3,9, M Thermal Pad (See Note D) 4,5 4,3 6,6 6,2,5 NOM Gage Plane,25 A 8,75,5,2 MAX,5,5 Seating Plane, DIM PS ** 4 6 2 24 28 A MAX 5, 5, 6,6 7,9 9,8 A M 4,9 4,9 6,4 7,7 9,6 473225/E 3/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusions. D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. E. Falls within JEDEC MO-53 PowerPAD is a trademark of Texas Instruments. 2 POST OFFICE BOX 65533 DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Mailing Address: Texas Instruments Post Office Box 65533 Dallas, Texas 75265 Copyright 22, Texas Instruments Incorporated