TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION

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1 Available in 2.5-V, 3-V, 3.3-V, 4.85-V, and 5-V Fixed-Output and Adjustable Versions Integrated Precision Supply-Voltage Supervisor Monitoring Regulator Output Voltage Active-Low Reset Signal with 2-ms Pulse Width Very Low Dropout Voltage...Maximum of 35 mv at I O = 1 ma (TPS735) Low Quiescent Current Independent of Load µa Typ Extremely Low Sleep-State Current,.5 µa Max 2% Tolerance Over Full Range of Load, Line, and Temperature for Fixed-Output Versions Output Current Range of ma to 5 ma TSSOP Package Option Offers Reduced Component Height For Critical Applications GND EN IN IN GND GND GND NC NC EN NC IN IN IN D OR P PACKAGE (TOP VIEW) PW PACKAGE (TOP VIEW) RESET SENSE /FB OUT OUT RESET NC NC FB NC SENSE OUT OUT NC NC description TJ 4 C to 125 C The TPS73xx devices are members of a family of micropower low-dropout (LDO) voltage regulators. They are differentiated from the TPS71xx and TPS72xx LDOs by their integrated delayed microprocessor-reset function. If the precision delayed reset is not required, the TPS71xx and TPS72xx should be considered. OUTPUT VOLTAGE (V) AVAILABLE OPTIONS NEGATIVE-GOING RESET THRESHOLD VOLTAGE (V) MIN TYP MAX MIN TYP MAX SMALL OUTLINE (D) NC No internal connection SENSE Fixed voltage options only (TPS7325, TPS733, TPS7333, TPS7348, and TPS735) FB Adjustable version only (TPS731) PACKAGED DEVICES PLASTIC DIP (P) TSSOP (PW) CHIP FORM (Y) TPS735QD TPS735QP TPS735QPW TPS735Y TPS7348QD TPS7348QP TPS7348QPW TPS7348Y TPS7333QD TPS7333QP TPS7333QPW TPS7333Y TPS733QD TPS733QP TPS733QPW TPS733Y TPS7325QD TPS7325QP TPS7325QPW TPS7325Y Adjustable TPS731QD TPS731QP TPS731QPW TPS731Y 1.2 V to 9.75 V The D and PW packages are available taped and reeled. Add an R suffix to device type (e.g., TPS735QDR). The TPS731Q is programmable using an external resistor divider (see application information). The chip form is tested at 25 C. The TPS7325 has a tolerance of ±3% over the full temperature range. The TPS71xx and the TPS72xx are 5-mA and 25-mA output regulators respectively, offering performance similar to that of the TPS73xx but without the delayed-reset function. The TPS72xx devices are further differentiated by availability in 8-pin thin-shrink small-outline packages (TSSOP) for applications requiring minimum package size. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 1999, Texas Instruments Incorporated POST OFFICE BOX DALLAS, TEXAS

2 description (continued) The RESET output of the TPS73xx initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS73xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage. If that occurs, the RESET output (open-drain NMOS) turns on, taking the RESET signal low. RESET stays low for the duration of the undervoltage condition. Once the undervoltage condition ceases, a 2-ms (typ) time-out begins. At the completion of the 2-ms delay, RESET goes high. An order of magnitude reduction in dropout voltage and quiescent current over conventional LDO performance is achieved by replacing the typical pnp pass transistor with a PMOS device. Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (maximum of 35 mv at an output current of 1 ma for the TPS735) and is directly proportional to the output current (see Figure 1). Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is low and remains constant, independent of output loading (typically 34 µa over the full range of output current, ma to 5 ma). These two key specifications yield a significant improvement in operating life for battery-powered systems. The LDO family also features a sleep mode; applying a logic high signal to EN (enable) shuts down the regulator, reducing the quiescent current to.5 µa maximum at T J = 25 C. The TPS73xx is offered in 2.5-V, 3-V, 3.3-V, 4.85-V, and 5-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.2 V to 9.75 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges (3% for the 2.5 V and the adjustable version). The TPS73xx family is available in PDIP (8 pin), SO (8 pin) and TSSOP (2 pin) packages. The TSSOP has a maximum height of 1.2 mm. Dropout Voltage V TPS7325 TPS733 TPS7333 TPS7348 TPS735 VI.1 µf TPS73xxPW IN IN RESET SENSE IN OUT EN OUT GND To System Reset 25 kω VO CO + 1 µf CSR = 1 Ω IO Output Current ma Figure 1. Dropout Voltage Versus Output Current TPS7325, TPS733, TPS7333, TPS7348, TPS735 (fixed-voltage options) Capacitor selection is nontrivial. See application information section for details. Figure 2. Typical Application Configuration 2 POST OFFICE BOX DALLAS, TEXAS 75265

3 TPS73xxY chip information TPS731Q, TPS7325Q, TPS733Q, TPS7333Q, TPS7348Q, TPS735Q These chips, when properly assembled, display characteristics similar to those of the TPS73xxQ. Thermal compression or ultrasonic bonding may be used on the doped aluminum bonding pads. Chips may be mounted with conductive epoxy or a gold-silicon preform. BONDING PAD ASSIGNMENTS (6) (5) (4) IN EN (3) (2) TPS73xx (5) (6) (4) (7) SENSE FB OUT RESET (1) (7) GND 8 CHIP THICKNESS: 15 TYPICAL BONDING PADS: 4 4 MINIMUM TJmax = 15 C TOLERANCES ARE ±1%. ALL DIMENSIONS ARE IN MILS. (1) (2) (3) SENSE Fixed voltage options only (TPS7325, TPS733, TPS7333, TPS7348, and TPS735) FB Adjustable version only (TPS731) 92 NOTE A. For most applications, OUT and SENSE should be tied together as close as possible to the device; for other implementations, refer to SENSE-pin connection discussion in the applications information section of this data sheet. functional block diagram IN EN Vref _ + + _ GND Delayed Reset R1 R2 RESISTOR DIVIDER OPTIONS DEVICE UNIT TPS731 Ω RESET TPS kω TPS kω TPS kω TPS kω OUT TPS kω NOTE A. Resistors are nominal values only. SENSE /FB For most applications, SENSE should be externally connected to OUT as close as possible to the device. For other implementations, refer to SENSE-pin connection discussion in applications information section. Switch positions are shown with EN low (active). R1 R2 COMPONENT COUNT MOS transistors Bilpolar transistors Diodes Capacitors Resistors POST OFFICE BOX DALLAS, TEXAS

4 timing diagram VI Vres Vres t VO VIT + VIT + Threshold Voltage VIT VIT t Output Undefined RESET Output ÎÎ ÎÎ ÎÎ 2 ms Delay 2 ms Delay ÎÎ ÎÎ ÎÎ t Output Undefined Vres is the minimum input voltage for a valid RESET. The symbol Vres is not currently listed within EIA or JEDEC standards for semiconductor symbology. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Input voltage range, V I, RESET, SENSE, EN V to 11 V Output current, I O A Continuous total power dissipation See Dissipation Rating Tables 1 and 2 Operating virtual junction temperature range, T J C to 15 C Storage temperature range, T stg C to 15 C Lead temperature 1,6 mm (1/16 inch) from case for 1 seconds C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network terminal ground. 4 POST OFFICE BOX DALLAS, TEXAS 75265

5 PACKAGE TPS731Q, TPS7325Q, TPS733Q, TPS7333Q, TPS7348Q, TPS735Q DISSIPATION RATING TABLE 1 FREE-AIR TEMPERATURE (SEE FIGURE 3) TA A 25 C DERATING FACTOR TA A = 7 C TA A = 125 C POWER RATING ABOVE POWER RATING POWER RATING D 725 mw 5.8 mw/ C 464 mw 145 mw P 1175 mw 9.4 mw/ C 752 mw 235 mw PW 7 mw 5.6 mw/ C 448 mw 14 mw PACKAGE DISSIPATION RATING TABLE 2 CASE TEMPERATURE (SEE FIGURE 4) TC C 25 C DERATING FACTOR TC C = 7 C TC C = 125 C POWER RATING ABOVE TC = 25 C POWER RATING POWER RATING D 2188 mw 9.4 mw/ C 1765 mw 1248 mw P 2738 mw 21.9 mw/ C 1752 mw 548 mw PW 425 mw 32.2 mw/ C 2576 mw 85 mw Refer to Thermal Information section for detailed power dissipation considerations when using the TSSOP package. P D Maximum Continuous Dissipation mw MAXIMUM CONTINUOUS DISSIPATION FREE-AIR TEMPERATURE PW Package RθJA = 178 C/W P Package RθJA = 16 C/W D Package RθJA = 172 C/W P D Maximum Continuous Dissipation mw MAXIMUM CONTINUOUS DISSIPATION CASE TEMPERATURE PW Package RθJC = 37 C/W D Package RθJC = 57 C/W P Package RθJC = 46 C/W TA Free-Air Temperature C Figure TC Case Temperature C Figure 4 POST OFFICE BOX DALLAS, TEXAS

6 recommended operating conditions MIN MAX UNIT TPS731Q TPS7325Q TPS733Q V Input voltage, VI TPS7333Q TPS7348Q V TPS735Q High-level input voltage at EN, VIH 2 V Low-level input voltage at EN, VIL.5 V Output current range, IO 5 ma Operating virtual junction temperature range, TJ C Minimum input voltage defined in the recommended operating conditions is the maximum specified output voltage plus dropout voltage, VDO, at the maximum specified load range. Since dropout voltage is a function of output current, the usable range can be extended for lighter loads. To calculate the minimum input voltage for the maximum load current used in a given application, use the following equation: V I(min) V O(max) V DO(max load) Because the TPS731 is programmable, rds(on) should be used to calculate VDO before applying the above equation. The equation for calculating VDO from rds(on) is given in Note 2 in the TPS731 electrical characteristics table. The minimum value of 2.97 V is the absolute lower limit for the recommended input voltage range for the TPS731. V 6 POST OFFICE BOX DALLAS, TEXAS 75265

7 electrical characteristics at I O = 1 ma, EN = V, C o = 4.7 µf (CSR = 1 Ω), SENSE/FB shorted to OUT (unless otherwise noted) Ground current (active mode) PARAMETER TEST CONDITIONS TJ MIN TYP MAX UNIT Input current (standby mode) EN = VI, 27V 2.7 VI 1 V Output current limit VO =V V, VI =1V Pass-element leakage current in standby mode EN.5 V, = 25 C 34 4 VI VO + 1 V, ma IO 5 ma 4 C to 125 C 55 EN = VI, 27V 2.7 VI 1 V 25 C C to 125 C 2 25 C C to 125 C 2 25 C C to 125 C 1 25 C.2.5 RESET leakage current Normal operation, V at RESET = 1 V µa 4 C to 125 C.5 Output voltage temperature coefficient 4 C to 125 C ppm/ C Thermal shutdown junction temperature 165 C EN logic high (standby mode) EN logic low (active mode) 2.5 V VI 6 V 6 V VI 1 V 27V 2.7 VI 1 V 4 C to125 C C.5 4 C to 125 C.5 EN hysteresis voltage 25 C 5 mv EN input current Minimum VI for active pass element V VI 1 V Minimum VI for valid RESET IO(RESET) = 3 µa 25 C C to 125 C C C to 125 C C C to 125 C 1.9 CSR (compensation series resistance) refers to the total series resistance, including the equivalent series resistance (ESR) of the capacitor, any series resistance added externally, and PWB trace resistance to Co. Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. µa µa A µa V V µa V V POST OFFICE BOX DALLAS, TEXAS

8 TPS731Q electrical characteristics at I O = 1 ma, V I = 3.5 V, EN = V, C o = 4.7 µf (CSR = 1 Ω), FB shorted to OUT at device leads (unless otherwise noted) PARAMETER TEST CONDITIONS TJ MIN TYP MAX UNIT Reference voltage (measured at FB) 2.5 V VI 1 V, See Note 1 Reference voltage temperature coefficient Pass-element series resistance (See Note 2) VI =24V 2.4 V, 5 ma IO 5 ma, 5 µa IO 15 ma 25 C V 4 C to 125 C V 4 C to 125 C ppm/ C 25 C C to 125 C 1 25 C VI =24V 2.4 V, 15 ma IO 5 ma 4 C to 125 C 1.3 Ω 25 C VI =29V 2.9 V, 5 µa IO 5 ma 4 C to 125 C.85 VI = 3.9 V, 5 µa IO 5 ma 25 C.32 VI = 5.9 V, 5 µa IO 5 ma 25 C.23 VI = 2.5 V to 1 V, 5 µa IO 5 ma, 25 C 3 18 Input regulation See Note 1 4 C to 125 C 25 Output regulation Ripple rejection 2.5 V VI 1 V, IO = 5 ma to 5 ma, 25 C 5 14 See Note 1 4 C to 125 C V VI 1 V, IO = 5 µa to 5 ma, 25 C 7 22 See Note 1 4 C to 125 C 54 f = 12 Hz IO =5µA 25 C C to 125 C 44 IO O = 5 ma, 25 C See Note 1 4 C to 125 C 44 Output noise-spectral density f = 12 Hz 25 C 2 µv/ Hz Co = 4.7 µf 25 C 95 Output noise voltage 1 Hz f 1 khz Co = 1 µf 25 C 89 µvrms Co = 1 µf 25 C 74 RESET trip-threshold voltage VO(FB) decreasing 4 C to 125 C V RESET hysteresis voltage Measured at VO(FB) 25 C 12 mv RESET output low voltage VI = 2.13 V, IO(RESET) = 4 µa FB input current 25 C C to 125 C.4 25 C C to 125 C 2 2 CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co. Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. Output voltage programmed to 2.5 V with closed-loop configuration (see application information). NOTES: 1. When VI < 2.9 V and IO > 15 ma simultaneously, pass element rds(on) increases (see Figure 33) to a point where the resulting dropout voltage prevents the regulator from maintaining the specified tolerance range. 2. To calculate dropout voltage, use equation: VDO = IO rds(on) rds(on) is a function of both output current and input voltage. This parametric table lists rds(on) for VI = 2.4 V, 2.9 V, 3.9 V, and 5.9 V, which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V, 4 V, and 6 V respectively. For other programmed values, refer to Figure 33. mv mv mv db V na 8 POST OFFICE BOX DALLAS, TEXAS 75265

9 TPS7325Q electrical characteristics at I O = 1 ma, V I = 3.5 V, EN = V, C o = 1 µf (CSR = 1 Ω), SENSE shorted to OUT (unless otherwise noted) Output voltage PARAMETER TEST CONDITIONS TJ MIN TYP MAX UNIT Dropout voltage IO = 1 ma, VI = 2.97 V 25 C V VI 1 V, 5 ma IO 5 ma 4 C to 125 C IO =1mA ma, IO = 5 ma, VI = 2.97 V VI = 2.97 V 25 C 5 4 C to 125 C C C to 125 C C C to 125 C 6 (2.97 V VO)/IO, VI = 2.97 V, 25 C.5.7 Pass-element series resistance O, IO = 5 ma 4 C to 125 C 1.4 Input regulation VI =35Vto1V 3.5 V, 5 µa IO 5 ma Output regulation Ripple rejection IO =5mAto5mA 5 ma, IO =5µA to 5 ma, f = 12 Hz 35V 3.5 VI 1 V 35V 3.5 VI 1 V IO =5µA IO = 5 ma 25 C C to 125 C C C to 125 C 5 25 C C to 125 C 1 25 C C to 125 C C C to 125 C 32 Output noise-spectral density f = 12 Hz 25 C 2 µv/ Hz Co = 4.7 µf 25 C 274 Output noise voltage 1 Hz f 1 khz Co = 1 µf 25 C 228 µvrms Co = 1 µf 25 C 159 RESET trip-threshold voltage VO decreasing 4 C to 125 C V 25 C.14.4 RESET output low voltage VI = 2.1 V, IO(RESET) =.8 ma V 4 C to 125 C.4 CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co. Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. Dropout test and pass-element series resistance test are not production tested. Test method requires SENSE terminal to be disconnected from output voltage. V mv Ω mv mv mv db POST OFFICE BOX DALLAS, TEXAS

10 TPS733Q electrical characteristics at I O = 1 ma, V I = 4 V, EN = V, C o = 4.7 µf (CSR = 1 Ω), SENSE shorted to OUT (unless otherwise noted) Output voltage PARAMETER TEST CONDITIONS TJ MIN TYP MAX UNIT 25 C 3 4 V VI 1 V, 5 ma IO 5 ma 4 C to 125 C IO =1mA ma, VI = 2.94 V Dropout voltage IO = 1 ma, VI = 2.94 V Pass-element series resistance IO = 5 ma, VI = 2.94 V 25 C C to 125 C 1 25 C C to 125 C 1 25 C C to 125 C 5 (2.94 V VO)/IO, O, VI = 2.94 V, 25 C.5.7 IO = 5 ma 4 C to 125 C 1 Input regulation VI =4Vto1V V, 5 µa IO 5 ma Output regulation Ripple rejection IO =5mAto5mA 5 ma, IO =5µA to 5 ma, f = 12 Hz 4V VI 1 V 4V VI 1 V IO =5µA IO = 5 ma 25 C C to 125 C C C to 125 C 6 25 C C to 125 C C C to 125 C 4 25 C C to 125 C 36 Output noise-spectral density f = 12 Hz 25 C 2 µv/ Hz Co = 4.7 µf 25 C 274 Output noise voltage 1 Hz f 1 khz Co = 1 µf 25 C 228 µvrms Co = 1 µf 25 C 159 RESET trip-threshold voltage VO decreasing 4 C to 125 C V 25 C.14.4 RESET output low voltage VI = 2.6 V, IO(RESET) =.8 ma V 4 C to 125 C.4 CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co. Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. V mv Ω mv mv mv db 1 POST OFFICE BOX DALLAS, TEXAS 75265

11 TPS7333Q electrical characteristics at I O = 1 ma, V I = 4.3 V, EN = V, C o = 4.7 µf (CSR = 1 Ω), SENSE shorted to OUT (unless otherwise noted) Output voltage PARAMETER TEST CONDITIONS TJ MIN TYP MAX UNIT 25 C V VI 1 V, 5 ma IO 5 ma 4 C to 125 C IO =1mA ma, VI = 3.23 V Dropout voltage IO = 1 ma, VI = 3.23 V Pass-element series resistance IO = 5 ma, VI = 3.23 V 25 C C to 125 C 8 25 C C to 125 C 8 25 C C to 125 C 4 (3.23 V VO)/IO, O, VI = 3.23 V, 25 C.44.6 IO = 5 ma 4 C to 125 C.8 25 C 6 23 Input regulation VI =43Vto1V 4.3 V, 5 µa IO 5 ma mv 4 C to 125 C 29 Output regulation Ripple rejection IO =5mAto5mA 5 ma, 43V 4.3 VI 1 V IO =5µA to 5 ma, 4.3 V VI 1 V f = 12 Hz IO =5µA IO = 5 ma 25 C C to 125 C C C to 125 C C C to 125 C 4 25 C C to 125 C 36 Output noise-spectral density f = 12 Hz 25 C 2 µv/ Hz Co = 4.7 µf 25 C 274 Output noise voltage 1 Hz f 1 khz Co = 1 µf 25 C 228 µvrms Co = 1 µf 25 C 159 RESET trip-threshold voltage VO decreasing 4 C to 125 C V RESET hysteresis voltage 25 C 18 mv 25 C.17.4 RESET output low voltage VI = 2.8 V, IO(RESET) = 1 ma V 4 C to 125 C.4 CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co. Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. V mv Ω mv mv db POST OFFICE BOX DALLAS, TEXAS

12 TPS7348Q electrical characteristics at I O = 1 ma, V I = 5.85 V, EN = V, C o = 4.7 µf (CSR = 1 Ω), SENSE shorted to OUT (unless otherwise noted) Output voltage PARAMETER TEST CONDITIONS TJ MIN TYP MAX UNIT 25 C V VI 1 V, 5 ma IO 5 ma 4 C to 125 C IO =1mA ma, VI = 4.75 V Dropout voltage IO = 1 ma, VI = 4.75 V Pass-element series resistance IO = 5 ma, VI = 4.75 V 25 C C to 125 C 8 25 C C to 125 C C C to 125 C 25 (4.75 V VO)/IO, O, VI = 4.75 V, 25 C IO = 5 ma 4 C to 125 C C 9 35 Input regulation VI =585Vto1V 5.85 V, 5 µa IO 5 ma mv 4 C to 125 C 37 Output regulation Ripple rejection IO =5mAto5mA 5 ma, 585V 5.85 VI 1 V IO =5µA to 5 ma, 5.85 V VI 1 V f = 12 Hz IO =5µA IO = 5 ma 25 C C to 125 C 8 25 C C to 125 C C C to 125 C C C to 125 C 35 Output noise-spectral density f = 12 Hz 25 C 2 µv/ Hz Co = 4.7 µf 25 C 41 Output noise voltage 1 Hz f 1 khz Co = 1 µf 25 C 328 µvrms Co = 1 µf 25 C 212 RESET trip-threshold voltage VO decreasing 4 C to 125 C V RESET hysteresis voltage 25 C 26 mv RESET output low voltage IO(RESET) = 1.2 ma,vi = 4.12 V 25 C C to 125 C.4 CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co. Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. V mv Ω mv mv db V 12 POST OFFICE BOX DALLAS, TEXAS 75265

13 TPS735Q electrical characteristics at I O = 1 ma, V I = 6 V, EN = V, C o = 4.7 µf (CSR = 1 Ω), SENSE shorted to OUT (unless otherwise noted) Output voltage PARAMETER TEST CONDITIONS TJ MIN TYP MAX UNIT 25 C 5 6 V VI 1 V, 5 ma IO 5 ma 4 C to 125 C IO =1mA ma, VI = 4.88 V Dropout voltage IO = 1 ma, VI = 4.88 V Pass-element series resistance IO = 5 ma, VI = 4.88 V 25 C C to 125 C 8 25 C C to 125 C 5 25 C C to 125 C 23 (4.88 V VO)/IO, O, VI = 4.88 V, 25 C IO = 5 ma 4 C to 125 C.5 25 C 4 25 Input regulation VI =6Vto1V V, 5 µa IO 5 ma mv 4 C to 125 C 45 Output regulation Ripple rejection IO =5mAto5mA 5 ma, IO =5µA to 5 ma, f = 12 Hz 6V VI 1 V 6V VI 1 V IO =5µA IO = 5 ma 25 C C to 125 C C C to 125 C C C to 125 C C C to 125 C 36 Output noise-spectral density f = 12 Hz 25 C 2 µv/ Hz Co = 4.7 µf 25 C 43 Output noise voltage 1 Hz f 1 khz Co = 1 µf 25 C 345 µvrms Co = 1 µf 25 C 22 RESET trip-threshold voltage VO decreasing 4 C to 125 C V RESET hysteresis voltage 25 C 28 mv RESET output low voltage IO(RESET) = 1.2 ma, VI = 4.25 V 25 C C to 125 C.4 CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co. Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. V mv Ω mv mv db V POST OFFICE BOX DALLAS, TEXAS

14 switching characteristics PARAMETER TEST CONDITIONS TJ RESET time-out delay See Figure 5 TPS731Q, TPS7333Q TPS7348Q, TPS735Q MIN TYP MAX 25 C C to 125 C 1 3 UNIT ms electrical characteristics at I O = 1 ma, EN = V, C o = 4.7 µf (CSR = 1 Ω), T J = 25 C, SENSE/FB shorted to OUT (unless otherwise noted) PARAMETER Ground current (active mode) EN.5 V, ma IO 5 ma TEST CONDITIONS VI = VO + 1 V, TPS731Y, TPS7333Y TPS7348Y, TPS735Y MIN TYP MAX UNIT 34 µa Input current (standby mode) EN = VI, 2.7 V VI 1 V.1 µa Output current limit VO = V, VI = 1 V 1.2 A Pass-element leakage current in standby mode EN = VI, 2.7 V VI 1 V.1 µa RESET leakage current Normal operation, V at RESET = 1 V.2 µa Thermal shutdown junction temperature 165 C EN logic low (active mode) 2.7 V VI 1 V.5 V EN hysteresis voltage 5 mv EN input current V VI 1 V.1 µa Minimum VI for active pass element 2.5 V Minimum VI for valid RESET IO(RESET) = 3 µa 1 V CSR (compensation series resistance) refers to the total series resistance, including the equivalent series resistance (ESR) of the capacitor, any series resistance added externally, and PWB trace resistance to Co. Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. 14 POST OFFICE BOX DALLAS, TEXAS 75265

15 TPS731Y electrical characteristics at I O = 1 ma, V I = 3.5 V, EN = V, C o = 4.7 µf (CSR = 1 Ω), T J = 25 C, FB shorted to OUT at device leads (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Reference voltage (measured at FB) V VI = 2.4 V, 5 µa IO 15 ma.7 VI = 2.4 V, 15 ma IO 5 ma.83 Pass-element series resistance (See Note 2) VI = 2.9 V, 5 µa IO 5 ma.52 Ω Input regulation Output regulation VI = 3.9 V, 5 µa IO 5 ma.32 Ripple rejection f = 12 Hz IO = 5 ma, See Note 1 VI = 5.9 V, 5 µa IO 5 ma.23 VI = 2.5 V to 1 V, See Note 1 5 µa IO 5 ma, 3 mv 2.5 V VI 1 V, See Note 1 IO = 5 ma to 5 ma, 5 mv 2.5 V VI 1 V, See Note 1 IO = 5 µa to 5 ma, 7 mv IO = 5 µa 59 Output noise-spectral density f = 12 Hz 2 µv/ Hz 54 Co = 4.7 µf 95 Output noise voltage 1 Hz f 1 khz Co = 1 µf 89 µvrms Co = 1 µf 74 RESET hysteresis voltage Measured at VO(FB) 12 mv RESET output low voltage VI = 2.13 V, IO(RESET) = 4 µa.1 V FB input current.1 na CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co. Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. Output voltage programmed to 2.5 V with closed-loop configuration (see application information). NOTES: 1. When VI < 2.9 V and IO > 15 ma simultaneously, pass element rds(on) increases (see Figure 33) to a point where the resulting dropout voltage prevents the regulator from maintaining the specified tolerance range. 2. To calculate dropout voltage, use equation: VDO = IO rds(on) rds(on) is a function of both output current and input voltage. The parametric table lists rds(on) for VI = 2.4 V, 2.9 V, 3.9 V, and 5.9 V, which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V, 4 V, and 6 V respectively. For other programmed values, refer to Figure 33. db POST OFFICE BOX DALLAS, TEXAS

16 TPS7325Y electrical characteristics at I O = 1 ma, V I = 3.5 V, EN = V, C o = 1 µf (CSR = 1 Ω), T J = 25 C, SENSE shorted to OUT (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Output voltage 2.5 V IO = 1 ma, VI = 2.97 V 5 Dropout voltage IO = 1 ma, VI = 2.97 V 5 mv Pass-element series resistance IO = 5 ma, VI = 2.97 V 27 (2.97 V VO)/IO, IO = 5 ma VI = 2.97 V,.5 Ω Input regulation VI = 3.5 V to 1 V, 5 µa IO 5 ma 6 mv Output regulation Ripple rejection IO = 5 ma to 5 ma, 3.5 V VI 1 V 2 mv IO = 5 µa to 5 ma, 3.5 V VI 1 V 28 mv f = 12 Hz IO = 5 µa 53 IO = 5 ma 53 Output noise-spectral density f = 12 Hz 2 µv/ Hz Co = 4.7 µf 274 Output noise voltage 1 Hz f 1 khz Co = 1 µf 228 µvrms Co = 1 µf 159 RESET output low voltage VI = 2.1 V, IO(RESET) =.8 ma.14 V CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co. Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. Dropout test and pass-element series resistance test are not production tested. Test method requires SENSE terminal to be disconnected from output voltage. db 16 POST OFFICE BOX DALLAS, TEXAS 75265

17 TPS733Y electrical characteristics at I O = 1 ma, V I = 4 V, EN = V, C o = 4.7 µf (CSR = 1 Ω), T J = 25 C, SENSE shorted to OUT (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Output voltage 3 V IO = 1 ma, VI = 2.94 V 5.2 Dropout voltage IO = 1 ma, VI = 2.94 V 52 mv Pass-element series resistance IO = 5 ma, VI = 2.94 V 267 (2.94 V VO)/IO, IO = 5 ma VI = 2.94 V,.5 Ω Input regulation VI = 4 V to 1 V, 5 µa IO 5 ma 6 mv Output regulation Ripple rejection IO = 5 ma to 5 ma, 4 V VI 1 V 2 mv IO = 5 µa to 5 ma, 4 V VI 1 V 28 mv f = 12 Hz IO = 5 µa 53 IO = 5 ma 53 Output noise-spectral density f = 12 Hz 2 µv/ Hz Co = 4.7 µf 274 Output noise voltage 1 Hz f 1 khz Co = 1 µf 228 µvrms Co = 1 µf 159 RESET output low voltage VI = 2.6 V, IO(RESET) =.8 ma.14 V CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co. Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. TPS7333Y electrical characteristics at I O = 1 ma, V I = 4.3 V, EN = V, C o = 4.7 µf (CSR = 1 Ω), T J = 25 C, SENSE shorted to OUT (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Output voltage 3.3 V IO = 1 ma, VI = 3.23 V 4.5 Dropout voltage IO = 1 ma, VI = 3.23 V 44 mv Pass-element series resistance IO = 5 ma, VI = 3.23 V 235 (3.23 V VO)/IO, IO = 5 ma VI = 3.23 V, db.44 Ω Input regulation VI = 4.3 V to 1 V, 5 µa IO 5 ma 6 mv Output regulation Ripple rejection IO = 5 ma to 5 ma, 4.3 V VI 1 V 21 mv IO = 5 µa to 5 ma, 4.3 V VI 1 V 31 mv f = 12 Hz IO = 5 µa 51 IO = 5 ma 49 Output noise-spectral density f = 12 Hz 2 µv/ Hz Co = 4.7 µf 274 Output noise voltage 1 Hz f 1 khz Co = 1 µf 228 µvrms Co = 1 µf 159 RESET hysteresis voltage 18 mv RESET output low voltage VI = 2.8 V, IO(RESET) = 1 ma.17 V CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co. Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. db POST OFFICE BOX DALLAS, TEXAS

18 TPS7348Y electrical characteristics at I O = 1 ma, V I = 5.85 V, EN = V, C o = 4.7 µf (CSR = 1 Ω), T J = 25 C, SENSE shorted to OUT (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Output voltage 4.85 V IO = 1 ma, VI = 4.75 V 2.9 Dropout voltage IO = 1 ma, VI = 4.75 V 28 mv Pass-element series resistance IO = 5 ma, VI = 4.75 V 15 (4.75 V VO)/IO, IO = 5 ma VI = 4.75 V,.28 Ω Input regulation VI = 5.85 V to 1 V, 5 µa IO 5 ma 9 mv Output regulation Ripple rejection IO = 5 ma to 5 ma, 5.85 V VI 1 V 28 mv IO = 5 µa to 5 ma, 5.85 V VI 1 V 42 mv f = 12 Hz IO = 5 µa 53 IO = 5 ma 5 Output noise-spectral density f = 12 Hz 2 µv/ Hz Co = 4.7 µf 41 Output noise voltage 1 Hz f 1 khz Co = 1 µf 328 µvrms Co = 1 µf 212 RESET hysteresis voltage 26 mv RESET output low voltage IO(RESET) = 1.2 ma, VI = 4.12 V.2 V CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co. Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. db 18 POST OFFICE BOX DALLAS, TEXAS 75265

19 TPS735Y electrical characteristics at I O = 1 ma, V I = 6 V, EN = V, C o = 4.7 µf (CSR = 1 Ω), T J = 25 C, SENSE shorted to OUT (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Output voltage 5 V IO = 1 ma, VI = 4.88 V Dropout voltage IO = 1 ma, VI = 4.88 V mv Pass-element series resistance IO = 5 ma, VI = 4.88 V (4.88 V VO)/IO, IO = 5 ma VI = 4.88 V, Ω Input regulation VI = 6 V to 1 V, 5 µa IO 5 ma 4 25 mv Output regulation Ripple rejection IO = 5 ma to 5 ma, 6 V VI 1 V mv IO = 5 µa to 5 ma, 6 V VI 1 V 41 mv f = 12 Hz IO = 5 µa 53 IO = 5 ma 51 Output noise-spectral density f = 12 Hz 2 µv/ Hz Co = 4.7 µf 43 Output noise voltage 1 Hz f 1 khz Co = 1 µf 345 µvrms Co = 1 µf 22 RESET hysteresis voltage 28 mv RESET output low voltage IO(RESET) = 1.2 ma, VI = 4.25 V.15.4 V CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co. Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. db POST OFFICE BOX DALLAS, TEXAS

20 PARAMETER MEASUREMENT INFORMATION VO VIT+ t VI IN RESET Reset EN SENSE.1 µf OUT GND + VO 1 µf CSR RESET RESET Timeout Delay t TEST CIRCUIT VOLTAGE WAVEFORMS Figure 5. Test Circuit and Voltage Waveforms VI IN OUT To Load SENSE EN GND + CO CSR Ccer RL Ceramic capacitor Figure 6. Test Circuit for Typical Regions of Stability (Refer to Figures 29 through 32) 2 POST OFFICE BOX DALLAS, TEXAS 75265

21 TYPICAL CHARACTERISTICS Table of Graphs IQ Quiescent current Output current 7 Input voltage 8 IQ Quiescent current TPS7348 Free-air temperature 9 IQ Quiescent current TPS7325 Input voltage 1 Free-air temperature 11 VDO Dropout voltage Output current 12 VDO Change in dropout voltage Free-air temperature 13 VDO Dropout voltage TPS731 Output current 14 VO Change in output voltage Free-air temperature 15 VO Output voltage Input voltage 16 VO Output voltage TPS7325 Input voltage 17 Line regulation 18 TPS731 Output current 19 TPS7325 Output current 2 VO Output voltage TPS733 Output current 21 TPS7333 Output current 22 TPS7348 Output current 23 TPS735 Output current 24 Output voltage response from enable (EN) 25 TPS731 or TPS TPS Load transient response TPS7348 or TPS TPS TPS TPS7348 or TPS Ripple rejection Frequency 32 Output spectral noise density Frequency 33 Output current 34 Co = 4.7 µf Compensation series resistance Added ceramic capacitance 35 (CSR) Output current 36 Co = 1 µf Added ceramic capacitance 37 rds(on) Pass-element resistance Input voltage 38 VI Minimum input voltage for valid RESET Free-air temperature 39 VIT Negative-going reset threshold Free-air temperature 4 IOL(RESET) RESET output current Input voltage 41 td Reset time delay Free-air temperature 42 td Distribution for reset delay 43 POST OFFICE BOX DALLAS, TEXAS

22 TYPICAL CHARACTERISTICS Quiescent Current µ A IQ TPS7333, VI = 4.3 V TPS7325, VI = 3.5 V QUIESCENT CURRENT OUTPUT CURRENT TPS73xx, VI = 1 V TPS735, VI = 6 V TPS7348, VI = 5.85 V TPS733, VI = 4 V Quiescent Current µ A IQ IO = 5 ma QUIESCENT CURRENT INPUT VOLTAGE TPS7333 TPS735 TPS731 With VO Programmed to 2.5 V TPS IO Output Current ma Figure VI Input Voltage V Figure VI = 5.85 V IO = 5 ma TPS7348 QUIESCENT CURRENT FREE-AIR TEMPERATURE 5 45 TPS7325 QUIESCENT CURRENT INPUT VOLTAGE IQ Quiescent Current µ A IQ Quiescent Current µ A TA = 125 C TA = 85 C TA = C TA Free-Air Temperature C Figure 9 TA = 4 C VI Input Voltage V Figure 1 22 POST OFFICE BOX DALLAS, TEXAS 75265

23 TYPICAL CHARACTERISTICS IQ Quiescent Current µ A IL = 75 ma TPS7325 QUIESCENT CURRENT FREE-AIR TEMPERATURE VI = 1 V VI = 3.5 V Dropout Voltage V DROPOUT VOLTAGE OUTPUT CURRENT TPS7325 TPS7333 TPS733 TPS7348 TPS TA Free-Air Temperature C Figure IO Output Current ma Figure 12 Change In Dropout Voltage mv V DO CHANGE IN DROPOUT VOLTAGE FREE-AIR TEMPERATURE IO = 1 ma V DO Dropout Voltage V TPS731 DROPOUT VOLTAGE OUTPUT CURRENT VI = 2.9 V VI = 3.2 V VI = 3.9 V VI = 5.9 V VI = 9.65 V VI = 2.4 V VI = 2.6 V TA Free-Air Temperature C Figure IO Output Current ma Figure 14 POST OFFICE BOX DALLAS, TEXAS

24 TYPICAL CHARACTERISTICS V O Change in Output Voltage mv CHANGE IN OUTPUT VOLTAGE FREE-AIR TEMPERATURE VI = VO(nom) + 1 V IO = 1 ma Output Voltage V V O IO = 5 ma OUTPUT VOLTAGE INPUT VOLTAGE TPS7333 TPS735 TPS731 With VO Programmed to 2.5 V and TPS7325 TPS TA Free-Air Temperature C Figure VI Input Voltage V Figure 16 Output Voltage V V O TPS7325 OUTPUT VOLTAGE INPUT VOLTAGE 1 ma 5 ma V O Change In Output Voltage mv IO = 25 ma TPS7325 LINE REGULATION TPS7333 TPS735 TPS VI Input Voltage V Figure VI Input Voltage V Figure POST OFFICE BOX DALLAS, TEXAS 75265

25 TYPICAL CHARACTERISTICS TPS731 OUTPUT VOLTAGE OUTPUT CURRENT VO Programmed to 2.5 V TPS7325 OUTPUT VOLTAGE OUTPUT CURRENT Output Voltage V V O VI = 1 V VI = 3.5 V Output Voltage V V O VI = 3.5 V VI = 1 V IO Output Current ma Figure IO Output Current ma Figure TPS733 OUTPUT VOLTAGE OUTPUT CURRENT TPS7333 OUTPUT VOLTAGE OUTPUT CURRENT Output Voltage V V O Output Voltage V V O VI = 4.3 V VI = 1 V IO Output Current ma Figure IO Output Current ma Figure 22 POST OFFICE BOX DALLAS, TEXAS

26 TYPICAL CHARACTERISTICS TPS7348 OUTPUT VOLTAGE OUTPUT CURRENT TPS735 OUTPUT VOLTAGE OUTPUT CURRENT Output Voltage V V O VI = 5.85 V VI = 1 V Output Voltage V V O VI = 6 V VI = 1 V IO Output Current ma Figure IO Output Current ma Figure 24 OUTPUT VOLTAGE RESPONSE FROM ENABLE (EN) Output Voltage V VO(nom) V O RL = 5 Ω Co = 4.7 µf (CSR = 1Ω) No Input Capacitance EN Voltage V Time µs Figure POST OFFICE BOX DALLAS, TEXAS 75265

27 TYPICAL CHARACTERISTICS V O Change in Output Voltage mv TPS731 (WITH VO PROGRAMMED TO 2.5 V) OR TPS7333 LOAD TRANSIENT RESPONSE VI = 6 V CI = Co = 4.7 µf (CSR = 1 Ω) t Time µs Figure Output Current ma I O 15 TPS7325 LOAD TRANSIENT RESPONSE V O Change in Output Voltage mv t Time µs IO = 1 ma VI = 6 V CI = Co = 1 µf Figure 27 POST OFFICE BOX DALLAS, TEXAS

28 TYPICAL CHARACTERISTICS V O Change in Output Voltage mv TPS7348 OR TPS735 LOAD TRANSIENT RESPONSE VI = 6 V CI = Co = 4.7 µf CSR = 1 Ω I O Output Current ma t Time µs Figure 28 V O Change in Output Voltage mv TPS731 WITH VO PROGRAMMED TO 2.5 V LINE TRANSIENT RESPONSE CI = Co = 4.7 µf (CSR = 1 Ω) t Time µs Input Voltage V V I Figure POST OFFICE BOX DALLAS, TEXAS 75265

29 TYPICAL CHARACTERISTICS V O Change in Output Voltage mv TPS7333 LINE TRANSIENT RESPONSE CI = Co = 4.7 µf (CSR = 1 Ω) V I Input Voltage V t Time µs Figure 3 V O Change in Output Voltage mv TPS7348 OR TPS735 LINE TRANSIENT RESPONSE CI = Co = 4.7 µf (CSR = 1 Ω) V I Input Voltage V t Time µs Figure 31 POST OFFICE BOX DALLAS, TEXAS

30 TYPICAL CHARACTERISTICS Ripple Rejection db TPS7333 TPS7348/ TPS735 RIPPLE REJECTION FREQUENCY K 1 K 1 K 1 M 1 M f Frequency Hz Figure 32 No Input Capacitance Added VI = VO + 1 V IO = 1 ma Co = 4.7 µf (CSR = 1) TPS731 With VO Programmed to 2.5 V Output Spectral-Noise Density µ V/ Hz OUTPUT SPECTRAL-NOISE DENSITY FREQUENCY Co = 1 µf (CSR = 1 Ω) No Input Capacitance Added VI = VO + 1 V Co = 4.7 µf (CSR = 1 Ω) k 1 k 1 k f Frequency Hz Figure 33 Co = 1 µf (CSR = 1 Ω) CSR Compensation Series Resistance Ω TYPICAL REGIONS OF STABILITY COMPENSATION SERIES RESISTANCE (CSR) OUTPUT CURRENT Region of Instability VI = VO + 1 V Co = 4.7 µf No Added Ceramic Capacitance No Input Capacitance Added CSR Compensation Series Resistance Ω TYPICAL REGIONS OF STABILITY COMPENSATION SERIES RESISTANCE (CSR) ADDED CERAMIC CAPACITANCE Region of Instability VI = VO + 1 V IO = 5 ma Co = 4.7 µf No Input Capacitor Added Region of Instability Region of Instability IO Output Current ma Added Ceramic Capacitance µf Figure 34 Figure 35 3 POST OFFICE BOX DALLAS, TEXAS 75265

31 TYPICAL CHARACTERISTICS CSR Compensation Series Resistance Ω TYPICAL REGIONS OF STABILITY COMPENSATION SERIES RESISTANCE (CSR) OUTPUT CURRENT Region of Instability VI = VO + 1 V Co = 1 µf No Added Ceramic Capacitance No Input Capacitor Added Region of Instability CSR Compensation Series Resistance Ω 1 TYPICAL REGIONS OF STABILITY COMPENSATION SERIES RESISTANCE (CSR) ADDED CERAMIC CAPACITANCE Region of Instability VI = VO + 1 V IO = 5 ma Co = 1 µf No Input Capacitor Added Region of Instability IO Output Current ma Added Ceramic Capacitance µf Figure 36 Figure 37 r DS(on) Pass-Element Resistance Ω PASS-ELEMENT RESISTANCE INPUT VOLTAGE IO = 5 ma IO = 1 ma VI Input Voltage V Figure 38 VI(FB) = 1.12 V 9 1 Minimum Input Voltage For Valid RESET V ÁÁ V I MINIMUM INPUT VOLTAGE FOR VALID RESET FREE-AIR TEMPERATURE TA Free-Air Temperature C Figure 39 POST OFFICE BOX DALLAS, TEXAS

32 TYPICAL CHARACTERISTICS Negative-Going Reset Threshold mv ÁÁ V IT NEGATIVE-GOING RESET THRESHOLD FREE-AIR TEMPERATURE TA Free-Air Temperature C Figure 4 RESET Output Current ma I OL IL = 1 ma VOL.4 V RESET OUTPUT CURRENT INPUT VOLTAGE VI Input Voltage V Figure 41 TPS735 TPS7348 TPS RESET DELAY TIME FREE-AIR TEMPERATURE DISTRIBUTION FOR RESET DELAY 197 Devices Reset Delay Time ms td Percentage of Units % TA Free-Air Temperature C td Reset Delay Time ms Figure 42 Figure POST OFFICE BOX DALLAS, TEXAS 75265

33 THERMAL INFORMATION In response to system-miniaturization trends, integrated circuits are being offered in low-profile and fine-pitch surface-mount packages. Implementation of many of today s high-performance devices in these packages requires special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-dissipation limits of a given component. Three basic approaches for enhancing thermal performance are illustrated in this discussion: Improving the power-dissipation capability of the PWB design Improving the thermal coupling of the component to the PWB Introducing airflow in the system Figure 44 is an example of a thermally enhanced PWB layout for the 2-lead TSSOP package. This layout involves adding copper on the PWB to conduct heat away from the device. The R θja (thermal resistance, junction-to-ambient) for this component/ board system is illustrated in Figure 45. The family of curves illustrates the effect of increasing the size of the copper-heat-sink surface area. The PWB is a standard FR4 board (L W H = 3.2 inch 3.2 inch.62 inch); the board traces and heat sink area are 1-oz (per square foot) copper. Figure 46 shows the thermal resistance for the same system with the addition of a thermally-conductive compound between the body of the TSSOP package and the PWB copper routed directly beneath the device. The thermal conductivity for the compound used in this analysis is.815 W/m C. Using these figures to determine the system R θja allows the maximum power-dissipation limit to be calculated with the equation: T J(max) T A P D(max) R JA(system) Where T J(max) is the maximum allowable junction temperature; 15 C absolute maximum and 125 C maximum recommended operating temperature for specified operation. This limit should then be applied to the internal power dissipated by the TPS73xx regulator. The equation for calculating total internal power dissipation of the TPS73xx is: P D(total).V I V O. I O V I I Q Because the quiescent current of the TPS73xx family is very low, the second term is negligible, further simplifying the equation to: P D(total).V I V O. I O For a 2-lead TSSOP/ FR4 board system with thermally conductive compound between the board and the device body, where T A = 55 C, airflow = 1 ft/min, and copper heat sink area = 1 cm 2, the maximum power-dissipation limit can be calculated. As indicated in Figure 46, the system R θja is 94 C/W; therefore, the maximum power-dissipation limit is: P D(max) T J(max) T A R JA(system) 125 C 55 C 745 mw 94 C W If the system implements a TPS7348 regulator where V I = 6 V and I O = 15 ma, the internal power dissipation is: P D(total).V I V O. I O (6 4.85) mw POST OFFICE BOX DALLAS, TEXAS

34 THERMAL INFORMATION Comparing P D(total) with P D(max) reveals that the power dissipation in this example does not exceed the maximum limit. When it does, one of two corrective actions can be taken. The power-dissipation limit can be raised by increasing either the airflow or the heat-sink area. Alternatively, the internal power dissipation of the regulator can be lowered by reducing either the input voltage or the load current. In either case, the above calculations should be repeated with the new system parameters. Copper Heat Sink 1 oz Cu Figure 44. Thermally Enhanced PWB Layout (not to scale) for the 2-Pin TSSOP C/W R θja Thermal Resistance, Junction-to-Ambient THERMAL RESISTANCE, JUNCTION-TO-AMBIENT AIR FLOW cm2 4 cm2 Component/Board System 2-Lead TSSOP cm2 2 cm2 8 cm Air Flow ft /min Figure 45 3 C/W R θja Thermal Resistance, Junction-to-Ambient THERMAL RESISTANCE, JUNCTION-TO-AMBIENT AIR FLOW Component/Board System 2-Lead TSSOP Includes Thermally Conductive Compound Between Body and Board 8 cm2 4 cm2 2 cm Air Flow ft /min Figure 46 cm2 1 cm POST OFFICE BOX DALLAS, TEXAS 75265

35 APPLICATION INFORMATION The TPS73xx series of low-dropout (LDO) regulators overcome many of the shortcomings of earlier generation LDOs, while adding features such as a power-saving shutdown mode and a supply-voltage supervisor. The TPS73xx family includes five fixed-output voltage regulators: the TPS7325 (2.5 V), TPS733 (3 V), TPS7333 (3.3 V), the TPS7348 (4.85 V), and the TPS735 (5 V). The family also offers an adjustable device, the TPS731 (adjustable from 1.2 V to 9.75 V). device operation The TPS73xx, unlike many other LDOs, features very low quiescent currents that remain virtually constant even with varying loads. Conventional LDO regulators use a pnp-pass element, the base current of which is directly proportional to the load current through the regulator (I B = I C /β). Close examination of the data sheets reveals that such devices are typically specified under near no-load conditions; actual operating currents are much higher as evidenced by typical quiescent current versus load current curves (see Figure 7). The TPS73xx uses a PMOS transistor to pass current; because the gate of the PMOS element is voltage driven, operating currents are low and invariable over the full load range. The TPS73xx specifications reflect actual performance under load. Another pitfall associated with the pnp-pass element is its tendency to saturate when the device goes into dropout. The resulting drop in β forces an increase in I B to maintain the load. During power-up, this translates to large start-up currents. Systems with limited supply current may fail to start up. In battery-powered systems, it means rapid battery discharge when the voltage decays below the minimum required for regulation. The TPS73xx quiescent current remains low even when the regulator drops out, thus eliminating both problems. Included in the TPS73xx family is a 4.85-V regulator, the TPS7348. Designed specifically for 5-V cellular systems, its 4.85-V output, regulated to within ± 2%, allows for operation within the low-end limit of 5-V systems specified to ± 5% tolerance; therefore, maximum regulated operating lifetime is obtained from a battery pack before the device drops out, adding crucial talk minutes between charges. The TPS73xx family also features a shutdown mode that places the output in the high-impedance state (essentially equal to the feedback-divider resistance) and reduces quiescent current to under.5 µa. When the shutdown feature is not used, EN should be tied to ground. Response to an enable transition is quick; regulated output voltage is reestablished in typically 12 µs. minimum load requirements The TPS73xx family is stable even at zero load; no minimum load is required for operation. SENSE connection The SENSE terminal of fixed-output devices must be connected to the regulator output for proper functioning of the regulator. Normally, this connection should be as short as possible; however, the connection can be made near a critical circuit (remote sense) to improve performance at that point. Internally, SENSE connects to a high-impedance wide-bandwidth amplifier through a resistor-divider network, and noise pickup feeds through to the regulator output. It is essential to route the SENSE connection in such a way as to minimize/avoid noise pickup. Adding an RC network between SENSE and OUT to filter noise is not recommended because it can cause the regulator to oscillate. external capacitor requirements An input capacitor is not required; however, a ceramic bypass capacitor (.47 pf to.1 µf) improves load transient response and noise rejection when the TPS73xx is located more than a few inches from the power supply. A higher-capacitance electrolytic capacitor may be necessary if large (hundreds of milliamps) load transients with fast rise times are anticipated. POST OFFICE BOX DALLAS, TEXAS

36 APPLICATION INFORMATION external capacitor requirements (continued) As with most LDO regulators, the TPS73xx family requires an output capacitor for stability. A low-esr 1-µF solid-tantalum capacitor connected from the regulator output to ground is sufficient to ensure stability over the full load range (see Figure 42). Adding high-frequency ceramic or film capacitors (such as power-supply bypass capacitors for digital or analog ICs) can cause the regulator to become unstable unless the ESR of the tantalum capacitor is less than 1.2 Ω over temperature. Capacitors with published ESR specifications such as the AVX TPSD16M35R3 and the Sprague 593D16X35D2W work well because the maximum ESR at 25 C is 3 mω (typically, the ESR in solid-tantalum capacitors increases by a factor of 2 or less when the temperature drops from 25 C to 4 C). Where component height and/or mounting area is a problem, physically smaller, 1-µF devices can be screened for ESR. Figures 29 through 32 show the stable regions of operation using different values of output capacitance with various values of ceramic load capacitance. In applications with little or no high-frequency bypass capacitance (<.2 µf), the output capacitance can be reduced to 4.7 µf, provided ESR is maintained between.7 and 2.5 Ω. Because capacitor minimum ESR is seldom if ever specified, it may be necessary to add a.5-ω to 1-Ω resistor in series with the capacitor and limit ESR to 1.5 Ω maximum. As shown in the CSR graphs (Figures 29 through 32), minimum ESR is not a problem when using 1-µF or larger output capacitors. Below is a partial listing of surface-mount capacitors usable with the TPS73xx family. This information, along with the CSR graphs, is included to assist in selection of suitable capacitance for the user s application. When necessary to achieve low height requirements along with high output current and/or high ceramic load capacitance, several higher ESR capacitors can be used in parallel to meet the guidelines above. All load and temperature conditions with up to 1 µf of added ceramic load capacitance: PART NO. MFR. VALUE MAX ESR SIZE (H L W) T421C226M1AS Kemet 22 µf, 1 V D156X25D2W Sprague 15 µf, 25 V D16X35D2W Sprague 1 µf, 35 V TPSD16M35R3 AVX 1 µf, 35 V Load < 2 ma, ceramic load capacitance <.2 µf, full temperature range: PART NO. MFR. VALUE MAX ESR SIZE (H L W) 592D156X2R2T Sprague 15 µf, 2 V D156X25C2T Sprague 15 µf, 25 V D16X25C2T Sprague 1 µf, 25 V D226X16D2W Sprague 22 µf, 16 V Load < 1 ma, ceramic load capacitance <.2 µf, full temperature range: PART NO. MFR. VALUE MAX ESR SIZE (H L W) 195D16X6R3V2T Sprague 1 µf, 6.3 V D16X16X2T Sprague 1 µf, 16 V D156X16B2T Sprague 15 µf, 16 V D226X15F2T Sprague 22 µf, 15 V D156X2F2T Sprague 15 µf, 2 V D16X35G2T Sprague 1 µf, 35 V Size is in mm. ESR is maximum resistance at 1 khz and. Listings are sorted by height. 36 POST OFFICE BOX DALLAS, TEXAS 75265