Dual Channel, 1.5MHz 800mA, Synchronous Step-Down Regulator. Features. Applications

Transcription

1 Dual Channel, 1.5MHz 800mA, Synchronous Step-Down Regulator General Description is designed with high efficiency step down DC/DC converter for portable devices applications. It features with extreme low quiescent current with no load which is the best fit for extending battery life during the standby mode. The device operates from 2.5V to 5.5V input voltage and up to 800mA output current capability. High 1.5MHz internal frequency makes small surface mount inductors and capacitors possible and reduces overall PCB board space. Further, build-in synchronous switch makes external Schottky diode is no longer needed and efficiency is improved. is designed base on pulse width modulation (PWM) for low output voltage ripple and fixed frequency noise, low dropout mode provides 100% duty cycle operation. Low reference voltage is designed for achieving regulated output down to 0.6V. Features Achieve 95% efficiency Input Voltage : 2.5V to 5.5V Output Current up to 800mA Reference voltage 0.6V Quiescent Current 200μA with No Load Internal switching frequency 1.5MHz No Schottky Diode needed Low Dropout Operation: 100% Duty Cycle Shutdown current < 1μA Excellent Line and Load Transient Response Over-temperature Protection Applications Blue-Tooth devices Cellular and Smart Phones Personal multi-media Player (PMP) Wireless networking Digital Still Cameras Portable applications is available in TDFN-10 package. Revision: 1.0 1/17

2 Typical Application FIG.1 Connection Diagrams Order information EN1 1 FB1 IN2 2 GND 4 7 SW GND SW1 GND IN1 FB2 EN2 -XXFF10NRR XX Output voltage 00 Adj output FF10 TDFN-10 Package NRR RoHS & Halogen free package Rating: -40 to 85 C Package in Tape & Reel TDFN-10 (3x3mm) Order, Marking & Packing Information Package Vout1 Vout2 Product ID. Marking Packing TDFN-10 Adj. Adj. -00FF10NRR Tape & Reel 5Kpcs Revision: 1.0 2/17

3 Pin Functions Name TDFN-10 Function Enable Pin for VOUT1. 1 EN1 Minimum 1.2V to enable the device. Maximum 0.4V to shut down the device. Do 2 FB1 (Adjustable) VOUT1 (Fixed voltage) not leave this pin floating. Feedback Pin for VOUT1. Receives the feedback voltage from an external resistive divider across the output. Output Voltage Pin for VOUT1. An internal resistive divider divides the output voltage down for comparison to the internal reference voltage. Input voltage Pin for VOUT2. 3 IN2 Must be closely decoupled to GND pin with a 4.7μF or greater ceramic capacitor. 4 GND Ground Pin for VOUT2. Switch Pin for VOUT2. 5 SW2 Must be connected to Inductor. This pin connects to the drains of the internal main and synchronous power MOSFET switches. Enable Pin for VOUT2. 6 EN2 Minimum 1.2V to enable the device. Maximum 0.4V to shut down the device. Do 7 FB2 (Adjustable) VOUT2 (Fixed voltage) not leave this pin floating. Feedback Pin for VOUT2. Receives the feedback voltage from an external resistive divider across the output. Output Voltage Pin for VOUT2. An internal resistive divider divides the output voltage down for comparison to the internal reference voltage. Input voltage Pin for VOUT1. 8 IN1 Must be closely decoupled to GND pin with a 4.7μF or greater ceramic capacitor. 9 GND Ground Pin for VOUT1. Switch Pin for VOUT1. 10 SW1 Must be connected to Inductor. This pin connects to the drains of the internal 11 GND Ground Pin. main and synchronous power MOSFET switches. Revision: 1.0 3/17

4 Absolute Maximum Ratings (Notes 1, 2) Input Voltage EN, FB SW -0.3V to 6V -0.3V to VIN -0.3V to (VIN +0.3V) Junction Temperature (TJ) 150 C Lead Temperature (Soldering, 10 sec.) 260 C ESD Rating Power Dissipation (Note 5) Storage Temperature Range -65 C to 150 C Human Body Model Machine model 2KV 200V Operating Ratings (Note 1, 2) Supply Voltage 2.5V to 5.5V Operating Temperature Range -40 C to 85 C Thermal Resistance (θja, Note 3)) Thermal Resistance (θjc, Note 4)) 110 C/W (TDFN-10) 8.5 C/W (TDFN-10) Electrical Characteristics The denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25 C. VIN = 3.6V unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units IVFB Feedback Current ±30 na VFB Regulated Feedback Voltage TA = 25 C V ΔVFB Reference Voltage Line Regulation VIN = 2.5V to 5.5V 0.4 %/V VOUT % Output Voltage Accuracy -3 3 % ΔVOVL Output Over-voltage Lockout ΔVOVL = VOVL VFB, 50 mv ΔVOVL = VOVL VOUT, -Fixed 7.8 % ΔVOUT Output Voltage Line Regulation VIN = 2.5V to 5.5V 0.4 %/V IPK Peak Inductor Current VIN = 3V, VFB = 0.5V or VOUT = 90%, Duty Cycle < 35% 1.3 A VLOADREG Output Voltage Load Regulation 0.5 % IS fosc Quiescent Current (Note 7) VFB = 0.5V or VOUT = 90% μa Shutdown VEN = 0V, VIN = 4.2V μa Oscillator Frequency VFB = 0.6V or VOUT = 100% MHz VFB = 0V or VOUT = 0V 290 khz RPFET R DS(ON) of PMOS ISW = 100mA Ω RNFET R DS(ON) of NMOS ISW = 100mA Ω ILSW SW Leakage VEN = 0V, VSW = 0V or 5V, VIN = 5V ±1 μa VEN Enable Threshold 1.2 V Shutdown Threshold 0.4 V IEN EN Leakage Current ±1 μa Revision: 1.0 4/17

5 Note 1: Absolute Maximum ratings indicate limits beyond which damage may occur. Electrical specifications do not apply when operating the device outside of its rated operating conditions. Note 2: All voltages are with respect to the potential at the ground pin. Note 3: θja is measured in the natural convection at TA=25 on a high effective thermal conductivity test board (2 layers, 2S0P). Note 4: θjc represents the resistance to the heat flows the chip to package top case. Note 5: Maximum Power dissipation for the device is calculated using the following equations: T J(MAX) - T A P D = θ JA Where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θja is the junction-to-ambient thermal resistance. E.g. for the TDFN-10 packageθja = 110 C/W, TJ (MAX) = 150 C and using TA = 25 C, the maximum power dissipation is found to be 1.13W. The derating factor (-1/θJA) = -9.09mW/ C, thus below 25 C the power dissipation figure can be increased by 9.09mW per degree, and similarity decreased by this factor for temperatures above 25 C. Note 6: Typical Values represent the most likely parametric norm. Note 7: Dynamic quiescent current is higher due to the gate charge being delivered at the switching frequency. Revision: 1.0 5/17

6 Typical Performance Characteristics Efficiency vs Output Current Efficiency vs Output Current Efficiency vs Output Current Efficiency vs Output Current Output Voltage vs Load Current Reference voltage vs Temperature 2.00V O u t p u t V o lt a g e ( V ) 1.95V 1.90V 1.85V 1.80V 1.75V 1.70V Vin=3.6V Vin=5.5V 1.65V 1.60V 0mA 200mA 400mA 600mA 800mA 1000mA 1200mA 1400mA Load Current (ma) Revision: 1.0 6/17

7 Typical Performance Characteristics (cont.) RDS(ON) vs Temperature RDS(ON) vs Input Voltage Dynamic Supply Current vs Temperature Dynamic Supply Current vs Supply Voltage Oscillator Frequency vs Temperature Oscillator Frequency vs Supply Voltage Revision: 1.0 7/17

8 Typical Performance Characteristics (cont.) Discontinuous Operation Load Step Revision: 1.0 8/17

9 Functional Block Diagram FIG.2. Functional Block Diagram of Revision: 1.0 9/17

10 Application Information General Description The typical application circuit of adjustable version is shown in Fig.1. Fixed voltage version is shown below: EML 3409 VIN IN1 SW1 2.2uH VOUT 1 Cin 4.7uF EN EN1 OUT 1 Cout 10 uf IN2 SW 2 2.2uH VOUT 2 Cin 4.7uF EN EN2 OUT 2 Cout 10 uf GND Inductor Selection Basically, inductor ripple current and core saturation are two factors considered to decide the Inductor value. 1 ΔI = V 1 L f L OUT V OUT V IN Eq. 1 The Eq. 1 shows the inductor ripple current is a function of frequency, inductance, Vin and Vout. It is recommended to set ripple current to 40% of max. load current. A low ESR inductor is preferred. CIN and COUT Selection A low ESR input capacitor can prevent large voltage transients at VIN. The RMS current of input capacitor is required larger than IRMS calculated by: I RMS I OMAX V OUT ( V V ) V IN IN OUT Eq. 2 ESR is an important parameter to select COUT. The output ripple VOUT is determined by: ΔV ΔI OUT L 1 ESR + 8 f C OUT Eq. 3 Revision: /17

11 Higher values, lower cost ceramic capacitors are now available in smaller sizes. These ceramic capacitors have high ripple currents, high voltage ratings and low ESR that make them ideal for switching regulator applications. Optimize very low output ripple and small circuit size is doable from Cout selection since Cout does not affect the internal control loop stability. It is recommended to use the X5R or X7R which have the best temperature and voltage characteristics of all the ceramics for a given value and size. Output Voltage ( adjustable) In the adjustable version, the output voltage can be determined by: V = 0. 6 V OUT 1 + R 2 R 1 Eq. 4 Thermal Considerations Although thermal shutdown is build-in in that protect the device from thermal damage, the total power dissipation that can sustain should be base on the package thermal capability. The formula to ensure the safe operation is shown in Note 5. To avoid the from exceeding the maximum junction temperature, the user will need to do some thermal analysis. Output Voltage Ripple When V IN Closes To V OUT goes into LDO mode when input voltage closes to output voltage. The transition from PWM mode to LDO mode is smooth. Bottom diagram shows the relationship of output voltage ripple versus input voltage when output voltage is 3.3V and provides 200mA load current. VOUT Ripple When VIN Closes To VOUT Revision: /17

12 Design Example Assume the is used in a single lithium-ion battery-powered application. The VIN range will be about 2.7V to 4.2V. Output voltage is 1.8V. With this information we can calculate L using equation: L = 1 f ΔI L V OUT 1 V OUT V IN Substituting VOUT = 1.8V, VIN = 4.2V, IL = 240mA and f = 1.5MHz in eq. 1 gives: = 1.8V 1.8V L 1 = 2.86μH 1.5MHz 240mA 4.2V A 2.2μH inductor could be chose with this application. A greater inductor with less equivalent series resistance makes best efficiency. CIN will require an RMS current rating of at least ILOAD(MAX)/2 and low ESR. In most cases, a ceramic capacitor will satisfy this requirement. Revision: /17

13 Typical Schematic for PCB Layout Note. R2, R6 and C4, C5 are preserved passive component locations for testing purpose. Please remove it during normal application. Guidelines for PCB Layout To ensure proper operation of the, please note the following PCB layout guidelines: 1. The GND trace, the SW trace and the VIN trace should be kept short, direct and wide. 2. FB pin must be connected directly to the feedback resistors. Resistive divider R1/R2 must be connected and parallel to the output capacitor COUT. 3. The Input capacitor CIN must be connected to pin VIN as closely as possible. 4. Keep SW node away from the sensitive FB node since this node is with high frequency and voltage swing. 5. Keep the ( ) plates of CIN and COUT as close as possible. Revision: /17

14 Package Outline Drawing TDFN-10 (3x3mm) Symbol Dimension in mm Exposed pad Min Max Dimension in mm A Min Max A D A E b D E e L BSC 0.50 Revision: /17

15 Old Order, Marking & Packing Information Package Vout1 Vout2 Product ID. Marking Packing TDFN-10 Adj. Adj. -00FF10NRR Tape & Reel 5Kpcs Revision: /17

16 Revision History Revision Date Description Original Revision: /17

17 Important Notice All rights reserved. No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this document are believed to be accurate at the time of publication. ESMT assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of ESMT or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. ESMT's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Revision: /17