Dual High-Efficiency PWM Step-Down DC-DC Converter

Transcription

1 D8245 Dual High-Efficiency PWM Step-Down DC-DC Converter General Description The is a dual high-efficiency Pulse-Width- Modulated (PWM) step-down DC-DC converter. It is capable of delivering 1A output current over a wide input voltage range from 2.5V to 5.5V, the is ideally suited for portable electronic devices that are powered from 1-cell Li-ion battery or from other power sources within the range such as cellular phones, PDAs and other handheld devices. Two operational modes are available: PWM/Low- Dropout auto-switch and shutdown modes. Internal synchronous rectifier with low RDS(ON) dramatically reduces conduction loss at PWM mode. No external Schottky diode is required in practical application. The enters Low-Dropout mode when normal PWM cannot provide regulated output voltage by continuously turning on the upper PMOS. The enter shutdown mode and consumes less than 0.1µA when EN pin is pulled low. The switching ripple is easily smoothed-out by small package filtering elements due to a fixed operation frequency of 1.5MHz. This along with small TDFN-12L 3x3 package provides small PCB area application. Other features include soft start, lower internal reference voltage with 3% accuracy, over temperature protection, and over current protection. Ordering Information - Output Voltage Adjustable Applications Mobile Phones Taping R: Tape and Reel Package FEC:TDFN-12L (3x3) Voltage Code AD Personal Information Appliances Wireless and DSL Modems MP3 Players Portable Instruments Features +2.5V to +5.5V Input Range Adjustable Output Voltage 1A Output Current 95% Efficiency No Schottky Diode Required 50μA Quiescent Current per Channel 1.5MHz Fixed-Frequency PWM Operation Small 12-Lead TDFN Package RoHS Compliant and Green Marking Information For marking information, please contact our sales representative directly or through distributor around your location. Jan V0.9

2 Typical Application Circuit (Adjustable Operation) TDFN-12L Package Pin Configurations (Top View) VIN EN2 SW NC2 GND 3 GND 10 FB2 FB1 4 9 GND NC1 5 8 SW1 EN VIN1 TDFN-12L Package Jan V0.9

3 Absolute Maximum Ratings (Note 1) Recommended Operating Conditions Supply Voltage V IN 6V Input Voltage V IN 2.5V to 5.5V Power Dissipation, P T A =25 C EN Input Voltage 0V to V IN TDFN-12L 2.083W Junction Temperature -40 C to 125 C Thermal Resistance, θja Ambient Operating Temperature -40 C to 85 C TDFN-12L 48 C/W Lead Temperature 260 C Storage Temperature -65 C to 150 C ESD Susceptibility HBM (Human Body Mode) 2kV MM (Machine Mode) 200V Pin Description Name Description VIN2 Power Input of Channel 2. SW2 Pin for Switching of Channel 2. GND Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. FB1 Feedback of Channel 1. NC1, NC2 EN1 No Connection or Connect to VIN. Chip Enable of Channel 1 (Active High). VEN1 VIN1. VIN1 Power Input of Channel 1. SW1 Pin for Switching of Channel 1. FB2 Feedback of Channel 2. EN2 Chip Enable of Channel 2 (Active High). VEN2 VIN2. Jan V0.9

4 Function Block Diagram Jan V0.9

5 Electrical Characteristics (VIN = 3.6V, VOUT = 2.5V, VREF = 0.6V, L = 2.2uH, CIN = 4.7uF, COUT = 10uF, TA = 25 C, IMAX= 1A unless otherwise specified) Parameters Symbol Test Condition Min Typ Max Units Channel 1 and Channel 2 Input Voltage Range V IN V Under Voltage Lock Out threshold UVLO V Quiescent Current I Q I OUT=0mA, V FB=V REF+5% µa Shutdown Current I SHDN EN=GND µa Reference Voltage V REF V Adjustable Output Voltage Range V OUT V REF -- V IN- V V Output Voltage Accuracy V OUT V IN=V OUT+ V to 5.5V; 0A<I OUT<1A % FB Input Current I FB VFB=V IN na R DS(ON) of P-MOSFET R DS(ON)_P I OUT=200mA R DS(ON) of N-MOSFET R DS(ON)_N I OUT=200mA V IN=2.5V V IN=3.6V V IN=2.5V V IN=3.6V Ω Ω P-Channel Current Limit I LIM_P V IN=2.5V to 5.5V A EN High-Level Input Voltage V EN_H V IN=2.5V to 5.5V V IN V EN Low-Level Input Voltage V EN-L V IN=2.5V to 5.5V Oscillator Frequency f OSC V IN=3.6V, I OUT=100mA MHz Thermal Shutdown Temperature T SD C Maximum Duty Cycle % SW Leakage Current I SW V IN=3.6V, V SW=0V or V SW=3.6V µa Jan V0.9

6 Typical Performance Characteristics (Unless otherwise specified T A =25 ). Efficiency vs. Output Current Efficiency vs. Output Current Efficiency 100% 90% 80% 70% 60% VIN = 5.0V VIN = 4.2V Efficiency 100% 90% 80% 70% 60% VIN = 5.0V VIN = 3.3V VIN = 2.5V 50% 50% V EN = V IN, V OUT = 3.3V, L = 2.2µH 40% V EN = V IN, V OUT = 1.2V, L = 2.2µH 40% Output Current (ma) Output Current (ma) Feedback Voltage vs. Input Voltage Feedback Voltage vs. Temperature Feedback Voltage (V) Feedback Voltage (V) V 0.57 EN = V IN, L = 2.2µH, I OUT=500mA V EN = V IN = 5.0V, I OUT = 500mA Input Voltage (V) Temperature ( ) Shutdown Current vs. Input Voltage Shutdown Current vs. Temperature Shutdown Current (µa) V EN = GND Shutdown Current (µa) V EN = GND Input Voltage (V) Temperature ( ) Jan V0.9

7 Enable Voltage Threshold (V) Enable Voltage vs. Input Voltage 0.9 ON 0.8 OFF Input Voltage (V) ) RDS (ON) (Ω 0.60 Isw = 0.1A 0.50 Isw = 0.5A Isw = 1.0A 0.40 R DS (ON) vs. Input Voltage V IN = V EN, V FB = 0V Input Voltage (V) 2.9 Current Limit vs. Input Voltage 2.20 Frequency vs. Input Voltage Current Limit (A) Frequency (MHz) V OUT = 1.2V, L=2.2µH, I OUT = 500mA Input Voltage (V) Input Voltage (V) Under Voltage Lockout V IN (DC) (1.00V/Div) V SW (DC) (1.00V/Div) V IN = V EN, V OUT = 1.2V, I OUT = 5mA, L = 2.2µH Time (1.00ms/Div) Jan V0.9

8 Load Transient Response Load Transient Response V OUT (AC) (50.0mV/Div) V OUT (AC) (50.0mV/Div) I OUT (DC) (200mA/Div) V IN = 3.6V, V OUT = 1.2V, L = 2.2µH, I OUT = 50mA to 500mA I OUT (DC) (500mA/Div) V IN = 3.6V, V OUT = 1.2V, L = 2.2µH, I OUT = 50mA to 1000mA Time (200µs/Div) Time (200µs/Div) Load Transient Response Load Transient Response V OUT (AC) (50.0mV/Div) V OUT (AC) (50.0mV/Div) I OUT (DC) (200mA/Div) V IN = 5.0V, V OUT = 1.2V, L = 2.2µH, I OUT = 50mA to 500mA I OUT (DC) (500mA/Div) V IN = 5.0V, V OUT = 1.2V, L = 2.2µH, I OUT = 50mA to 1000mA Time (200µs/Div) Time (200µs/Div) Steady State Output Ripple Steady State Output Ripple V IN (DC) (2.00V/Div) V IN (DC) (2.00V/Div) V OUT (AC) (10.0mV/Div) V OUT (AC) (10.0mV/Div) V IN = 3.6V, V OUT = 1.2V, L = 2.2µH, I OUT = 1000mA V IN = 5.0V, V OUT = 1.2V, L = 2.2µH, I OUT = 1000mA Time (400ns/Div) Time (400ns/Div) Jan V0.9

9 Functional Description The basic application circuit is shown in Typical Application Circuit. External component selection is determined by the maximum load current and begins with the selection of the inductor value and operating frequency followed by CIN and COUT. Inductor Selection For a given input and output voltage, the inductor value and operating frequency determine the ripple current. The ripple current IL increases with higher VIN and decreases with higher inductance. VOUT V IL = 1 f L V OUT IN Having a lower ripple current reduces the ESR losses in the output capacitors and the output voltage ripple. Highest efficiency operation is achieved at low frequency with small ripple current. This, however, requires a large inductor. A reasonable starting point for selecting the ripple current is IL = 0.4(IMAX). The largest ripple current occurs at the highest VIN. To guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation: L = V f I OUT L( MAX ) V 1 VIN Inductor Core Selection OUT ( MAX ) Once the value for L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite or permalloy cores. Actual core loss is independent of core size for a fixed inductor value but it is very dependent on the inductance selected. As the inductance increases, core losses decrease. However, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates hard, which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Different core materials and shapes will change the size/current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and don't radiate energy but generally cost more than powdered iron core inductors with similar characteristics. The choice of which style inductor to use mainly depend on the price vs. size requirements and any radiated field/emi requirements. CIN and COUT Selection The input capacitance, CIN, is needed to filter the trapezoidal current at the source of the top MOSFET. To prevent large ripple voltage, a low ESR input capacitor sized for the maximum RMS current should be used. RMS current is given by : I RMS = I V V V V OUT IN OUT ( MAX ) IN OUT This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further de-rate the capacitor, or choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. The selection of COUT is determined by the effective 1 Jan V0.9

10 series resistance (ESR) that is required to minimize voltage ripple and load step transients, as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. Loop stability can be checked by viewing the load transient response as described in a later section. The output ripple, VOUT, is determined by: V OUT I L 1 ESR + 8 fc OUT The output ripple is highest at maximum input voltage since IL increases with input voltage. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Special polymer capacitors offer very low ESR but have lower capacitance density than other types. Tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR but can be used in cost sensitive applications provided that consideration is given to ripple current ratings and long-term reliability. Ceramic capacitors have excellent low ESR characteristics but can have a high voltage coefficient and audible piezoelectric effects. The high Q of ceramic capacitors with trace inductance can also lead to significant ringing. Using Ceramic Input and Output Capacitors Higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. However, care must be taken when these capacitors are used at the input and output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, VIN. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VIN large enough to damage the part. Output Voltage Programming The resistive divider allows the FB pin to sense a fraction of the output voltage as shown in Figure 3. For adjustable voltage mode, the output voltage is set by an external resistive divider according to the following equation : VOUT = VREF x (1+ R1/R2) Where VREF is the internal reference voltage (0.6V typical) PSM Mode As the output current drops, the enters discontinuous conduction mode (DCM). If a very light load current only requires the switch on time to be less than 1/10F OSC (minimum on time), the IC enters pulseskipping mode. In this mode, the device prevents the switch from turning on for one or more switching cycles to prevent the output voltage from rising above the regulated voltage. According this, when enters in PSM mode will get higher efficiency than PWM mode. Compared to normal PWM operation, the output ripple in pulse- skipping will be larger. Efficiency Considerations The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It Jan V0.9

11 is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Efficiency can be expressed as: Efficiency = 100% (L1+ L2+ L3+...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses: VIN quiescent current and I2R losses. The VIN quiescent current loss dominates the efficiency loss at very low load currents whereas the I2R loss dominates the efficiency loss at medium to high load currents. In a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence. 1.The VIN quiescent current appears due to two components : the DC bias current and the gate charge currents. The gate charge current results from switching the gate capacitance of the internal power MOSFET switches. Each time the gate is switched from high to low to high again, a packet of charge Q moves from VIN to ground. The resulting Q/ t is the current out of VIN that is typically larger than the DC bias current. In continuous mode, IGATECHG = f(qt + QB) where QT and QB are the gate charges of the internal top and bottom switches. Both the DC bias and gate charge losses are proportional to VIN and thus their effects will be more pronounced at higher supply voltages. 2. I2R losses are calculated from the resistances of the internal switches, RSW and external inductor RL. In continuous mode the average output current flowing through inductor L is chopped between the main switch and the synchronous switch. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) is shown as follows : RSW = RDS(ON)TOP x DC + RDS(ON)BOT x (1 DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus, to obtain I2R losses, simply add RSW to RL and multiply the result by the square of the average output current. Other losses including CIN and COUT ESR dissipative losses and inductor core losses generally account for less than 2% of the total loss. Thermal Considerations The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula : PD(MAX) = ( TJ(MAX) TA ) / θja Where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature and the θja is the junction to ambient thermal resistance. For recommended operating conditions specification of DC/DC converter, where TJ(MAX) is the maximum junction temperature of the die and TA is the ambient temperature. The junction to ambient thermal resistance θja is layout dependent. For TDFN-12L 3x3 packages, the thermal resistance θja is 48 C/W on the standard JEDEC 51-7 four-layers thermal test board. The maximum power dissipation at TA = 25 C can be calculated by following formula : PD(MAX) = (125 C 25 C) / (48 C/W) = 2.083W for TDFN-12L 3x3 packages The maximum power dissipation depends on operating ambient temperature for fixed TJ(MAX) and thermal resistance θja. For packages, the Figure 4 of derating curves allows the designer to see the effect of Jan V0.9

12 rising ambient temperature on the maximum power allowed. 2.5 Maximum Power Dissipation Power Dissipation (W) Ambient Temperature ( C) Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ILOAD (ESR), where ESR is the effective series resistance of COUT. ILOAD also begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. Jan V0.9

13 Layout Considerations Follow the PCB layout guidelines for optimal performance of. For the main current paths, keep their traces short and wide. Put the input capacitor as close as possible to the device pins (VIN and GND). SW node is with high frequency voltage swing and should be kept small area. Keep analog components away from SW node to prevent stray capacitive noise pick-up. Connect feedback network behind the output capacitors. Keep the loop area small. Place the feedback components near the. Connect all analog grounds to a command node and then connect the command node to the power ground behind the output capacitors. C OUT2 C11 SW1,2 should be connected to Inductor by wide and short trace, keep sensitive compontents away from this trace. C IN2 L2 R12 R11 VIN2 SW2 GND FB1 NC1 EN EN2 NC FB2 GND 4 9 GND 6 7 FB1,2 node copper area should be minimized and keep far away from noise sources (SW1,2 and VIN1,2). SW1 VIN1 R21 R22 L1 C IN1 The resistor divider, R11 R12 R21 R22, must be connected between the (+) plate of C OUT1,2 and a ground line terminated near GND. C21 C OUT1 C OUT1,2 must be near. NC1,2 pin no connect or connect to GND. The exposed pad and GND should be connected to a strong ground plane for heat sinking and noise prevention. C IN1,2 must be placed between VIN and GND as closer as Possible. TDFN-12L Package Jan V0.9

14 Packaging TDFN-12L (3mm x 3mm) SYMBOLS DIMENSIONS IN MILLIMETERS DIMENSIONS IN INCH MIN NOM MAX MIN NOM MAX A A A REF REF --- A b C REF D D E E L P S 0.16 min 0.006min --- Jan V0.9

15 Footprints TDFN-12L (3mm x 3mm) Footprint Dimension (mm) Package Number of PIN Tolerance P A B C D Sx Sy M TDFN-12L 3x ±0.030 Jan V0.9