Chip Scle Pckged Digitl Therml Orienttion Sensing Accelerometer MXC6226XC Document Version D Pge 1 of 13
Fetures Generl Description Fully Integrted Therml Accelerometer X/Y Axis, 8 bit, Accelertion A/D Output (± 2g) Chip Scle Pckge (1.17x1.70x1.0mm) 4-position Orienttion Detection Shke Detection with Interrupt Progrmmble Shke Threshold Shke Direction Detection I 2 C Interfce Power Down Mode Shock Survivl Greter thn 50,000 g Operting Supply Voltge from 2.5V to 5.5V with 1.8V comptible IO Produces no Mechnicl Sounds ("click") The MEMSIC Digitl Therml Orienttion Sensor is the world's first fully-integrted orienttion sensor lso with chip scle pckge. Its opertion is bsed on our ptented MEMS-therml technology nd is built using stndrd 0.18um CMOS process. DTOS contins no moving prts (such s bll) nd thus elimintes field-relibility nd repetbility issues ssocited with competitive products. It lso elimintes the "click" sounds typiclly herd in bll bsed orienttion sensors. Shock survivl is greter thn 50,000g. DTOS detects four orienttions, shke nd shke direction. In ddition, it provides X/Y xis ccelertion signls with very low 0g offset. An I 2 C interfce is used to communicte with this device nd n interrupt pin (INT) is provided for shke nd orienttion. The DTOS lso hs power down enbled through the I 2 C interfce. Functionl Block Digrm Applictions Consumer: Cell Phones Digitl Still Cmers (DSC) Digitl Video Cmers (DVC) LCD TV Toys MP3, MP4 Plyers Household Sfety: Fn Heters Hlogen Lmps Iron Cooling Fns Figure 1 The DTOS is pckged in Chip Scle Pckge (1.17x1.70x1.0mm), the product is RoHS comptible nd opertes over -20~70 temperture rnge. Document Version D Pge 2 of 13
Pin Description: CSP Pckge Pin Nme Description 1 I 2 C SCL This pin is the seril clock line for the I 2 C interfce. Since the MXC6255XC only opertes s slve device, this pin is lwys n input. 2 NC During norml opertion, this pin must be left floting. 3 GND This is the ground pin for the MXC6255XC. 4 INT This pin is the MXC6255XC interrupt output. The logic level on this pin reflects the stte of the INT bit in the STATUS register. INT is set when the orienttion differs from the lst orienttion red by the processor, or shke event is detected. INT is clered upon reding of the STATUS register. Figure 2 Top View (smll circle indicte pin 1) 5 I 2 C SDA This pin is the seril dt line for the I 2 C interfce. It is n I/O pin tht functions s n input during write, nd n output during red from the MXC6255XC. 6 VDD This is the power supply input. The DC voltge should be between 2.5 nd 5.5 volts. Absolute Mximum Rtings* Supply Voltge (V DD )...-0.5 V to +7.0V Storge Temperture..-40 C to +150 C Accelertion..50,000 g *Stresses bove those listed under Absolute Mximum Rtings my cuse permnent dmge to the device. This is stress rting only; the functionl opertion of the device t these or ny other conditions bove those indicted in the opertionl sections of this specifiction is not implied. Exposure to bsolute mximum rting conditions for extended periods my ffect device relibility. Electricl Specifictions 1 Prmeter (Units) Conditions Minimum Typicl Mximum Operting Voltge Rnge (V) 2.5 5.5 VIO(I 2 C interfce)(v) 1.62 1.8 VDD Figure 3 Side View In power-up mode 1.2 Supply Current (ma) In power-down mode 0.0004 0.001 Turn-On Time (ms) 2 300 500 Turn-off Time (ms) 0.5 Operting Temperture Rnge ( ) -20 +70 VDD Rise Time (ms) 3 10 e t o Notes: 1 All specifictions re t 3V nd room temperture unless otherwise noted. 2 Time to obtin vlid dt fter existing power-down mode. 3 Mximum llowble power supply rise time from 0.25V to 2.5V (minimum). Slower VDD rise time my cuse erroneous dt retrievl from OTP memory t power-up. Sensor Chrcteristics 1 Prmeter (Units) Conditions Minimum Typicl Mximum Mesurement Rnge (g) X/Y Axis ± 2.0 Alignment Error ( ) X/Y Axis ± 1.0 ± 2.0 Sensitivity Error (%) X/Y Axis ± 5.0 Sensitivity (LSB/g) X/Y Axis 64 Figure 4 Bottom View Sensitivity Drift Over Temperture (%) Delt from 25 (-20-70 ) ± 15 Zero g Offset Bis Level (mg) X/Y Axis (25 ) ± 50 Zero g Offset Temperture coefficient (mg/ ) X/Y Axis (-20-70 ) 0.6 3dB Signl Bndwidth (Hz) 10 Notes: 1 All specifictions re t 3V nd room temperture unless otherwise noted. Document Version D Pge 3 of 13
tbf tsu;p P S Digitl Prmeters Symbol Prmeter (Units) Minimum Typicl Mximum V IH High Level Input Voltge (Volts) 0.7*VIO V IL Low Level Input Voltge (Volts) 0.3*VIO V HYS Hysteresis of Schmitt Trigger Input (Volts) 0.1 I IL Input Lekge, All Inputs (ua) -10 10 V OH High Level Output Voltge (Volts) 0.8*VIO V OL Low Level Output Voltge (Volts) 0.2*VIO tsu;d thigh tsu;s Sr Digitl Switching Chrcteristics Symbol Prmeter (Units) Minimum Typicl Mximum top Operting Vlid Time (ms) 1 20 fscl SCK Clock Frequency (khz) 0 400 tr Rise Time (us) 0.3 tlow tr thd;d thd;s tf Fll Time (us) 0.3 tlow SCL Low Time (us) 1.3 thigh SCL High Time (us) 0.6 thd;d Dt Hold Time (us) 0 0.9 tsu;d Dt Set-Up Time (us) 0.1 S tsu;s Strt Set-Up Time (us) 0.6 thd;s Strt Hold Time (us) 0.6 tsu;p Stop Set-Up Time (us) 0.6 tbf Bus Free Time Between Strt nd Stop (us) 1.3 Note: 1. Mster is recommended not to tlk with the device within 20mS fter power up.2. It is not recommended to keep both SCL nd SDA signls low for over 10ms. VDD SDA SCL top tf Figure 5 Document Version D Pge 4 of 13
Circuit Schemtics Note: R1 nd R2 re pull-up resistors, the vlue cn be determined by customer ccording to the requirement of the host device, nd the recommendtion vlue is 2.7KOhm. INT does not need ny pull-up/pull-down resistor If INT is not used, keep it disconnected (don't pull up or pull down) Leve NC pin s no connection. Figure 6 Lnding Pttern Note: The device should be put into the center re of the PCB, edge re is not recommended. The device routing should be symmetric. Solder msk define on PCB is preferred. The recommended opening size of soldering re of PCB is 230um. The stencil opening size is sme s the foot print lnd pttern. The thickness of the stencil cn be 0.1mm~0.12mm Figure 7 Document Version D Pge 5 of 13
Reflow Profile Note: Reflow is limited to two cycles. If second reflow cycle is implemented, it should be pplied only fter device hs cooled down to 25 (room temperture) Figure 8 is the reflow profile for Pb free process The pek temperture on the sensor surfce must be limited to under 260 for 10 seconds. Follow solder pste supplier s recommendtions for the best SMT qulity. Mnul Soldering Figure 8 Reflow Profile Low Temperture Glss Note: When soldering mnully or repiring vi soldering iron for Chip Scle pckged device, the time must be limited to less thn 10 seconds nd the temperture must not exceed 275. If het gun is used, the time must be limited to less thn 10seconds nd the temperture must not exceed 270 Avoid bending the PCB fter the sensor ssembly Figure 9 Chip Scle Pckge Document Version D Pge 6 of 13
6 5 4 1 2 3 Powerful Sensing Solutions for Better Life Orienttion (Bottom View) Stte Bits OR [1,0] Orienttion/Shke Chrcteristics 6 5 4 t e o 1 2 3 01 Output stte response to orienttion If the sensor is rotted pst the 45 degree threshold, the orienttion bits will chnge only if the sensor stys in the sme stte for defined period of time. If the sensor crosses bck before this time period, the orienttion bits remin unchnged. This is to prevent dithering of the orienttion stte. Four user progrmmble hysteresis time periods re vilble: 160, 320, 640 nd 1280ms. e t o 00 4 3 2 1 o t e 5 6 11 1 2 3 Figure 11 Figure 12 t e o 6 5 4 10 MXC6226XC cn detect orienttion chnges with up to 60 degrees of off-xis tilt Shke Detection Shke nd shke direction re orthogonl to screen orienttion. An interrupt pin (INT) is set high nd must be clered by the MCU vi the I 2 C interfce. Four user progrmmble thresholds re vilble: 0.5g, 1g, 1.5g nd 2g. Grvity Direction Bottom View Sme Plne e t o θ + Figure 10 Figure 13 Document Version D Pge 7 of 13
I 2 C Interfce A slve mode I 2 C interfce, cpble of operting in stndrd or fst mode, is implemented on the MXC6226XC. The interfce uses seril dt line (SDA) nd seril clock line (SCL) to chieve bi-directionl communiction between mster nd slve devices. A mster (typiclly microprocessor) initites ll dt trnsfers to nd from the device, nd genertes the SCL clock tht synchronizes the dt trnsfer. The SDA pin on the MXC6226XC opertes both s n input nd n open drin output. Since the MXC6226XC only opertes s slve device, the SCL pin is lwys n input. There re externl pull-up resistors on the I 2 C bus lines. Devices tht drive the I 2 C bus lines do so through open-drin n-chnnel driver trnsistors, creting wired NOR type rrngement. Dt on SDA is only llowed to chnge when SCL is low. A high to low trnsition on SDA when SCL is high is indictive of START condition, wheres low to high trnsition on SDA when SCL is high is indictive of STOP condition. When the interfce is not busy, both SCL nd SDA re high. A dt trnsmission is initited by the mster pulling SDA low while SCL is high, generting START condition. The dt trnsmission occurs serilly in 8 bit bytes, with the MSB trnsmitted first. During ech byte of trnsmitted dt, the mster will generte 9 clock pulses. The first 8 clock pulses re used to clock the dt, the 9th clock pulse is for the cknowledge bit. After the 8 bits of dt re clocked in, the trnsmitting device releses SDA, nd the receiving device pulls it down so tht it is stble low during the entire 9th clock pulse. By doing this, the receiving device "cknowledges" tht it hs received the trnsmitted byte. If the slve receiver does not generte n cknowledge, then the mster device cn generte STOP condition nd bort the trnsfer. If the mster is the receiver in dt trnsfer, then it must signl the end of dt to the slve by not generting n cknowledge on the lst byte tht ws clocked out of the slve. The slve must relese SDA to llow the mster to generte STOP or repeted START condition. The mster initites dt trnsfer by generting START condition. After dt trnsmission is complete, the mster my terminte the dt trnsfer by generting STOP condition. The bus is considered to be free gin certin time fter the STOP condition. Alterntively, the mster cn keep the bus busy by generting repeted START condition insted of STOP condition. This repeted START condition is functionlly identicl to START condition tht follows STOP. Ech device tht sits on the I 2 C bus hs unique 7 bit ddress. The first byte trnsmitted by the mster following START is used to ddress the slve device. The first 7 bits contin the ddress of the slve device, nd the 8th bit is the R/W* bit (red = 1, write = 0; the sterisk indictes ctive low, nd is used insted of br). If the trnsmitted ddress mtches up to tht of the MXC6226XC, then the MXC6226XC will cknowledge receipt of the ddress, nd prepre to receive or send dt. If the mster is writing to the MXC6226XC, then the next byte tht the MXC6226XC receives, following the ddress byte, is loded into the ddress counter internl to the MXC6226XC. The contents of the ddress counter indicte which register on the MXC6226XC is being ccessed. If the mster now wnts to write dt to the MXC6226XC, it just continues to send 8-bit bytes. Ech byte of dt is ltched into the register on the MXC6226XC tht the ddress counter points to. The ddress counter is incremented fter the trnsmission of ech byte. If the mster wnts to red dt from the MXC6226XC, it first needs to write the ddress of the register it wnts to begin reding dt from to the MXC6226XC ddress counter. It does this by generting START, followed by the ddress byte contining the MXC6226XC ddress, with R/W* = 0. The next trnsmitted byte is then loded into the MXC6226XC ddress counter. Then, the mster repets the START condition nd re-trnsmits the MXC6226XC ddress, but this time with the R/W* bit set to 1. During the next trnsmission period, byte of dt from the MXC6226XC register tht is ddressed by the contents of the ddress counter will be trnsmitted from the MXC6226XC to the mster. As in the cse of the mster writing to the Document Version D Pge 8 of 13
MXC6226XC, the contents of the ddress counter will be incremented fter the trnsmission of ech byte. The protocol for multiple byte reds nd writes between mster nd slve device is depicted in Figure 14. Figure 14 The I 2 C ddress for MXC6226XC is set s:06h Document Version D Pge 9 of 13
User Register Summry Address Nme Definition Access Defult $00 XOUT 8-bit x-xis ccelertion output red 00000000 $01 YOUT 8-bit y-xis ccelertion output red 00000000 $02 STATUS orienttion nd shke sttus red 00000000 $04 DETECTION Power down, orienttion nd shke detection prmeters write 00000000 $08 CHIP_ID Chip ID of MXC6226XC red xx000110 The registers vilble to the user on the MXC6226XC re summrized in the tble bove. Ech register contins 8 bits. $00: XOUT 8-bit x-xis ccelertion output (red only) D7 D6 D5 D4 D3 D2 D1 D0 XOUT[7] XOUT[6] XOUT[5] XOUT[4] XOUT[3] XOUT[2] XOUT[1] XOUT[0] 8-bit x-xis ccelertion output. Dt in 2's complement formt with rnge of -128 to +127. $01: YOUT 8-bit y-xis ccelertion output (red only) D7 D6 D5 D4 D3 D2 D1 D0 YOUT[7] YOUT[6] YOUT[5] YOUT[4] YOUT[3] YOUT[2] YOUT[1] YOUT[0] 8-bit y-xis ccelertion output. Dt in 2's complement formt with rnge of -128 to +127. $02: STATUS orienttion nd shke sttus register (red only) D7 D6 D5 D4 D3 D2 D1 D0 INT SH[1] SH[0] TILT ORI[1] ORI[0] OR[1] OR[0] OR[1:0] is 2-bit indiction of the device orienttion, ccording to the following scheme (lso shown visully in Figure 10): OR[1:0] = 00 device is verticl in upright orienttion; 01 device is rotted 90 degrees clockwise; 10 device is verticl in inverted orienttion; 11 device is rotted 90 degrees counterclockwise. The bits OR[1:0] re indictive of "long-term" orienttion. The orienttion is determined by mesuring the signs of the quntities x y, nd x + y, s shown in Figure 12. The orienttion mesurement is ignored for ny smples in which the mgnitudes of x nd y re both less thn 3/8 g (for exmple, during free-fll event). In order for new vlue of OR[1:0] to be written to the STATUS register, vlid mesurement of the new orienttion must be mesured consecutive number of times determined by the setting of bits ORC[1:0] in the DETECTION register. This provides low-pss filtering nd hysteresis effect tht keeps disply from flickering ner orienttion boundries. ORI[1:0] is the instntneous device orienttion. It follows the sme scheme s OR[1:0], except tht it is updted every time vlid orienttion mesurement is mde, not subject to the sme low-pss filtering s OR[1:0]. TILT is n indiction of whether there is enough ccelertion signl strength to mke vlid orienttion mesurement. If TILT = 0, the orienttion mesurement is vlid, if TILT = 1, then the orienttion mesurement is invlid. TILT is updted every mesurement cycle. Document Version D Pge 10 of 13
SH[1:0] indicte whether shke event hs tken plce, nd if so, its direction. Shke cn only be detected in direction perpendiculr to the verticl orienttion of the device. When n ccelertion perpendiculr to the device orienttion (x for OR[1:0] = 01 or 11; y for OR[1:0] = 00 or 10) is sensed tht hs mgnitude greter thn the vlue set by bits SHTH[1:0] in the DETECTION register, then shke detection begins. For shke event to be written to SH[1:0], the perpendiculr ccelertion must gin exceed the mgnitude set by SHTH[1:0] but with the opposite sign (if bit SHM = 0 in the DETECTION register), or just reverse its sign (if bit SHM = 1 in the DETECTION register). The bove mentioned second ccelertion events must occur within certin mount of time, set by SHC[1:0] in the DETECTION register, of the originl breking of the threshold. If shke is determined to hve occurred, then the direction of the shke cn be determined by the signs of the ccelertions. The shke sttus is indicted s shown in the following tble: SH[1] SH[0] Comment 0 0 no shke event 0 1 shke left 1 0 shke right 1 1 undefined INT is the interrupt bit. Setting this bit high will cuse the INT pin to output high level. The INT bit will be set whenever either (1) The orienttion, s indicted by bits OR[1:0] chnges, or (2) A shke event occurs. The microprocessor cn then service the interrupt by reding the STATUS register. Once shke event occurs, no new shke events will be recorded until the interrupt hs been serviced, lthough the orienttion bits will continue to be updted. The INT bit is clered by reding the STATUS register. $04: DETECTION orienttion nd shke detection prmeters (write only) D7 D6 D5 D4 D3 D2 D1 D0 PD SHM SHTH[1] SHTH[0] SHC[1] SHC[0] ORC[1] ORC[0] PD = 1 powers down the MXC6226XC to non-functionl low power stte with mximum current drin of 1 ua. ORC[1:0] sets the orienttion hysteresis time period, which is the time period of consecutive vlid new instntneous orienttion mesurements tht must be mde before new orienttion vlue is written into bits OR[1:0] in the STATUS register. The "long-term" orienttion chnge is set by ORC[1:0] s follows: 00 160ms, 01 320ms, 10 640ms, 11 1280ms nominlly. SHC[1:0] sets the shke events time window, which determines the time window llowed between the first shke event (perpendiculr ccelertion exceeding the threshold set by SHTH[1:0]) nd the second shke event (ccelertion breking the threshold with opposite sign, SHM = 0, or just reversing sign, SHM = 1). The time window is set by SHC[1:0] s follows: 00 80ms, 01 160ms, 10 320ms, 11 640ms nominlly. SHTH[1:0] sets the shke threshold tht the perpendiculr ccelertion must exceed to trigger the first shke event. The settings for SHTH[1:0] re: 00-0.5 g, 01 1.0 g, 10 1.5 g, 11 2.0 g. SHM is the shke mode bit. If SHM = 0, then for shke to be detected, nd written to SH[1:0] in the STATUS register, the second shke event must brek the threshold set by SHTH[1:0] with the opposite sign of the first shke event, within the time window set by SHC[1:0]. If SHM = 1, then the second shke event must just hve the opposite sign of the first shke event within the time window set by SHC[1:0]. Document Version D Pge 11 of 13
$08 (6LSB),: CHIP_ID Chip ID of MXC6226XC (red only) D7 D6 D5 D4 D3 D2 D1 D0 ID[7] ID[6] ID[5] ID[4] ID[3] ID[2] ID[1] ID[0] x x 0 0 0 1 1 0 Document Version D Pge 12 of 13
Pckge Drwing nd Mrking Illustrtion Top View Bottom View 0.025 1 2 3 6 5 4 0.025 e t O 6-0.22 Side View Figure 15 Document Version D Pge 13 of 13