It s a matter of tradition RAPID WHOLE - CHIP RF MODELING ñ Inductance-aware RFIC design
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It s a matter of tradition IPL MEMBER Helic's VeloceRFì is based on more than a decade of research on rapid electromagnetic modeling algorithms, adapted to modern silicon technologies. Its seamlessly-integrated design flow enables you to rapidly synthesize spiral inductors, model interconnect parasitics, verify RF ICs with mutual inductance effects all with great ease of use and without wait. VeloceRF is used by semiconductor companies worldwide in the design of demanding circuits for WCDMA, PHS, WLAN, UWB, multi-gigabit communications and more. Whatever your design domain SiGe BiCMOS, 90 nanoscale RF CMOS, System-in-Package inductance is key to first-pass success. Start dealing with it using VeloceRFì.
First-time-right RF silicon has been a dream. We strongly believe the designer-centric methodology, the tools and the PDK adaptation we provide with Helic is the ultimate door opener to the whole new world of RF COT/ASIC. Tetsu Tanizawa Fujitsu Limited Sirenza has used VeloceRF for a number of different applications, such as a 5.8GHz ISM band FSK transceiver with a +21dBm PA. VeloceRF allowed us to model supply and ground inductance, giving us insight on how to minimize inductance and mutual inductance that would reduce gain or cause instability. With the use of VeloceRF, the PA met specifications on first pass silicon. Being seamlessly integrated in our design flow, VeloceRF is very easy to use. Bob Koupal Sirenza Microdevices, Inc. The integration of the tool in the Cadence-based design flow is amazing. It allows for a very fast and seamless inductor implementation from initial L and Q request to full layout, Spectre and S-parameters models. Automatically generated testbenches and plots give the designer a full picture of inductor behaviour over a wide frequency range. The ability to generate a poly shield with the touch of a button is great bonus too. Vladimir Posse ClariPhy Communications, Inc.
No more visits to the oracle VeloceRF - Spiral Wizard If you are used to relying on an oracle or EM guru for optimal inductors, there is now a better and faster way. If you are the EM guru in your company, your life has just become easier. With Spiral Wizard TM, part of the VeloceRF toolset, it takes only a few seconds to synthesize an inductor geometry according to spec. The Spiral Wizard helps you reach an optimal inductor solution effortlessly. It automatically decides on metal stacking and ground shielding options and delivers DRC-clean output, compliant with DFM rules and electromigration constraints. Optionally, the Spiral Wizard can shrink the size of the resulting spiral inductor or transformer, helping you save precious real estate.
The end of a speed vs. accuracy dilemma Clearly, spending several minutes, hours or even days to model a single spiral inductor is a productivity killer. On the other hand, alternatives such as lookup tables and back-of-the-envelope calculations will not meet your accuracy requirements. And it is not only spirals, but also critical interconnect that should be modeled. VeloceRaptor TM, a powerful modeling engine, now cuts the Gordian knot of on-chip EM simulation, by introducing rapid RLCk netlist extraction for spiral Pcells and arbitrary interconnect with proven accuracy in RF and microwave frequencies. This robust, vectorbased engine was developed specifically for integrated structures; even the most complex structures are extracted in seconds. No compromises in accuracy are made though; all applicable EM effects are covered. Conductor skin and proximity effect modeling is comprehensive, yet extremely fast. On-chip temperature gradients can also be modeled, enhancing the verification of RF front-end cells such as integrated power amplifiers and VCOs. Nevertheless, the model netlist size does not get out of hand. Novel algorithms provide adaptable netlist compaction, ranging from full distributed RLCK model to a simplified pi-network. Dielectric C P Broadband skin-effect model C P Magnetic and capacitive coupling R SUB Detailed substrate model takes into account distance and shape of grounding contacts
Inductance gains ground If you have been using conventional EM solvers for inductor simulation, you have probably been ignoring ground effects. But a spiral inductor is more than a metal coil. On-chip ground is key in determining inductance effects at high frequencies. VeloceRF seamlessly models parasitic effects introduced by substrate contacts around the spiral. This ensures resonance frequencies are correctly predicted, which leads to safer design. Additionally, VeloceRF Pcells support shielding structures that you can use for optimizing the quality factor and isolation properties of spiral inductors. ñ Accurate substrate modeling for CMOS, SiGe, SOI ñ Parametric polysilicon mesh shields ñ Custom shield design capability
EM meets DFM Making it manufacturable is one thing; being able to model it is another. Design for Manufacturability (DFM) rules impose changes in the structure of spiral inductors and high-speed interconnects that affect their electromagnetic (EM) behaviour. Slotting should be applied to relieve mechanical stress on wide metal tracks. Coverage rules in 90nm and 65nm CMOS impose dummy fill patterns or confetti around spiral inductors. VeloceRF supports all this and more, providing Pcells with built-in DFM. You can also simulate the effects of DFM on the EM properties of inductors and interconnects. All of this is performed with great ease and speed. ñ Spiral inductor track slotting ñ Metal track stacking with distributed via contacts ñ Dummy fill patterns included in spiral cells
Go with the flow VeloceRF is taking care of the inductors, so that you can focus on designing your circuits. A topology-aware, highly accurate magnetic coupling component can be easily added in schematics simulations making mutual inductance modeling more intuitive. Parasitic magnetic effects are seamlessly included in the early stages of design. VeloceRF seamlessly interfaces with other tools in your design flow, which makes designing and extracting inductors very straightforward. Verification is greatly enhanced for RF, with inductors being included in layout vs. schematics (LVS) checks. You can extract the whole chip with a single click, taking into account all intentional, parasitic and mutual inductances. Interconnects can easily be extracted in place, so full-chip EM simulation becomes part of the flow. ñ Extraction of spirals and interconnects from layout with mutual inductances ñ LVS checks of spiral inductor connectivity and properties
Product Datasheet VeloceRaptorì modeling engine Modeling approach Vector-based lumped-element (RLCK) modeling of conductor microstrips. Support for substrate and dielectric losses, conductor skin effect, metal track stacking, temperature gradients. Technology setup ASCII-type file containing metal, dielectric and substrate thickness and resistivity parameters (typical, min, max). No parameter fitting or preprocessing required. Input geometries VeloceRF inductor Pcells, arbitrary path shapes, path-like polygon shapes. Extraction times * 1-2 sec for a 5-turn octagonal spiral inductor 3-4 sec for 4x octagonal spiral inductors as above 4-5 sec for above inductor, with polysilicon mesh shield * measured on an Athlon 3000+/1.8GHz CPU, 2Gb RAM Corner models ñ High L ñ Low L ñ Best Case Q ñ Worst Case Q Supported simulators Any SPICE-type simulator. Spiral Wizardì inductor synthesis & parametric inductor library Supported structures Square, rectangular, octagonal, polygonal and circular spiral inductors (single, differential with/without center-tap, tapered). Spiral transformers, baluns. Synthesis criteria Inductance @ frequency, quality factor, size, track width, bridge segment orientation, metal layer stack, polysilicon shield. For transformers and baluns: center frequency, insertion loss, return losses, bandwidth. VeloceRulesì interfaces for layout vs. schematic verification Methodology Spiral inductor instances have layout, symbol and schematic views to support LVS. For post-layout verification, an extracted view is generated, encapsulating a netlist model for all inductors and any mutual inductances. Metal or polysilicon interconnects and arbitrary paths from layout can be interactively included in the extracted view model. Supported LVS tools Cadence Assura, Mentor Calibre, Synopsis Hercules. Additional tools with standard interfaces (e.g. CDL, GDSII) can be supported. LVS checks Spiral inductor connectivity, spiral type, size, number of turns, track width, polysilicon, shield (on/off), stacking profile. VelocePASSì Process Design Kit setup system Functionality ñ Graphical definition of VeloceRF technology file ñ Pcell layer selection and customization of VeloceRF inductor library ñ Automated creation of VeloceRules (LVS rule decks) ñ Spiral Wizard solution space setup DRC/DFM features ñ Minimum/maximum metal track parameter setting ñ Via contact geometry definition ñ Metal slotting parameter setting ñ Polysilicon shield setting ñ Current carrying limit definition ñ Stacking profile System Requirements Hardware ñ x86 based PC (Intel/AMD) ñ Sun Sparc workstations ñ HP RISC workstations Operating Systems ñ Linux: RedHat 8 / 9 / EL3, SuSE 9.3 / SLES9 ñ SunOS/Solaris: 8 / 9 ñ HPUX: 11.00 / 11.11 ñ Windows 2000/XP * EDA Platforms Cadence IC 5.1.41-USR4 or higher OpenAccess compatible Support for Ciranova PyCellsì
Ordering information VeloceRFì is licensed under time-based lease (TBL) and permanent lease schemes, in a bundle that comprises all of the above modules. Typical customers include fabless chip companies, IDMs, silicon and compound semiconductor foundries. VelocePASSì is a companion product that automates PDK setup for use with VeloceRF. It addresses the needs of foundries and IDMs maintaining custom PDKs. The software allows a high degree of customization in the core features of VeloceRF, such as enabling Design for Manufacturing (DFM) rules for spiral Pcells. VelocePASS is bundled with a priority maintenance and support package that offers customer request processing for Pcell customization and early access to VeloceRF updates. The following programs are offered: ñ VelocePASS basic: License and support for up to two (2) silicon PDKs. ñ VelocePASS advanced: License and support for up to four (4) PDKs, which may include silicon, non-silicon (e.g. GaAs) and SiP processes. Includes 40 hours of on-site and internet-based training. ñ VelocePASS IDM: License and support for up to ten (10) PDKs, silicon, non-silicon and SiP. Includes up to 90 hours of on-site and internetbased training. Product options and codes for RFQ and purchase orders: Code Product License scheme 1100-FL VeloceRF Site license, floating key, 12 mo. TBL 1100-FL-PM VeloceRF Site license, floating key, permanent 1200-FL-B VelocePASS basic Site license, floating key, 12 mo. TBL 1200-FL-A VelocePASS advanced Site license, floating key, 12 mo. TBL 1200-FL-I VelocePASS IDM Site license, floating key, 12 mo. TBL Trademark notice: VeloceRF, the VeloceRF logo, VeloceRaptor, Spiral Wizard, VeloceRules and VelocePASS are trademarks of Helic S.A. The Helic logo is a registered trademark of Helic S.A. All other trademarks are the property of their respective owners. Copyright 2008 by Helic S.A. All rights reserved. Reproduction in whole or in part of this document is prohibited without the prior written consent of the copyright owner. Helic S.A. reserves the right to change specifications contained in this document without notice and without assuming any liability.
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