Tunneling Field Effect Transistors for Low Power ULSI Byung-Gook Park Inter-university Semiconductor Research Center and School of Electrical and Computer Engineering Seoul National University
Outline I. Introduction II. III. IV. Novel Injection Mechanisms for Sub-60 mv/dec. Subthreshold Swing Tunneling Field Effect Transistor (TFET) Advanced TFET Structures VI. Conclusions 2
Average Design Rule ( m) CMOS Scaling-Down 100 SIA Roadmap 94 10 1 SIA Roadmap 97 ITRS (DRAM) 11 ITRS (MPU) 11 D.R. = 20e -0.116(Y-1960) q ~ 3 yrs : 2-1/2 q ~ 20 yrs : 10-1 0.1 ITRS ( 11) 2024 : 7.4 nm (MPU L phy ) 0.01 1960 1980 2000 2020 Year 2026 : 5.6 nm (MPU L phy ) 3
Power: Roadblock to CMOS Scaling 4
Power: Roadblock to 3D Integration q 3D Integration of Devices - Confrontation of scaling limit - 3D stacked arrays <H. Aochi, et al. SSDM 2008> q System in Package - Independent process optimization - Through silicon via (TSV) ** Heat generation is N times the single layer case!! 5
CMOS: Switching and Leakage Power Switching Power P 2 fcv DD log I D Leakage Power log I OFF P V DD I OFF 1/ SS Unavoidable Link Subthreshold Swing (SS) V G 6
Ideal Switch SS = 0 ln I D I OFF = negligible V DD << 1V ln I OFF V G 7
Origin of the 60 mv/dec. SS Limit q Thermal Carrier Injection: - Control of the energy barrier height by the bias voltage - Carrier energy distribution by the Boltzmann law q(v 0 -V) q(v 0 -V) q( V V )/ kbt I Ae 0 q( V log I log A k dv d(log I) kbt q log e B V ) T 0 log e ~ 60 mv/dec. at 300K 8
Outline I. Introduction II. III. IV. Novel Injection Mechanisms for Sub-60 mv/dec. Subthreshold Swing - Impact Ionization - Tunneling Tunneling Field Effect Transistor (TFET) Advanced TFET Structures VI. Conclusions 9
Various Approaches ** Some mechanisms that do not depend on thermal carrier injection. IMOS: injection by impact ionization TFET : injection by inter-band tunneling Mechanical Switch: injection by mechanical contact 10
Concept of Impact Ionization 11
Avalanche Multiplication 12
I-MOS Device Concept q I-MOS (Impact-Ionization MOS) was proposed first by K. Gopalakrishnan. (IEDM 2002) q It uses modulation of avalanche breakdown voltage of a gated p-i-n diode. n + Drain Gate p + Source N + Source Gate P + Drain L G L I t ox L I L G t ox Intrinsic Si Substrate Intrinsic Si Substrate <n-channel I-MOS> <p-channel I-MOS> 13
I-MOS Device Characteristics q Transfer Curves I D (A/ m) 10-3 V D = 1V 10-4 VD = 0.1V 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 SS = 3.7mV/dec T = 300K L G = 70nm L I = 50nm W = 10 m t ox = 3nm 0.0 0.2 0.4 0.6 0.8 1.0 V G (V) <n-channel I-MOS> I D (A/ m) 10-3 V D = -1V 10-4 VD = -0.1V 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 SS = 8.9mV/dec T = 300K L G = 70nm L I = 50nm W = 10 m t ox = 3nm -1.0-0.8-0.6-0.4-0.2 0.0 V G (V) <p-channel I-MOS> 14
Concept of Tunneling (1) 15
Concept of Tunneling (2) 16
Outline I. Introduction II. III. III. Novel Injection Mechanisms for Sub-60 mv/dec. Subthreshold Swing Tunneling Field Effect Transistor (TFET) - Device Structure and Operation - Fabrication and Characteristics Advanced TFET Structures VI. Conclusions 17
TFET Device Structure q p + source instead of n + source in n-channel MOSFET (n + source instead of p + source in n-channel MOSFET) q Induced tunnel junction between source and channel Gate Gate p + Source n + Drain n + Source p + Drain L G Si substrate Si substrate L G t ox t ox <n-channel TFET> <p-channel TFET> 18
TFET Device Operation q OFF state - Valence electron tunneling blocked q ON state - Valence electron tunneling allowed 19
TFET Device Fabrication (1) q Device Structure: - Basically the same as I-MOS except the lack of impact ionization region (L i = 0) - Thinner t ox 20
TFET Device Fabrication (2) q SEM Micrograph 21
TFET Device Characteristics q Transfer Curves <n-channel TFET> 22
Outline I. Introduction II. III. IV. Novel Injection Mechanisms for Sub-60 mv/dec. Subthreshold Swing Tunneling Field Effect Transistor Advanced TFET Structures - Smaller Bandgap Material - Stronger Field - Larger Injection Area IV. Conclusions 23
Silicon TFET Device Issues q Main Issue: - Low ON current due to the relatively large bandgap of silicon q Approaches: - Smaller bandgap material (Ge, graphene) - Stronger field - Larger injection area 24
Gate Gate Ge Source TFET q Ge source TFET - Ge region for source and part of the channel narrow bandgap - double gate field enhancement through stronger gate control Ultrathin body to utilize field-coupling effect (Critical dimension) Ge region with p-n junction across P+ Ge source N+ Ge channel Very lightly doped Si channel S/Channel Jct. with engineered tunneling barrier Long enough channel to suppress SCE N+ drain Bottom oxide BOX or p-type substrate 25
Gate-All-Around TFET (1) q GAA TFET Structure - field concentration - n-doping layer for field enhancement 26
Gate-All-Around TFET (2) 27
L-Shaped TFET q L-shaped TFET - tunneling toward gate - increase of tunneling area 28
Conclusions (1) q CMOS device scaling is faced with a big roadblock: power consumption. But, we cannot arbitrarily reduce the power supply voltage in CMOS circuits because of the exponential leakage current increase. q The leakage current can be drastically reduced by decreasing the subthreshold swing (SS) below 60 mv/dec. Thus, new injection mechanisms to decrease the subthreshold swing are actively pursued. q Utilizing impact ionization is one of the approaches (i-mos). Interband tunneling is another mechanism (TFET). q Tunneling Field Effect Transistor (TFET) is a promising low-power device based on inter-band tunneling mechanism. 29
Conclusions (2) q We have fabricated and characterized TFETs that show 52.8 mv/dec. subthreshold swing. q One major issue with silicon TFET devices is the low ON current due to the relatively large bandgap. q Various approaches to increase the ON current of TFETs are pursued: 1) Smaller bandgap material such as germanium is incorporated in the source. 2) Stronger field is induced in the source end of the channel by utilizing field concentration effect. 3) The injection area is increased by changing the device structure. 30