ARCHIVE 2010 LOW COST, SMALL FORM FACTOR PACKAGING by Brandon Prior Senior Consultant Prismark Partners W ABSTRACT hile size reduction and performance improvement are often the drivers of new package and interconnect solutions, cost reduction strategies have become an even more critical factor to further enable continued profitability through challenging times. Although those times are hopefully (albeit temporarily) behind us, many companies large and small have adopted strategies to reduce package, interconnect and test cost. This presentation paper will look at leading package trends driven by cost reduction. COPYRIGHT NOTICE The papers in this publication comprise the proceedings of the 2010 BiTS Workshop. They reflect the authors opinions and are reproduced as presented, without change. Their inclusion in this publication does not constitute an endorsement by the BiTS Workshop, the sponsors, BiTS Workshop LLC, or the authors. There is NO copyright protection claimed by this publication or the authors. However, each presentation is the work of the authors and their respective companies: as such, it is strongly suggested that any use reflect proper acknowledgement to the appropriate source. Any questions regarding the use of any materials presented should be directed to the author/s or their companies. All photographs in this archive are copyrighted by BiTS Workshop LLC. The BiTS logo and Burn-in & Test Socket Workshop are trademarks of BiTS Workshop LLC. BiTS Workshop 2010 Archive
Low Cost and Small Form Factor Packaging Brandon Prior Prismark Partners 2010 BiTS Workshop March 7-10, 2010 GROWTH CYCLES OF ELECTRONICS MARKET Relative Growth (1998 = 100%) 300% Electronics Systems Market - $893Bn in 1998 N210.239jd-growth dec1 250% Semiconductor Market - $126Bn in 1998 PCB and Substrate Market - $33.1Bn in 1998 Global Recession Financial Crisis Demand Drop 200% 150% Dotcom Bubble Over Supply 100% 50% Concentrated sector decline Large inventory build up in supply chain Wide spread decline Lean supply chain no excess 0% 1998 1999 2000 2001 2002 2003 2005 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 3/2010 BiTS 2010 : Low Cost and Small Form Factor Packaging 2 March 7-10, 2010 1
WHY LOW COST PACKAGES? Cost Reduction is always a priority, but industry downturns increase the stress put into cost reduction strategies Various approaches can be applied Raw Material Cost (e.g. Copper vs. Gold wire) Package Size Reduction (QFN/DFN, tighter pitch FBGA, WL- CSP) Outsourcing and Regional Shifts Efficiency Improvements (throughput, strip test, etc) 3/2010 BiTS 2010 : Low Cost and Small Form Factor Packaging 3 SEMICONDUCTOR FABRICATION VALUE CHAIN (2009) A 40% Gross Margin Business A 15% to 35% Gross Margin Business A 40% Gross Margin Business $97Bn $25Bn $36Bn $68Bn $226Bn Wafer Fabrication 43% Test Value (Wafer Probe, Package Test) 11% Package Assembly 16% Design, SG&A,and Profit (Gross Margin) 30% Shipped Silicon 100% Kc210.267bp-silicon $76Bn FAB Process Packaging Assembly $20.5Bn $21Bn Input Materials Input Materials and Fabricated Components $15.5Bn 3/2010 BiTS 2010 : Low Cost and Small Form Factor Packaging 4 March 7-10, 2010 2
100% 90% IC PACKAGE VALUE TREND Wirebond (Leadframe/Module) Kc210.088bp package value Percent of IC Package Value Add 80% 70% 60% 50% 40% 30% 20% Wirebond (BGA/CSP) Flip Chip DCA Flip Chip Package 10% 3D TSV 0% 1990 1995 2000 2005 2010 2015 2020 $6Bn 10% CAAGR $25Bn 6% CAAGR $59Bn 3/2010 BiTS 2010 : Low Cost and Small Form Factor Packaging 5 ARRAY PACKAGE PITCH TRENDS (BGA, CSP, PGA, LGA, WLCSP) (Excludes Small Die DCA, Display Drivers, and RF Modules) Bn Units 50 Kc29.088bp-pitch trends 45 40 35 DCA in Module 0.4mm 0.3mm 30 25 0.5mm 20 15 10 0.65-0.8mm 5 1.0mm 0 2004 2005 2006 2007 2008 2009 2010 2011 2012 1.27mm 2013 Note: Sub 0.5mm was 2% of overall volume in 2008. By 2013 this will increase to 12% or 5.7Bn units 3/2010 BiTS 2010 : Low Cost and Small Form Factor Packaging 6 March 7-10, 2010 3
TI WiLink 6.0 Single chip WLAN (b/g/n), Bluetooth, and FM Tx/Rx Found as WLCSP in Motorola Droid Mounted on main board, underfilled 5.0 x 4.6mm die size 0.4mm pitch 126 balls (near full array) One metal layer redistribution 210.1/085bp Photos source: Prismark/Binghamton University 3/2010 BiTS 2010 : Low Cost and Small Form Factor Packaging 7 WLCSP SOLUTION IN APPLE ipod TOUCH 79.10/283bp WLAN/Bluetooth/FM Radio (FM not enabled) Broadcom BCM4325 WLAN/BT/FM WLCSP 6.4 x 5.7mm 320 SnAg bumps at 250µm pitch Ceramic filter, crystal 52 SMT parts 1.0cm 2 PCB area mounted on rigid-flex Photo source: Prismark/Binghamton University 3/2010 BiTS 2010 : Low Cost and Small Form Factor Packaging 8 March 7-10, 2010 4
99.1/085bp Mobile Phone RECENT WLCSP APPLICATION EXAMPLES Total Wafer CSP WLCSP Applications Comments Palm Pre 10 ESD/EMI, EEPROM, 6 25 I/O on board Bluetooth, WLAN WLAN, BT, EEPROM on module Panasonic P901i TV 7 ESD/EMI, Up to 5mm die with 119 I/O at 0.4mm analog/power, other? pitch LG KM900 Arena 3 ESD/EMI, GPS 4.7mm, 64 I/O at 0.4mm pitch Apple iphone 3GS 6 Panasonic P905i 6 ESD/EMI, Bluetooth, WLAN, GPS Transceiver, Bluetooth, power, TV tuner (two chips), GPS Up to 4.7mm die with 69 I/O at 0.4mm pitch on board, 6.4 x 5.7mm die at 320 I/O on module 5 die use copper post tech, up to 185 I/O at 0.4mm pitch Nokia 6220 Classic 7 ESD/EMI, power, other? Up to 5mm die Nokia N95 8 Nokia N97 8 EMI/ESD, analog, Bluetooth, FM radio EMI/ESD, GPS, WLAN, analog Up to 4mm die with 47 I/O at 0.5mm pitch Up to 4.4mm on module (104 I/O) Up to 3.5mm die on board (61 I/O) 3/2010 BiTS 2010 : Low Cost and Small Form Factor Packaging 9 TOSHIBA TCM9000MD VGA MODULE USING TSV 210.8/371PL Image sensor die 25 balls at 0.5mm pitch 2.8 x 3.3mm Lens Barrel 70µm thick 125µm thick attach to glass 350µm thick glass IR Filter Die Attach Via Image Sensor Glass Plate 50µm 8µm 70µm 70µm Photos source: Prismark/Binghamton University 3/2010 BiTS 2010 : Low Cost and Small Form Factor Packaging 10 March 7-10, 2010 5
ST-ERICSSON ROADMAP COMMERICAL WIRELESS PRODUCTS 99.5/294bp 3/2010 BiTS 2010 : Low Cost and Small Form Factor Packaging 11 210.1/141bp COPPER WIRE BONDING DRIVING FORCES Lower cost metal Most attractive for thick gold wire (33µm 50µm) 90% to 95% material cost savings depending on diameter Higher thermal and electrical conductivity Other driving forces Stiffer wire/less wire sweep for longer bonds with thin diameter wire Higher current capability Can use existing wire bonders with conversion kits 3/2010 BiTS 2010 : Low Cost and Small Form Factor Packaging 12 March 7-10, 2010 6
78.141bp COPPER WIRE ENABLES LOWER COST Leadframe and CSP Examples No argument that copper wire is lower cost than gold wire. Two example products and differences between copper and gold wire are shown below: SO-14 (33µm wire) Cu Wire Au Wire Wire Cost 0.1 1 Wire Bonding Cost 0.6 0.5 Other Package Costs 1.1 1.1 Total Cost (not price) 1.8 2.6 Total Savings: 0.8 or 30% 350 FBGA (20µm wire) Cu Wire Au Wire Wire Cost 3 13 Wire Bonding Cost 17 15 Other Package Costs 37 37 Total Cost (not price) 57 65 Total Savings: 8 or 12% Savings with copper wire as a percent of package are more pronounced with thicker wire, not more wires. Concerns with yield are less noticed with low I/O, low-value devices. 3/2010 BiTS 2010 : Low Cost and Small Form Factor Packaging 13 COPPER WIRE BOND STATUS In 2009, copper represented 4% to 5% of all bonding wire by length, up from < 1% in 2006 This is expected to reach 15% or more by 2014 Driving applications are power discretes (i.e., power transistors, rectifiers, thyristors), power/logic mixed signal devices, and now logic and memory Justification Lower cost than thick gold Faster bonding than aluminum Possibility to do corners easily (unlike aluminum) Possibility to place function under pads (unlike aluminum) However, copper wire may be slow to penetrate mainstream IC market as the following items are addressed: Yield parity with gold Establish comprehensive reliability database Pad structure compatibility Qualification risk and expense mitigated 210.1/141bp 3/2010 BiTS 2010 : Low Cost and Small Form Factor Packaging 14 March 7-10, 2010 7
WORLDWIDE PACKAGE ASSEMBLY HOT SPOTS Europe 4% of Package Assembly Value Morocco Malta Germany Ireland France Portugal Santa Clara, CA US Mexico Canada Phoenix, AZ Americas 3% of Package Assembly Value Nijmegen Grenob le Munich Milan Japan 19% of Package Assembly Value Seoul Shanghai Taipei Penang Singapore Asia 74% of Package Assembly Value Malaysia Philippines Taiwan Korea 14% 9% 17% 8% Singapore China/ 3% 20% Indonesia/Thailand/Others 3% Iwate To k yo Kyushu Kaohsiung Cavite S117.267bp_hot 3/2010 BiTS 2010 : Low Cost and Small Form Factor Packaging 15 CONCLUSIONS Semiconductor companies always searching for cost reduction strategies Various approaches can and have been applied Copper vs. Gold wire, Lower cost EMC, laminate, etc Smaller packages such as QFN/DFN, tight pitch FBGA, and WL- CSP as bare die Outsourcing and Regional Shifts Asia already dominates, but continued growth in China, India, Philippines and Vietnam Efficiency Improvements (throughput, strip test, etc) are never sufficient 3D/TSV approaches are still searching for cost effective test Pitches approach 50um Test before die to die or die to wafer assembly often required 3/2010 BiTS 2010 : Low Cost and Small Form Factor Packaging 16 March 7-10, 2010 8