WCAS2016 Analysis and Design of 180 nm CMOS Transmitter for a New SBCD Transponder SoC Andrade, N.; Toledo, P.; Cordova, D.; Negreiros, M.; Dornelas, H.; Timbó, R.; Schmidt, A.; Klimach, H.; Frabris, E. And Bampi, S. NSCAD Microeletrônica, Porto Alegre, RS, Brazil nj.andrade@hotmail.com {toledo, david, marcelo.negreiros, helga.dornelas, rene.timbo, alonso}@nscad.org.br, hamilton.klimach@ufrgs.br, {bampi, fabris}@inf.ufrgs.br WCAS2016-6 th Workshop on Circuits and Systems Design CHIP ON THE MOUNTAINS Belo Horizonte, Brazil 29 August 03 September, 2016
Agenda Motivation Satellite Transponder SoC Transmitter Architecture Transmitter Design Results Conclusions WCAS2016, Belo Horizonte, Brazil, 2016 - Analysis and Design of 180 nm CMOS Transmitter for a New SBCD Transponder SoC 2
Agenda Motivation Satellite Transponder SoC Transmitter Architecture Transmitter Design Results Conclusions WCAS2016, Belo Horizonte, Brazil, 2016 - Analysis and Design of 180 nm CMOS Transmitter for a New SBCD Transponder SoC 3
Motivation (1) CI Brazil - IC Design Training Program - Project Phase Designs implemented from functional specification down to physical implementation (180nm from XFAB) IPs evaluation and usage Ongoing Project: DSP-Based Satellite Transponder SoC (RF+AMS+DSP) www.ci-brasil.gov.br/ WCAS2016, Belo Horizonte, Brazil, 2016 - Analysis and Design of 180 nm CMOS Transmitter for a New SBCD Transponder SoC 4
Motivation (1) Brazilian System of Data Collection (SBCD) Collection of environmental and weather data in Brazil through sensors attached to Data Collection Platforms (DCP) spread all over the Brazilian territory. Satellites receive the DCP signals and send then back to ground stations in two processing centers. WCAS2016, Belo Horizonte, Brazil, 2016 - Analysis and Design of 180 nm CMOS Transmitter for a New SBCD Transponder SoC 5
Agenda Motivation Satellite Transponder SoC Transmitter Architecture Transmitter Design Results Conclusions WCAS2016, Belo Horizonte, Brazil, 2016 - Analysis and Design of 180 nm CMOS Transmitter for a New SBCD Transponder SoC 6
Satellite Transponder SoC This Presentation Next Presentation Next Presentation WCAS2016, Belo Horizonte, Brazil, 2016 - Analysis and Design of 180 nm CMOS Transmitter for a New SBCD Transponder SoC 7
Agenda Motivation Satellite Transponder SoC Transmitter Architecture Transmitter Design Results Conclusions WCAS2016, Belo Horizonte, Brazil, 2016 - Analysis and Design of 180 nm CMOS Transmitter for a New SBCD Transponder SoC 8
Transmitter Architecture (2) Transmitter Block Diagram I t pm t Q t Analog pm t = A c cos(2π Fc t + m t k p ) pm t = A c (cos(2π Fc t) cos m t k p sin(2π Fc t) sin m t k p ) Digital I t = cos m t k p Q t = sin m t k p WCAS2016, Belo Horizonte, Brazil, 2016 - Analysis and Design of 180 nm CMOS Transmitter for a New SBCD Transponder SoC 9
Transmitter Architecture (1) Transmitter Block Diagram Thursday, 09/01 at 18:00 h. (More details) Band-S 0 KHz 755 KHz Thursday, 09/01 at 10:40 h. (More details) Transmitter Specification Parameter Min Typ Max Unit Output Frequency 2267.52 MHz Input Frequency 0 775 khz Corners: ±10% variation of VDD Temperatures between -40 C and 125 C. Output Power 20.5 21.5 22.5 dbm Output Impedance 50 Ohm RF Mask Attenuation 40 db RF Mask Bandwidth 1.55 MHz Intermodulation Products -30 db Maximum Peak Power 24.75 dbm LO Amplitude Mismatch 20 mv LO Phase Mismatch 2 Supply Current 20 ma Modulation Index (kp) 1.6 1.8 2.0 - WCAS2016, Belo Horizonte, Brazil, 2016 - Analysis and Design of 180 nm CMOS Transmitter for a New SBCD Transponder SoC 10
Agenda Motivation Satellite Transponder SoC Transmitter Architecture Transmitter Design Results Conclusions WCAS2016, Belo Horizonte, Brazil, 2016 - Analysis and Design of 180 nm CMOS Transmitter for a New SBCD Transponder SoC 11
Transmitter Design (1) DAC Topology 2nd order Sigma-Delta modulator with 32x oversampling; Input: 10 bits data stream; [1] E. Hogenauer, An economical class of digital filters for decimation and interpolation, TASSP, 1981 [2] J. Logue, XAPP154: Virtex Synthesizable Delta-Sigma DAC, Xilinx,1999, [Online]. Ava: http://www.xilinx.com/support/documentation/application_notes/xapp154.pdf [3] Torres, M. Low drop-out voltage regulators: Capacitor-less architecture omparison, Circuits and Systems Magazine WCAS2016, Belo Horizonte, Brazil, 2016 - Analysis and Design of 180 nm CMOS Transmitter for a New SBCD Transponder SoC 12
Transmitter Design (2) Filter Topology Fully Differential Thursday, 09/01 at 18:00 h. (More details) Third order Gm-C LPF OTAs with inherent common mode detection OTAs with llinearity enhancement [4] A. N. Mohieldin A low-voltage fully balanced ota with common mode feedforward and inherent common mode feedback detector, ESSCIRC 2002. [5] T. Y. Wang Linearity efficiency factor and power-efficient operational transconductance amplifier in subthreshold operation ISCAS 2015 WCAS2016, Belo Horizonte, Brazil, 2016 - Analysis and Design of 180 nm CMOS Transmitter for a New SBCD Transponder SoC 13
Transmitter Design (3) Modulator Design Conventional Gilbert Cell topology (no strong linearity requirements); Resistors used as load, to perform the addition of I and Q branches easily; [6] B. Razavi, RF Microelectronics. Prentice Hall, 2011. WCAS2016, Belo Horizonte, Brazil, 2016 - Analysis and Design of 180 nm CMOS Transmitter for a New SBCD Transponder SoC 14
Transmitter Design (4) PA Design [7] Two Stages Class-A Topology Envelope Detector to control output power External Amplifier needed. [7] TRF1123: 2.1-GHz to 2.7-GHz 1-W Power Amplifier, Texas Instruments, 09 2006, datasheet., WCAS2016, Belo Horizonte, Brazil, 2016 - Analysis and Design of 180 nm CMOS Transmitter for a New SBCD Transponder SoC 15
Transmitter Design (5) Yield Considerations Individual biasing sources to compensate temperature variations 5 bits calibration resolution for PV conditions WCAS2016, Belo Horizonte, Brazil, 2016 - Analysis and Design of 180 nm CMOS Transmitter for a New SBCD Transponder SoC 16
Agenda Motivation Satellite Transponder SoC Transmitter Architecture Transmitter Design Results Conclusions WCAS2016, Belo Horizonte, Brazil, 2016 - Analysis and Design of 180 nm CMOS Transmitter for a New SBCD Transponder SoC 17
Filter Output [db] Results (1) Digital to Analog Conversion By applying one tone of 155kHz. At the DAC output: Effective Number of Bits (ENOB): 9bits; Signal-to-Noise and Distortion Ratio (SINAD): 43.63 db; Total Harmonic Distortion (THD): -46.01 db. -10-30 -50-70 -90-110 155.27kHz -10.26 db DAC ENOB Plot -130 1,E+04 1,E+05 1,E+06 1,E+07 Frequency [Hz] WCAS2016, Belo Horizonte, Brazil, 2016 - Analysis and Design of 180 nm CMOS Transmitter for a New SBCD Transponder SoC 18
Results (2) Output Power Output Power = 21.88 dbm. WCAS2016, Belo Horizonte, Brazil, 2016 - Analysis and Design of 180 nm CMOS Transmitter for a New SBCD Transponder SoC 19
Results (3) Linearity (1) - 47.2 db spurious rejection WCAS2016, Belo Horizonte, Brazil, 2016 - Analysis and Design of 180 nm CMOS Transmitter for a New SBCD Transponder SoC 20
Results (5) Variability MC analysis for 50 samples: Uncalibrated Yield: 24% Calibrated Yield: 82% WCAS2016, Belo Horizonte, Brazil, 2016 - Analysis and Design of 180 nm CMOS Transmitter for a New SBCD Transponder SoC 21
Results (6) Summary Specification Parameter Min Typ Max Result Unit Output Power 20.5 21.5 22.5 21.88 dbm RF Mask Attenuation 40 47.7 db Intermodulation Products 30 40.6 db ENOB (at filter output) 8 9 bits Supply Current 20 19.6 ma WCAS2016, Belo Horizonte, Brazil, 2016 - Analysis and Design of 180 nm CMOS Transmitter for a New SBCD Transponder SoC 22
Agenda Motivation Satellite Transponder SoC Transmitter Architecture Transmitter Design Results Conclusions WCAS2016, Belo Horizonte, Brazil, 2016 - Analysis and Design of 180 nm CMOS Transmitter for a New SBCD Transponder SoC 23
Conclusions A transmitter with I-Q modulation, operating in 2.267 GHz for a SBCD DSP-based satellite transponder SoC was analyzed and designed in CMOS 180 nm technology. Output Power: 21.88 dbm Spurious Rejection (within 1.55 MHz bandwidth): 47.7 db Supply Current: 19.6 ma Floorplan area 0.544mm² Calibration strategy - Yield Improvement: from 24% to 82%. Design implemented in the context of the CI Brazil Training Program WCAS2016, Belo Horizonte, Brazil, 2016 - Analysis and Design of 180 nm CMOS Transmitter for a New SBCD Transponder SoC 24
Questions? Analysis and Design of 180 nm CMOS Transmitter for a New SBCD Transponder SoC NSCAD Microeletronica / CI Brazil toledo@nscad.org.br Thank you! WCAS2016, Belo Horizonte, Brazil, 2016 - Analysis and Design of 180 nm CMOS Transmitter for a New SBCD Transponder SoC 25
References [1] E. Hogenauer, An economical class of digital filters for decimation and interpolation, TASSP, 1981 [2] J. Logue, XAPP154: Virtex Synthesizable Delta-Sigma DAC, Xilinx,1999, [Online]. Ava: http://www.xilinx.com/support/documentation/application_notes/xapp154.pdf [3] Torres, M. Low drop-out voltage regulators: Capacitor-less architecture omparison, Circuits and Systems Magazine [4] A. N. Mohieldin A low-voltage fully balanced ota with common mode feedforward and inherent common mode feedback detector, ESSCIRC 2002. [5] T. Y. Wang Linearity efficiency factor and power-efficient operational transconductance amplifier in subthreshold operation ISCAS 2015 [6] B. Razavi, RF Microelectronics. Prentice Hall, 2011. [7] TRF1123: 2.1-GHz to 2.7-GHz 1-W Power Amplifier, Texas Instruments, 09 2006, datasheet., WCAS2016, Belo Horizonte, Brazil, 2016 - Analysis and Design of 180 nm CMOS Transmitter for a New SBCD Transponder SoC 26
Appendix WCAS2016, Belo Horizonte, Brazil, 2016 - Analysis and Design of 180 nm CMOS Transmitter for a New SBCD Transponder SoC 27
Motivation (2) Implementation of a DSP-Based Satellite Transponder SoC Analog Transponder Digital Transponder WCAS2016, Belo Horizonte, Brazil, 2016 - Analysis and Design of 180 nm CMOS Transmitter for a New SBCD Transponder SoC 28
Phase Modulation Analysis (1) Transmitter Architecture (2) A signal m t to be transmitted is assumed to be in the interval [-1;+1]. The phase modulated signal (pm t ) is given by: pm t = A c cos(2π Fc t + m t k p ) where A c is the carrier amplitude, Fc is the carrier frequency, t is time and k p is the modulation index, the largest phase deviation possible. By using trigonometrical identities, the phase modulated signal can be written as: pm t = A c (cos(2π Fc t) cos m t k p sin(2π Fc t) sin m t k p ) WCAS2016, Belo Horizonte, Brazil, 2016 - Analysis and Design of 180 nm CMOS Transmitter for a New SBCD Transponder SoC 29
Transmitter Architecture (3) Phase Modulation Analysis (2) The digital blocks of the SoC Transponder produce the signals I t = cos m t k p and Q t = sin m t k p. Therefore, these signals shall be multiplied by the carrier (with the appropriate phase deviations stated by the previous equation) in order to obtain the final modulated signal. An I-Q direct conversion architecture is used in the transmitter, with a sigma-delta digital to analog converter, providing these signals to a modulator block, which performs the required multiplication. WCAS2016, Belo Horizonte, Brazil, 2016 - Analysis and Design of 180 nm CMOS Transmitter for a New SBCD Transponder SoC 30
Transmitter Architecture (4) Bandwidth Requirements and Mask Specification (1) The functions cos m t k p and sin m t k p are non-linear The required signal bandwidth for I and Q signals is larger than the baseband input signal bandwidth; Current analog transponders IF = 90kHz, with 60kHz bandwidth; Maximum Frequency = 125kHz; New digital transponder IF = 90kHz, with 120kHz bandwidth; Maximum Frequency = 155kHz; RF Mask for current analog transponders 1.25MHz centered at F c. 1.25MHz = 2 625kHz (5 th harmonic of a 125kHz signal) RF Mask for new digital transponder 1.55MHz centered at F c. 1.25MHz = 2 775kHz (5 th harmonic of a 155kHz signal) WCAS2016, Belo Horizonte, Brazil, 2016 - Analysis and Design of 180 nm CMOS Transmitter for a New SBCD Transponder SoC 31
Transmitter Design (2) SBCD Transmitter Specifications (2) The main specifications for the design considerations are: Output Power: 20.5 dbm 22.5 dbm Spurious Rejection: 40 dbm Intermodulation Rejection: 30dBm ENOB at Filter Output: 9 bits WCAS2016, Belo Horizonte, Brazil, 2016 - Analysis and Design of 180 nm CMOS Transmitter for a New SBCD Transponder SoC 32
Results (4) Linearity (2) The linearity specification of the ideally demodulated signal was also simulated. The difference between the highest inter- modulation product that arises from the non-linearity of the transmitter and the input tones is 40.6 db, 10.6 db above the specification. WCAS2016, Belo Horizonte, Brazil, 2016 - Analysis and Design of 180 nm CMOS Transmitter for a New SBCD Transponder SoC 33
Transmitter Architecture (3) Bandwidth Requirements and Mask Specification (2) Spectrum of phase modulated sine waves, with frequencies of 125kHz and 155KHz, respectively, and the corresponding mask specifications: WCAS2016, Belo Horizonte, Brazil, 2016 - Analysis and Design of 180 nm CMOS Transmitter for a New SBCD Transponder SoC 34
Transmitter Architecture (4) Signal Path Analysis (1) WCAS2016, Belo Horizonte, Brazil, 2016 - Analysis and Design of 180 nm CMOS Transmitter for a New SBCD Transponder SoC 35
Transmitter Architecture (5) Signal Path Analysis (2) WCAS2016, Belo Horizonte, Brazil, 2016 - Analysis and Design of 180 nm CMOS Transmitter for a New SBCD Transponder SoC 36
Transmitter Architecture (6) Signal Path Analysis (3) WCAS2016, Belo Horizonte, Brazil, 2016 - Analysis and Design of 180 nm CMOS Transmitter for a New SBCD Transponder SoC 37