Communications in Information Science and Management Engineering Apr. 2013, Vol. 3 Iss. 4, PP. 192-19 The Application of System Generator in Digital Quadrature Direct Up-Conversion Zhi Chai 1, Jun Shen 2 etc Beijing Institute of Technology, Beijing, China 1 chaizhi113@12.com; 2 bitshen@bit.edu.cn Abstract-This paper presented a new method of digital quadrature up-conversion design based on field-programmable gate arrays (FPGA), which is the hardware design based on System Generator. First, the paper analysed the principle of digital quadrature up-conversion, applied System Generator for modeling, simulation and hardware implementation, then compared the advantages and disadvantages between the hardware design method based on System Generator and traditional RTL-level (register transfer level) design method based on HDL (hardware design language). Finally, the experiment results showed that the method has higher feasibility, more efficiency and full of resource utilization in practical applications, and it helped to shorten the system development cycle greatly. Keywords- Digital Quadrature Up-Conversion; FPGA; System Generator I. INTRODUCTION Currently, FPGA has become the main device in digital signal processing systems, especially in the field of digital communications, navigation, network, video and image applications. In addition, digital quadrature up-conversion is a widely used technology in digital signal processing, so the use of FPGA in the implementation of digital quadrature up-conversion and other digital signal processing techniques is gradually becoming the mainstream, such as the application in radar echo simulation. However, the traditional RTL-level FPGA hardware design mothed obviously cannot follow the short-term trend of system development cycle, meanwhile, there is also a gap between the pre-matlab-based algorithm verification and FPGA-based hardware implementation. More efficient methods are needed. Given the above considerations, this design comes up with a new approach based on System Generator. The FPGA in Virtex5 series from Xilinx Inc. is selected as the design object, using System Generator software for design and simulation, which is a product of cooperation between Xilinx Inc. and Mathwork Inc.. The application of this software makes it a perfect combination between IP cores provided by Xilinx and tools in Matlab Simulink, making the system-level simulation and verification easier. What s more, with its help, the design model can be directly compiled into netlist file which can be layouted in the FPGA device. As a result, a seamless connection between algorithm and hardware implementation can be built, the efficiency improved greatly and the development cycle shortened [1]. Starting from the digital quadrature up-conversion, this paper uses the method of System Generator-based digital quadrature direct up-conversion design to realize the migration from algorithms to FPGA hardware implementation seamlessly, and it illustrates the feasibility and benefits of the System Generator-based hardware design. II. THE PRINCIPLE OF DIGITAL QUADRATURE UP-CONVERSION DESIGN Digital quadrature modulation is a commonly used modulation technology, and I / Q modulation is the primary modulation method, I refers to the same phase, Q refers to quadrature. The nature of this technology is to multiply the baseband signal I / Q components by the orthogonal local oscillator signal, and then add them together to achieve the signal conversion. Formula is as follows: sin( t) cos( t) cos( t) sin( t) sin(( ) t) The diagram of I/Q modulation is shown in Figure 1 [2]. 1 2 1 2 1 2 Figure 1 The diagram of I/Q modulation What s more, any signal can be expressed in complex signal - 192 -
Communications in Information Science and Management Engineering Apr. 2013, Vol. 3 Iss. 4, PP. 192-19 X () t x () t x () t r in which, xr () t is the real part of the signal, xq () t is the imaginary part of the signal. The quadrature up-conversion of the signal can also be explained in the following way [3]. j t e cos( t) j sin( t) j t that is, complex signal Xt () multiplied by the complex signal e. By taking out the real part, the signal spectrum has been moved, thus we achieve the conversion. We take off the real part of the complex signal to get real signal and symmetrical signal spectrum. The spectra shifting is shown in Figure 2. q Figure 2 Example of the spectra shifting III. SYSTEM GENERATOR-BASED SYSTEM MODELING AND IMPLEMENTATION A. Basic Knowledge on System Generator System Generator is a new FPGA design tool developed by Xilinx Inc. and Mathworks Inc. together. It serves as a bridge between high-level DSP system design and FPGA hardware implementations. Users only need to build the model in Simulink and launch System Generator, then the VHDL source codes and other project files can be generated automatically, and the system model is mapped to the target FPGA device. The typical design process of System Generator includes the following six steps [4]. 1) getting the mathematical description of the algorithm model; 2) building system model in Simulink; 3) the Simulink simulation, and the corresponding parameters adjustment; 4) starting System Generator, and generating the HDL codes and other documents automatically; 5) debugging the generated files, synthesis, translation, map, place&route and timing analysis in the ISE; ) downloading the program to the FPGA device for implementation, running and debugging the program. System Generator provides a module library, named Xilinx Blockset, which includes basic module, digital signal processing module (FIR and FFT), math module, memory module and interface module. And only by using modules in this library, projects can be automatically converted into HDL codes by System Generator. B. System Modeling Based on System Generator The design demonstrates the application of System Generator-based digital quadrature direct up-conversion mothed, selecting sin(5 10 t) and cos(5 10 t) as I / Q signals, and sin(10 t) and cos(10 t) as orthogonal LO signals. Frequencies of I / Q signals are 2.5 MHz, and frequencies of orthogonal LO signals are 5 MHz - 193 -
Communications in Information Science and Management Engineering Apr. 2013, Vol. 3 Iss. 4, PP. 192-19 According to the formula: sin(5 10 t) cos(10 t) cos(5 10 t) sin(10 t) sin(1.5 10 t) we can get a signal as sin(1.5 10 t), frequency of 5 MHz, after the quadrature up-conversion. Then build the model of the system in the System Generator and simulate model, where there are two steps. 1) building the signal models of sin(5 10 t), cos(5 10 t) and cos(10 t) by using DDS technology. 2) combining the above four models together to build the whole system model. Step 1, the building of the four models is shown in Figure 3, which are cos(10 t). sin(5 10 t), cos(5 10 t), sin(10 t) and Figure 3 Model of cos(5 10 t) DDS technology is a new frequency synthesis method, it works as follows: driven by the reference clock, the phase accumulator accumulates frequency control word linearly as the phase code, addressing the waveform memory according to the phase code, then output the corresponding amplitude code, which changes into step wave through analog to digital converter, and finally after smoothed by a low-pass filter, the required frequency of the waveform comes into being. And its formula is as follows: f f K /2 N out clk in which, f out refers to output frequency, f clk refers to the system operating frequency, N is the number of phase accumulator bit, K is the frequency control word, and we can change the value of the output signal frequency by changing the frequency control word K [1]. Figure 3 above shows the model of to the formula: cos(5 10 t), using Convent module to generate a frequency control word, according f f K /2 N out clk 1 we choose the frequency control word K as 13.53125, Z module is used for delaying one clock cycle data. AddSub module is for the continuous cumulative frequency control word. Convent module is for DDS cut-off position. ROM module is for waveform output, and its initial vector is set to sin( (0 : 4095) / 2048 / 2). OUT module is for the interface of Xilinx data field and Matlab data field. Out1 interface connects the current module to the upper-level model. SpectrumScope module is for the spectrum analyzer. Scope module is for scope [5]. Similarly, you can use the same approach to build the models sin(5 10 t), and cos(10 t), and the frequency control words of them are respectively 3.003125, 13.53125 and 3.003125, ROM sampling depth is 409, the beginning of start vectors are respectively sin( (0 : 4095) / 2048), sin( (0 : 4095) / 2048), sin( (0 : 4095) / 2048 / 2). Step 2, building the whole System Model. The whole System Model is shown in Figure 4. - 194 -
Communications in Information Science and Management Engineering Apr. 2013, Vol. 3 Iss. 4, PP. 192-19 Figure 4 Building the whole System Model In Figure 4, SystemGenerator module is the core module of System Generator, and Simulation module is to achieve the conversion of HDL code, the key parameters are set as: compilation for HDL Netlist file, part for Virtex5 xc5vsx95t-1ff113, synthesis tool for XST, hardware description language for VHDL, FPGA clock period for 20/3ns, simulink system period for 1/150e (sec), and so on. ResourceEstimator module is used to analysis the hardware resources needed. Four models, sin(5 10 t), cos(5 10 t), cos(10 t), are corresponding to the four models mentioned above in Figure 3, and they are all the upper-level models. The output is out1 module for every model. Mult1 module is for multiplication between cos(5 10 t) and sin(10 t). Mult2 module is for multiplication between sin(5 10 t) and cos(10 t). AddSub module is for addition between produces the signal sin(1.5 10 t) finally. sin(5 10 t) cos(10 t) and cos(5 10 t) sin(10 t). Then it IV. TESTING RESULTS A. Simulation Results The Simulink simulation parameter is set to 1024/5e, emulation mode is set to normal, then start the simulation. The spectrums of the four modules cos(5 10 t), sin(5 10 t), cos(10 t) are shown in Figure 5, and their frequencies are: 2.5 MHz, 5 MHz, 2.5 MHz, 5 MHz. Figure 5 The spectrum of the four modules The spectrum of the final signal sin(1.5 10 t) is shown in Figure. It shows that the frequency of the signal generated is.5 MHz, so the System Generator-based system model can meet the theoretical requirements [5]. - 195 -
Communications in Information Science and Management Engineering Apr. 2013, Vol. 3 Iss. 4, PP. 192-19 Figure The spectrum of the whole System Model B. Hardware Verification After simulation, we can verify the actual performance in FPGA device. Run SystemGenerator module generates standard files (Netlist), then imports the netlist into ISE12.2, compilation, synthesis, translation, map, place&route and timing analysis. When the high system frequency is needed, UCF file can be used for timing constraints, group constraints and other user constraints, and the process of place &route and constraints file modifition are repeated until it meets the requirements, then a downloadable file with configuration data is generated finally. Download it to the FPGA device, collect the final data by using the ChipScope, then analysis and validate the data. At last, we can get the answer that the actual results are consistent with the theoretical results [1]. C. Resource Usage Analysis Running ResourceEstimator module, we can get the information about the hardware resources needed by the system. The result is shown in Figure. It shows that the resource utilization is perfect for such a design. Figure Resource utilization V. COMPARISON WITH TRADITIONAL HDL HARDWARE DESIGN METHODS HDL hardware design, which is also called the traditional RTL-based design method, is divided into two parts: system-level and algorithm-level simulation and varification; hardware programming and implementation based on HDL programming language. The vast majority of algorithm design and system verification are completed in Matlab and Simulink, but this soft system level design environment cannot result in the final hardware implementation, furthermore, most developers based on algorithms are not familiar with the process of hardware programming, so a gap is formed between algorithm modeling and hardware programming implementation finally []. However, System Generator can convert the algorithm design and system simulation to the hardware programming language automatically and efficiently, which provides a good solution to the problem mentioned above. The solution based on System Generator, can greatly shorten the development cycle, improve the efficiency, and increase the rate of resources utilization, and it makes FPGA development much easier. It can also be used to design more complex systems conveniently by combining HDL hardware languages. Of course, it also has its own shortcomings. The multi-clock design and bi-directional bus are not supported here, but these shortcomings can be made up by using the skills of design based on HDL hardware programming language. - 19 -
Communications in Information Science and Management Engineering Apr. 2013, Vol. 3 Iss. 4, PP. 192-19 VI. CONCLUSION Through the experiment of digital quadrature up-conversion, this paper indicates that the System Generator-based design method can achieve the successful application in the digital quadrature up-conversion, the same to the field of digital signal processing. Compared with the traditional HDL hardware design method, as a new method, it highlights some advantages, such as strong operability, high development efficiency and resource utilization. What s more, this design provides a seamless top-down FPGA solution to the digital signal processing system designers. There is a reason to believe that, with the development of the technology, hardware design method based on System Generator will bring us higher performance. REFERENCES [1] Xu Wenbo, Tan Yin and Hu Bin. Xilinx ISE Design Suite 10.x FPGA design. POSTS TELECOM PRESS, first edition, 2008. [2] Optimization of quadrature modulator performance. RF Micro Devices, Inc., 199. [3] Kenneth W. Martin. Complex signal processing is not complex. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, pages 1823 183, 2004. [4] Dai Qing and Feng Yongxin. The design and implementation of fir filter based on system generator. ELECTRONIC TECHNOLOGY, pages 114 115, 200. [5] Ji Zhicheng and Gao Chunneng. Digital signal processing design tutorial based on FPGA introduction and improvement of System Generator. Xi an Electronic and Science University Press, first edition, 2008. [] Zhu Jiang. FPGA system-level design in the field of DSP. Jovian Test Control Tech., pages 25 20, 2000. - 19 -